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Commit | Line | Data |
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9e60fdcf | 1 | /* |
c103de24 | 2 | * PCA953x 4/8/16 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe MZ |
17 | #include <linux/interrupt.h> |
18 | #include <linux/irq.h> | |
55ecd263 | 19 | #include <linux/irqdomain.h> |
9e60fdcf | 20 | #include <linux/i2c.h> |
d1c057e3 | 21 | #include <linux/i2c/pca953x.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1965d303 NC |
23 | #ifdef CONFIG_OF_GPIO |
24 | #include <linux/of_platform.h> | |
1965d303 | 25 | #endif |
9e60fdcf | 26 | |
33226ffd HZ |
27 | #define PCA953X_INPUT 0 |
28 | #define PCA953X_OUTPUT 1 | |
29 | #define PCA953X_INVERT 2 | |
30 | #define PCA953X_DIRECTION 3 | |
31 | ||
ae79c190 AS |
32 | #define REG_ADDR_AI 0x80 |
33 | ||
33226ffd HZ |
34 | #define PCA957X_IN 0 |
35 | #define PCA957X_INVRT 1 | |
36 | #define PCA957X_BKEN 2 | |
37 | #define PCA957X_PUPD 3 | |
38 | #define PCA957X_CFG 4 | |
39 | #define PCA957X_OUT 5 | |
40 | #define PCA957X_MSK 6 | |
41 | #define PCA957X_INTS 7 | |
42 | ||
43 | #define PCA_GPIO_MASK 0x00FF | |
44 | #define PCA_INT 0x0100 | |
45 | #define PCA953X_TYPE 0x1000 | |
46 | #define PCA957X_TYPE 0x2000 | |
89ea8bbe | 47 | |
3760f736 | 48 | static const struct i2c_device_id pca953x_id[] = { |
33226ffd HZ |
49 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
50 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
51 | { "pca9536", 4 | PCA953X_TYPE, }, | |
52 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
53 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
54 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
55 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
56 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
57 | { "pca9556", 8 | PCA953X_TYPE, }, | |
58 | { "pca9557", 8 | PCA953X_TYPE, }, | |
59 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
60 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
61 | ||
62 | { "max7310", 8 | PCA953X_TYPE, }, | |
63 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
64 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
65 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
66 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, | |
67 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
68 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 69 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
3760f736 | 70 | { } |
f5e8ff48 | 71 | }; |
3760f736 | 72 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 73 | |
f3dc3630 | 74 | struct pca953x_chip { |
9e60fdcf | 75 | unsigned gpio_start; |
ae79c190 AS |
76 | u32 reg_output; |
77 | u32 reg_direction; | |
6e20fb18 | 78 | struct mutex i2c_lock; |
9e60fdcf | 79 | |
89ea8bbe MZ |
80 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
81 | struct mutex irq_lock; | |
ca3ffe91 LA |
82 | u32 irq_mask; |
83 | u32 irq_stat; | |
84 | u32 irq_trig_raise; | |
85 | u32 irq_trig_fall; | |
89ea8bbe | 86 | int irq_base; |
55ecd263 | 87 | struct irq_domain *domain; |
89ea8bbe MZ |
88 | #endif |
89 | ||
9e60fdcf | 90 | struct i2c_client *client; |
91 | struct gpio_chip gpio_chip; | |
62154991 | 92 | const char *const *names; |
33226ffd | 93 | int chip_type; |
9e60fdcf | 94 | }; |
95 | ||
ae79c190 | 96 | static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val) |
9e60fdcf | 97 | { |
33226ffd | 98 | int ret = 0; |
f5e8ff48 GL |
99 | |
100 | if (chip->gpio_chip.ngpio <= 8) | |
101 | ret = i2c_smbus_write_byte_data(chip->client, reg, val); | |
ae79c190 | 102 | else if (chip->gpio_chip.ngpio == 24) { |
96b70641 AS |
103 | cpu_to_le32s(&val); |
104 | ret = i2c_smbus_write_i2c_block_data(chip->client, | |
ae79c190 | 105 | (reg << 2) | REG_ADDR_AI, |
96b70641 AS |
106 | 3, |
107 | (u8 *) &val); | |
ae79c190 | 108 | } |
33226ffd HZ |
109 | else { |
110 | switch (chip->chip_type) { | |
111 | case PCA953X_TYPE: | |
112 | ret = i2c_smbus_write_word_data(chip->client, | |
113 | reg << 1, val); | |
114 | break; | |
115 | case PCA957X_TYPE: | |
116 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, | |
117 | val & 0xff); | |
118 | if (ret < 0) | |
119 | break; | |
120 | ret = i2c_smbus_write_byte_data(chip->client, | |
121 | (reg << 1) + 1, | |
122 | (val & 0xff00) >> 8); | |
123 | break; | |
124 | } | |
125 | } | |
f5e8ff48 GL |
126 | |
127 | if (ret < 0) { | |
128 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 129 | return ret; |
f5e8ff48 GL |
130 | } |
131 | ||
132 | return 0; | |
9e60fdcf | 133 | } |
134 | ||
ae79c190 | 135 | static int pca953x_read_reg(struct pca953x_chip *chip, int reg, u32 *val) |
9e60fdcf | 136 | { |
137 | int ret; | |
138 | ||
96b70641 | 139 | if (chip->gpio_chip.ngpio <= 8) { |
f5e8ff48 | 140 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
96b70641 | 141 | *val = ret; |
ae79c190 | 142 | } |
96b70641 AS |
143 | else if (chip->gpio_chip.ngpio == 24) { |
144 | *val = 0; | |
145 | ret = i2c_smbus_read_i2c_block_data(chip->client, | |
146 | (reg << 2) | REG_ADDR_AI, | |
147 | 3, | |
148 | (u8 *) val); | |
149 | le32_to_cpus(val); | |
150 | } else { | |
f5e8ff48 | 151 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); |
96b70641 AS |
152 | *val = ret; |
153 | } | |
f5e8ff48 | 154 | |
9e60fdcf | 155 | if (ret < 0) { |
156 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 157 | return ret; |
9e60fdcf | 158 | } |
159 | ||
9e60fdcf | 160 | return 0; |
161 | } | |
162 | ||
f3dc3630 | 163 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 164 | { |
f3dc3630 | 165 | struct pca953x_chip *chip; |
ae79c190 | 166 | uint reg_val; |
33226ffd | 167 | int ret, offset = 0; |
9e60fdcf | 168 | |
f3dc3630 | 169 | chip = container_of(gc, struct pca953x_chip, gpio_chip); |
9e60fdcf | 170 | |
6e20fb18 | 171 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 172 | reg_val = chip->reg_direction | (1u << off); |
33226ffd HZ |
173 | |
174 | switch (chip->chip_type) { | |
175 | case PCA953X_TYPE: | |
176 | offset = PCA953X_DIRECTION; | |
177 | break; | |
178 | case PCA957X_TYPE: | |
179 | offset = PCA957X_CFG; | |
180 | break; | |
181 | } | |
182 | ret = pca953x_write_reg(chip, offset, reg_val); | |
9e60fdcf | 183 | if (ret) |
6e20fb18 | 184 | goto exit; |
9e60fdcf | 185 | |
186 | chip->reg_direction = reg_val; | |
6e20fb18 RS |
187 | ret = 0; |
188 | exit: | |
189 | mutex_unlock(&chip->i2c_lock); | |
190 | return ret; | |
9e60fdcf | 191 | } |
192 | ||
f3dc3630 | 193 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 194 | unsigned off, int val) |
195 | { | |
f3dc3630 | 196 | struct pca953x_chip *chip; |
ae79c190 | 197 | uint reg_val; |
33226ffd | 198 | int ret, offset = 0; |
9e60fdcf | 199 | |
f3dc3630 | 200 | chip = container_of(gc, struct pca953x_chip, gpio_chip); |
9e60fdcf | 201 | |
6e20fb18 | 202 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 203 | /* set output level */ |
204 | if (val) | |
205 | reg_val = chip->reg_output | (1u << off); | |
206 | else | |
207 | reg_val = chip->reg_output & ~(1u << off); | |
208 | ||
33226ffd HZ |
209 | switch (chip->chip_type) { |
210 | case PCA953X_TYPE: | |
211 | offset = PCA953X_OUTPUT; | |
212 | break; | |
213 | case PCA957X_TYPE: | |
214 | offset = PCA957X_OUT; | |
215 | break; | |
216 | } | |
217 | ret = pca953x_write_reg(chip, offset, reg_val); | |
9e60fdcf | 218 | if (ret) |
6e20fb18 | 219 | goto exit; |
9e60fdcf | 220 | |
221 | chip->reg_output = reg_val; | |
222 | ||
223 | /* then direction */ | |
224 | reg_val = chip->reg_direction & ~(1u << off); | |
33226ffd HZ |
225 | switch (chip->chip_type) { |
226 | case PCA953X_TYPE: | |
227 | offset = PCA953X_DIRECTION; | |
228 | break; | |
229 | case PCA957X_TYPE: | |
230 | offset = PCA957X_CFG; | |
231 | break; | |
232 | } | |
233 | ret = pca953x_write_reg(chip, offset, reg_val); | |
9e60fdcf | 234 | if (ret) |
6e20fb18 | 235 | goto exit; |
9e60fdcf | 236 | |
237 | chip->reg_direction = reg_val; | |
6e20fb18 RS |
238 | ret = 0; |
239 | exit: | |
240 | mutex_unlock(&chip->i2c_lock); | |
241 | return ret; | |
9e60fdcf | 242 | } |
243 | ||
f3dc3630 | 244 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 245 | { |
f3dc3630 | 246 | struct pca953x_chip *chip; |
ae79c190 | 247 | u32 reg_val; |
33226ffd | 248 | int ret, offset = 0; |
9e60fdcf | 249 | |
f3dc3630 | 250 | chip = container_of(gc, struct pca953x_chip, gpio_chip); |
9e60fdcf | 251 | |
6e20fb18 | 252 | mutex_lock(&chip->i2c_lock); |
33226ffd HZ |
253 | switch (chip->chip_type) { |
254 | case PCA953X_TYPE: | |
255 | offset = PCA953X_INPUT; | |
256 | break; | |
257 | case PCA957X_TYPE: | |
258 | offset = PCA957X_IN; | |
259 | break; | |
260 | } | |
261 | ret = pca953x_read_reg(chip, offset, ®_val); | |
6e20fb18 | 262 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 263 | if (ret < 0) { |
264 | /* NOTE: diagnostic already emitted; that's all we should | |
265 | * do unless gpio_*_value_cansleep() calls become different | |
266 | * from their nonsleeping siblings (and report faults). | |
267 | */ | |
268 | return 0; | |
269 | } | |
270 | ||
271 | return (reg_val & (1u << off)) ? 1 : 0; | |
272 | } | |
273 | ||
f3dc3630 | 274 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 275 | { |
f3dc3630 | 276 | struct pca953x_chip *chip; |
ae79c190 | 277 | u32 reg_val; |
33226ffd | 278 | int ret, offset = 0; |
9e60fdcf | 279 | |
f3dc3630 | 280 | chip = container_of(gc, struct pca953x_chip, gpio_chip); |
9e60fdcf | 281 | |
6e20fb18 | 282 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 283 | if (val) |
284 | reg_val = chip->reg_output | (1u << off); | |
285 | else | |
286 | reg_val = chip->reg_output & ~(1u << off); | |
287 | ||
33226ffd HZ |
288 | switch (chip->chip_type) { |
289 | case PCA953X_TYPE: | |
290 | offset = PCA953X_OUTPUT; | |
291 | break; | |
292 | case PCA957X_TYPE: | |
293 | offset = PCA957X_OUT; | |
294 | break; | |
295 | } | |
296 | ret = pca953x_write_reg(chip, offset, reg_val); | |
9e60fdcf | 297 | if (ret) |
6e20fb18 | 298 | goto exit; |
9e60fdcf | 299 | |
300 | chip->reg_output = reg_val; | |
6e20fb18 RS |
301 | exit: |
302 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 303 | } |
304 | ||
f5e8ff48 | 305 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 306 | { |
307 | struct gpio_chip *gc; | |
308 | ||
309 | gc = &chip->gpio_chip; | |
310 | ||
f3dc3630 GL |
311 | gc->direction_input = pca953x_gpio_direction_input; |
312 | gc->direction_output = pca953x_gpio_direction_output; | |
313 | gc->get = pca953x_gpio_get_value; | |
314 | gc->set = pca953x_gpio_set_value; | |
84207805 | 315 | gc->can_sleep = 1; |
9e60fdcf | 316 | |
317 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
318 | gc->ngpio = gpios; |
319 | gc->label = chip->client->name; | |
d8f388d8 | 320 | gc->dev = &chip->client->dev; |
d72cbed0 | 321 | gc->owner = THIS_MODULE; |
77906a54 | 322 | gc->names = chip->names; |
9e60fdcf | 323 | } |
324 | ||
89ea8bbe MZ |
325 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
326 | static int pca953x_gpio_to_irq(struct gpio_chip *gc, unsigned off) | |
327 | { | |
328 | struct pca953x_chip *chip; | |
329 | ||
330 | chip = container_of(gc, struct pca953x_chip, gpio_chip); | |
331 | return chip->irq_base + off; | |
332 | } | |
333 | ||
6f5cfc0e | 334 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 335 | { |
6f5cfc0e | 336 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
89ea8bbe | 337 | |
55ecd263 | 338 | chip->irq_mask &= ~(1 << d->hwirq); |
89ea8bbe MZ |
339 | } |
340 | ||
6f5cfc0e | 341 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 342 | { |
6f5cfc0e | 343 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
89ea8bbe | 344 | |
55ecd263 | 345 | chip->irq_mask |= 1 << d->hwirq; |
89ea8bbe MZ |
346 | } |
347 | ||
6f5cfc0e | 348 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 349 | { |
6f5cfc0e | 350 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
89ea8bbe MZ |
351 | |
352 | mutex_lock(&chip->irq_lock); | |
353 | } | |
354 | ||
6f5cfc0e | 355 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 356 | { |
6f5cfc0e | 357 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
ca3ffe91 LA |
358 | u32 new_irqs; |
359 | u32 level; | |
a2cb9aeb MZ |
360 | |
361 | /* Look for any newly setup interrupt */ | |
362 | new_irqs = chip->irq_trig_fall | chip->irq_trig_raise; | |
363 | new_irqs &= ~chip->reg_direction; | |
364 | ||
365 | while (new_irqs) { | |
366 | level = __ffs(new_irqs); | |
367 | pca953x_gpio_direction_input(&chip->gpio_chip, level); | |
368 | new_irqs &= ~(1 << level); | |
369 | } | |
89ea8bbe MZ |
370 | |
371 | mutex_unlock(&chip->irq_lock); | |
372 | } | |
373 | ||
6f5cfc0e | 374 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 375 | { |
6f5cfc0e | 376 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); |
55ecd263 | 377 | u32 mask = 1 << d->hwirq; |
89ea8bbe MZ |
378 | |
379 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
380 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 381 | d->irq, type); |
89ea8bbe MZ |
382 | return -EINVAL; |
383 | } | |
384 | ||
385 | if (type & IRQ_TYPE_EDGE_FALLING) | |
386 | chip->irq_trig_fall |= mask; | |
387 | else | |
388 | chip->irq_trig_fall &= ~mask; | |
389 | ||
390 | if (type & IRQ_TYPE_EDGE_RISING) | |
391 | chip->irq_trig_raise |= mask; | |
392 | else | |
393 | chip->irq_trig_raise &= ~mask; | |
394 | ||
a2cb9aeb | 395 | return 0; |
89ea8bbe MZ |
396 | } |
397 | ||
398 | static struct irq_chip pca953x_irq_chip = { | |
399 | .name = "pca953x", | |
6f5cfc0e LB |
400 | .irq_mask = pca953x_irq_mask, |
401 | .irq_unmask = pca953x_irq_unmask, | |
402 | .irq_bus_lock = pca953x_irq_bus_lock, | |
403 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
404 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
405 | }; |
406 | ||
ca3ffe91 | 407 | static u32 pca953x_irq_pending(struct pca953x_chip *chip) |
89ea8bbe | 408 | { |
ae79c190 | 409 | u32 cur_stat; |
ca3ffe91 LA |
410 | u32 old_stat; |
411 | u32 pending; | |
412 | u32 trigger; | |
33226ffd HZ |
413 | int ret, offset = 0; |
414 | ||
415 | switch (chip->chip_type) { | |
416 | case PCA953X_TYPE: | |
417 | offset = PCA953X_INPUT; | |
418 | break; | |
419 | case PCA957X_TYPE: | |
420 | offset = PCA957X_IN; | |
421 | break; | |
422 | } | |
423 | ret = pca953x_read_reg(chip, offset, &cur_stat); | |
89ea8bbe MZ |
424 | if (ret) |
425 | return 0; | |
426 | ||
427 | /* Remove output pins from the equation */ | |
428 | cur_stat &= chip->reg_direction; | |
429 | ||
430 | old_stat = chip->irq_stat; | |
431 | trigger = (cur_stat ^ old_stat) & chip->irq_mask; | |
432 | ||
433 | if (!trigger) | |
434 | return 0; | |
435 | ||
436 | chip->irq_stat = cur_stat; | |
437 | ||
438 | pending = (old_stat & chip->irq_trig_fall) | | |
439 | (cur_stat & chip->irq_trig_raise); | |
440 | pending &= trigger; | |
441 | ||
442 | return pending; | |
443 | } | |
444 | ||
445 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
446 | { | |
447 | struct pca953x_chip *chip = devid; | |
ca3ffe91 LA |
448 | u32 pending; |
449 | u32 level; | |
89ea8bbe MZ |
450 | |
451 | pending = pca953x_irq_pending(chip); | |
452 | ||
453 | if (!pending) | |
454 | return IRQ_HANDLED; | |
455 | ||
456 | do { | |
457 | level = __ffs(pending); | |
55ecd263 | 458 | handle_nested_irq(irq_find_mapping(chip->domain, level)); |
89ea8bbe MZ |
459 | |
460 | pending &= ~(1 << level); | |
461 | } while (pending); | |
462 | ||
463 | return IRQ_HANDLED; | |
464 | } | |
465 | ||
466 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 DJ |
467 | const struct i2c_device_id *id, |
468 | int irq_base) | |
89ea8bbe MZ |
469 | { |
470 | struct i2c_client *client = chip->client; | |
33226ffd | 471 | int ret, offset = 0; |
ae79c190 | 472 | u32 temporary; |
89ea8bbe | 473 | |
c6dcf592 | 474 | if (irq_base != -1 |
33226ffd | 475 | && (id->driver_data & PCA_INT)) { |
89ea8bbe MZ |
476 | int lvl; |
477 | ||
33226ffd HZ |
478 | switch (chip->chip_type) { |
479 | case PCA953X_TYPE: | |
480 | offset = PCA953X_INPUT; | |
481 | break; | |
482 | case PCA957X_TYPE: | |
483 | offset = PCA957X_IN; | |
484 | break; | |
485 | } | |
ae79c190 AS |
486 | ret = pca953x_read_reg(chip, offset, &temporary); |
487 | chip->irq_stat = temporary; | |
89ea8bbe MZ |
488 | if (ret) |
489 | goto out_failed; | |
490 | ||
491 | /* | |
492 | * There is no way to know which GPIO line generated the | |
493 | * interrupt. We have to rely on the previous read for | |
494 | * this purpose. | |
495 | */ | |
496 | chip->irq_stat &= chip->reg_direction; | |
89ea8bbe MZ |
497 | mutex_init(&chip->irq_lock); |
498 | ||
c6dcf592 | 499 | chip->irq_base = irq_alloc_descs(-1, irq_base, chip->gpio_chip.ngpio, -1); |
910c8fb6 DJ |
500 | if (chip->irq_base < 0) |
501 | goto out_failed; | |
502 | ||
55ecd263 MR |
503 | chip->domain = irq_domain_add_legacy(client->dev.of_node, |
504 | chip->gpio_chip.ngpio, | |
505 | chip->irq_base, | |
506 | 0, | |
507 | &irq_domain_simple_ops, | |
508 | NULL); | |
509 | if (!chip->domain) { | |
510 | ret = -ENODEV; | |
511 | goto out_irqdesc_free; | |
512 | } | |
513 | ||
89ea8bbe MZ |
514 | for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) { |
515 | int irq = lvl + chip->irq_base; | |
516 | ||
910c8fb6 | 517 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
b51804bc | 518 | irq_set_chip_data(irq, chip); |
6dd599f8 DJ |
519 | irq_set_chip(irq, &pca953x_irq_chip); |
520 | irq_set_nested_thread(irq, true); | |
89ea8bbe MZ |
521 | #ifdef CONFIG_ARM |
522 | set_irq_flags(irq, IRQF_VALID); | |
523 | #else | |
b51804bc | 524 | irq_set_noprobe(irq); |
89ea8bbe MZ |
525 | #endif |
526 | } | |
527 | ||
528 | ret = request_threaded_irq(client->irq, | |
529 | NULL, | |
530 | pca953x_irq_handler, | |
17e8b42c | 531 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, |
89ea8bbe MZ |
532 | dev_name(&client->dev), chip); |
533 | if (ret) { | |
534 | dev_err(&client->dev, "failed to request irq %d\n", | |
535 | client->irq); | |
55ecd263 | 536 | goto out_irqdesc_free; |
89ea8bbe MZ |
537 | } |
538 | ||
539 | chip->gpio_chip.to_irq = pca953x_gpio_to_irq; | |
540 | } | |
541 | ||
542 | return 0; | |
543 | ||
55ecd263 MR |
544 | out_irqdesc_free: |
545 | irq_free_descs(chip->irq_base, chip->gpio_chip.ngpio); | |
89ea8bbe | 546 | out_failed: |
8a233f01 | 547 | chip->irq_base = -1; |
89ea8bbe MZ |
548 | return ret; |
549 | } | |
550 | ||
551 | static void pca953x_irq_teardown(struct pca953x_chip *chip) | |
552 | { | |
c609c05d DJ |
553 | if (chip->irq_base != -1) { |
554 | irq_free_descs(chip->irq_base, chip->gpio_chip.ngpio); | |
89ea8bbe | 555 | free_irq(chip->client->irq, chip); |
c609c05d | 556 | } |
89ea8bbe MZ |
557 | } |
558 | #else /* CONFIG_GPIO_PCA953X_IRQ */ | |
559 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 DJ |
560 | const struct i2c_device_id *id, |
561 | int irq_base) | |
89ea8bbe MZ |
562 | { |
563 | struct i2c_client *client = chip->client; | |
89ea8bbe | 564 | |
c6dcf592 | 565 | if (irq_base != -1 && (id->driver_data & PCA_INT)) |
89ea8bbe MZ |
566 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
571 | static void pca953x_irq_teardown(struct pca953x_chip *chip) | |
572 | { | |
573 | } | |
574 | #endif | |
575 | ||
1965d303 NC |
576 | /* |
577 | * Handlers for alternative sources of platform_data | |
578 | */ | |
579 | #ifdef CONFIG_OF_GPIO | |
580 | /* | |
581 | * Translate OpenFirmware node properties into platform_data | |
a57339b4 | 582 | * WARNING: This is DEPRECATED and will be removed eventually! |
1965d303 | 583 | */ |
404ba2b8 | 584 | static void |
6a7b36aa | 585 | pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert) |
1965d303 | 586 | { |
1965d303 | 587 | struct device_node *node; |
1648237d DE |
588 | const __be32 *val; |
589 | int size; | |
1965d303 | 590 | |
61c7a080 | 591 | node = client->dev.of_node; |
1965d303 | 592 | if (node == NULL) |
c6dcf592 | 593 | return; |
1965d303 | 594 | |
c6dcf592 | 595 | *gpio_base = -1; |
1648237d | 596 | val = of_get_property(node, "linux,gpio-base", &size); |
a57339b4 | 597 | WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__); |
1965d303 | 598 | if (val) { |
1648237d DE |
599 | if (size != sizeof(*val)) |
600 | dev_warn(&client->dev, "%s: wrong linux,gpio-base\n", | |
601 | node->full_name); | |
1965d303 | 602 | else |
c6dcf592 | 603 | *gpio_base = be32_to_cpup(val); |
1965d303 NC |
604 | } |
605 | ||
606 | val = of_get_property(node, "polarity", NULL); | |
a57339b4 | 607 | WARN(val, "%s: device-tree property 'polarity' is deprecated!", __func__); |
1965d303 | 608 | if (val) |
c6dcf592 | 609 | *invert = *val; |
1965d303 NC |
610 | } |
611 | #else | |
404ba2b8 | 612 | static void |
6a7b36aa | 613 | pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert) |
1965d303 | 614 | { |
25fcf2b7 | 615 | *gpio_base = -1; |
1965d303 NC |
616 | } |
617 | #endif | |
618 | ||
3836309d | 619 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
620 | { |
621 | int ret; | |
622 | ||
623 | ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output); | |
624 | if (ret) | |
625 | goto out; | |
626 | ||
627 | ret = pca953x_read_reg(chip, PCA953X_DIRECTION, | |
628 | &chip->reg_direction); | |
629 | if (ret) | |
630 | goto out; | |
631 | ||
632 | /* set platform specific polarity inversion */ | |
633 | ret = pca953x_write_reg(chip, PCA953X_INVERT, invert); | |
33226ffd HZ |
634 | out: |
635 | return ret; | |
636 | } | |
637 | ||
3836309d | 638 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
639 | { |
640 | int ret; | |
ae79c190 | 641 | u32 val = 0; |
33226ffd HZ |
642 | |
643 | /* Let every port in proper state, that could save power */ | |
644 | pca953x_write_reg(chip, PCA957X_PUPD, 0x0); | |
645 | pca953x_write_reg(chip, PCA957X_CFG, 0xffff); | |
646 | pca953x_write_reg(chip, PCA957X_OUT, 0x0); | |
647 | ||
648 | ret = pca953x_read_reg(chip, PCA957X_IN, &val); | |
649 | if (ret) | |
650 | goto out; | |
651 | ret = pca953x_read_reg(chip, PCA957X_OUT, &chip->reg_output); | |
652 | if (ret) | |
653 | goto out; | |
654 | ret = pca953x_read_reg(chip, PCA957X_CFG, &chip->reg_direction); | |
655 | if (ret) | |
656 | goto out; | |
657 | ||
658 | /* set platform specific polarity inversion */ | |
659 | pca953x_write_reg(chip, PCA957X_INVRT, invert); | |
660 | ||
661 | /* To enable register 6, 7 to controll pull up and pull down */ | |
662 | pca953x_write_reg(chip, PCA957X_BKEN, 0x202); | |
663 | ||
664 | return 0; | |
665 | out: | |
666 | return ret; | |
667 | } | |
668 | ||
3836309d | 669 | static int pca953x_probe(struct i2c_client *client, |
3760f736 | 670 | const struct i2c_device_id *id) |
9e60fdcf | 671 | { |
f3dc3630 GL |
672 | struct pca953x_platform_data *pdata; |
673 | struct pca953x_chip *chip; | |
6a7b36aa | 674 | int irq_base = 0; |
7ea2aa20 | 675 | int ret; |
6a7b36aa | 676 | u32 invert = 0; |
9e60fdcf | 677 | |
1965d303 NC |
678 | chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL); |
679 | if (chip == NULL) | |
680 | return -ENOMEM; | |
681 | ||
9e60fdcf | 682 | pdata = client->dev.platform_data; |
c6dcf592 DJ |
683 | if (pdata) { |
684 | irq_base = pdata->irq_base; | |
685 | chip->gpio_start = pdata->gpio_base; | |
686 | invert = pdata->invert; | |
687 | chip->names = pdata->names; | |
688 | } else { | |
689 | pca953x_get_alt_pdata(client, &chip->gpio_start, &invert); | |
a57339b4 DJ |
690 | #ifdef CONFIG_OF_GPIO |
691 | /* If I2C node has no interrupts property, disable GPIO interrupts */ | |
692 | if (of_find_property(client->dev.of_node, "interrupts", NULL) == NULL) | |
693 | irq_base = -1; | |
694 | #endif | |
1965d303 | 695 | } |
9e60fdcf | 696 | |
697 | chip->client = client; | |
698 | ||
33226ffd | 699 | chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE); |
77906a54 | 700 | |
6e20fb18 RS |
701 | mutex_init(&chip->i2c_lock); |
702 | ||
9e60fdcf | 703 | /* initialize cached registers from their original values. |
704 | * we can't share this chip with another i2c master. | |
705 | */ | |
33226ffd | 706 | pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 707 | |
33226ffd | 708 | if (chip->chip_type == PCA953X_TYPE) |
7ea2aa20 | 709 | ret = device_pca953x_init(chip, invert); |
33226ffd | 710 | else |
7ea2aa20 WS |
711 | ret = device_pca957x_init(chip, invert); |
712 | if (ret) | |
9e60fdcf | 713 | goto out_failed; |
714 | ||
c6dcf592 | 715 | ret = pca953x_irq_setup(chip, id, irq_base); |
89ea8bbe MZ |
716 | if (ret) |
717 | goto out_failed; | |
f5e8ff48 GL |
718 | |
719 | ret = gpiochip_add(&chip->gpio_chip); | |
9e60fdcf | 720 | if (ret) |
272df502 | 721 | goto out_failed_irq; |
9e60fdcf | 722 | |
c6dcf592 | 723 | if (pdata && pdata->setup) { |
9e60fdcf | 724 | ret = pdata->setup(client, chip->gpio_chip.base, |
725 | chip->gpio_chip.ngpio, pdata->context); | |
726 | if (ret < 0) | |
727 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
728 | } | |
729 | ||
730 | i2c_set_clientdata(client, chip); | |
731 | return 0; | |
732 | ||
272df502 | 733 | out_failed_irq: |
89ea8bbe | 734 | pca953x_irq_teardown(chip); |
272df502 | 735 | out_failed: |
9e60fdcf | 736 | kfree(chip); |
737 | return ret; | |
738 | } | |
739 | ||
f3dc3630 | 740 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 741 | { |
f3dc3630 GL |
742 | struct pca953x_platform_data *pdata = client->dev.platform_data; |
743 | struct pca953x_chip *chip = i2c_get_clientdata(client); | |
9e60fdcf | 744 | int ret = 0; |
745 | ||
c6dcf592 | 746 | if (pdata && pdata->teardown) { |
9e60fdcf | 747 | ret = pdata->teardown(client, chip->gpio_chip.base, |
748 | chip->gpio_chip.ngpio, pdata->context); | |
749 | if (ret < 0) { | |
750 | dev_err(&client->dev, "%s failed, %d\n", | |
751 | "teardown", ret); | |
752 | return ret; | |
753 | } | |
754 | } | |
755 | ||
756 | ret = gpiochip_remove(&chip->gpio_chip); | |
757 | if (ret) { | |
758 | dev_err(&client->dev, "%s failed, %d\n", | |
759 | "gpiochip_remove()", ret); | |
760 | return ret; | |
761 | } | |
762 | ||
89ea8bbe | 763 | pca953x_irq_teardown(chip); |
9e60fdcf | 764 | kfree(chip); |
765 | return 0; | |
766 | } | |
767 | ||
ed32620e MR |
768 | static const struct of_device_id pca953x_dt_ids[] = { |
769 | { .compatible = "nxp,pca9534", }, | |
770 | { .compatible = "nxp,pca9535", }, | |
771 | { .compatible = "nxp,pca9536", }, | |
772 | { .compatible = "nxp,pca9537", }, | |
773 | { .compatible = "nxp,pca9538", }, | |
774 | { .compatible = "nxp,pca9539", }, | |
775 | { .compatible = "nxp,pca9554", }, | |
776 | { .compatible = "nxp,pca9555", }, | |
777 | { .compatible = "nxp,pca9556", }, | |
778 | { .compatible = "nxp,pca9557", }, | |
779 | { .compatible = "nxp,pca9574", }, | |
780 | { .compatible = "nxp,pca9575", }, | |
781 | ||
782 | { .compatible = "maxim,max7310", }, | |
783 | { .compatible = "maxim,max7312", }, | |
784 | { .compatible = "maxim,max7313", }, | |
785 | { .compatible = "maxim,max7315", }, | |
786 | ||
787 | { .compatible = "ti,pca6107", }, | |
788 | { .compatible = "ti,tca6408", }, | |
789 | { .compatible = "ti,tca6416", }, | |
790 | { .compatible = "ti,tca6424", }, | |
791 | { } | |
792 | }; | |
793 | ||
794 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
795 | ||
f3dc3630 | 796 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 797 | .driver = { |
f3dc3630 | 798 | .name = "pca953x", |
ed32620e | 799 | .of_match_table = pca953x_dt_ids, |
9e60fdcf | 800 | }, |
f3dc3630 GL |
801 | .probe = pca953x_probe, |
802 | .remove = pca953x_remove, | |
3760f736 | 803 | .id_table = pca953x_id, |
9e60fdcf | 804 | }; |
805 | ||
f3dc3630 | 806 | static int __init pca953x_init(void) |
9e60fdcf | 807 | { |
f3dc3630 | 808 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 809 | } |
2f8d1197 DB |
810 | /* register after i2c postcore initcall and before |
811 | * subsys initcalls that may rely on these GPIOs | |
812 | */ | |
813 | subsys_initcall(pca953x_init); | |
9e60fdcf | 814 | |
f3dc3630 | 815 | static void __exit pca953x_exit(void) |
9e60fdcf | 816 | { |
f3dc3630 | 817 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 818 | } |
f3dc3630 | 819 | module_exit(pca953x_exit); |
9e60fdcf | 820 | |
821 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 822 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 823 | MODULE_LICENSE("GPL"); |