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Commit | Line | Data |
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9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe | 17 | #include <linux/interrupt.h> |
9e60fdcf | 18 | #include <linux/i2c.h> |
5877457a | 19 | #include <linux/platform_data/pca953x.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
9b8e3ec3 | 21 | #include <asm/unaligned.h> |
1965d303 | 22 | #include <linux/of_platform.h> |
f32517bf | 23 | #include <linux/acpi.h> |
e23efa31 | 24 | #include <linux/regulator/consumer.h> |
9e60fdcf | 25 | |
33226ffd HZ |
26 | #define PCA953X_INPUT 0 |
27 | #define PCA953X_OUTPUT 1 | |
28 | #define PCA953X_INVERT 2 | |
29 | #define PCA953X_DIRECTION 3 | |
30 | ||
ae79c190 AS |
31 | #define REG_ADDR_AI 0x80 |
32 | ||
33226ffd HZ |
33 | #define PCA957X_IN 0 |
34 | #define PCA957X_INVRT 1 | |
35 | #define PCA957X_BKEN 2 | |
36 | #define PCA957X_PUPD 3 | |
37 | #define PCA957X_CFG 4 | |
38 | #define PCA957X_OUT 5 | |
39 | #define PCA957X_MSK 6 | |
40 | #define PCA957X_INTS 7 | |
41 | ||
44896bea YL |
42 | #define PCAL953X_IN_LATCH 34 |
43 | #define PCAL953X_INT_MASK 37 | |
44 | #define PCAL953X_INT_STAT 38 | |
45 | ||
33226ffd HZ |
46 | #define PCA_GPIO_MASK 0x00FF |
47 | #define PCA_INT 0x0100 | |
8c7a92da | 48 | #define PCA_PCAL 0x0200 |
33226ffd HZ |
49 | #define PCA953X_TYPE 0x1000 |
50 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
51 | #define PCA_TYPE_MASK 0xF000 |
52 | ||
53 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 54 | |
3760f736 | 55 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 56 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
57 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
58 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
59 | { "pca9536", 4 | PCA953X_TYPE, }, | |
60 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
61 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
62 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
63 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
64 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
65 | { "pca9556", 8 | PCA953X_TYPE, }, | |
66 | { "pca9557", 8 | PCA953X_TYPE, }, | |
67 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
68 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 69 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 70 | |
747e42a1 AS |
71 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
72 | ||
33226ffd HZ |
73 | { "max7310", 8 | PCA953X_TYPE, }, |
74 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
75 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
76 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
77 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, | |
78 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
79 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 80 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 81 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 82 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 83 | { } |
f5e8ff48 | 84 | }; |
3760f736 | 85 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 86 | |
f32517bf | 87 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
44896bea | 88 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
f32517bf AS |
89 | { } |
90 | }; | |
91 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
92 | ||
f5f0b7aa GC |
93 | #define MAX_BANK 5 |
94 | #define BANK_SZ 8 | |
95 | ||
a246b819 | 96 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 97 | |
53661f3b BG |
98 | struct pca953x_reg_config { |
99 | int direction; | |
100 | int output; | |
101 | int input; | |
102 | }; | |
103 | ||
104 | static const struct pca953x_reg_config pca953x_regs = { | |
105 | .direction = PCA953X_DIRECTION, | |
106 | .output = PCA953X_OUTPUT, | |
107 | .input = PCA953X_INPUT, | |
108 | }; | |
109 | ||
110 | static const struct pca953x_reg_config pca957x_regs = { | |
111 | .direction = PCA957X_CFG, | |
112 | .output = PCA957X_OUT, | |
113 | .input = PCA957X_IN, | |
114 | }; | |
115 | ||
f3dc3630 | 116 | struct pca953x_chip { |
9e60fdcf | 117 | unsigned gpio_start; |
f5f0b7aa GC |
118 | u8 reg_output[MAX_BANK]; |
119 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 120 | struct mutex i2c_lock; |
9e60fdcf | 121 | |
89ea8bbe MZ |
122 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
123 | struct mutex irq_lock; | |
f5f0b7aa GC |
124 | u8 irq_mask[MAX_BANK]; |
125 | u8 irq_stat[MAX_BANK]; | |
126 | u8 irq_trig_raise[MAX_BANK]; | |
127 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
128 | #endif |
129 | ||
9e60fdcf | 130 | struct i2c_client *client; |
131 | struct gpio_chip gpio_chip; | |
62154991 | 132 | const char *const *names; |
c6664149 | 133 | unsigned long driver_data; |
e23efa31 | 134 | struct regulator *regulator; |
53661f3b BG |
135 | |
136 | const struct pca953x_reg_config *regs; | |
7acc66e3 BG |
137 | |
138 | int (*write_regs)(struct pca953x_chip *, int, u8 *); | |
c6e3cf01 | 139 | int (*read_regs)(struct pca953x_chip *, int, u8 *); |
9e60fdcf | 140 | }; |
141 | ||
f5f0b7aa GC |
142 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
143 | int off) | |
144 | { | |
145 | int ret; | |
146 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
147 | int offset = off / BANK_SZ; | |
148 | ||
149 | ret = i2c_smbus_read_byte_data(chip->client, | |
150 | (reg << bank_shift) + offset); | |
151 | *val = ret; | |
152 | ||
153 | if (ret < 0) { | |
154 | dev_err(&chip->client->dev, "failed reading register\n"); | |
155 | return ret; | |
156 | } | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
162 | int off) | |
163 | { | |
8c7a92da | 164 | int ret; |
f5f0b7aa GC |
165 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
166 | int offset = off / BANK_SZ; | |
167 | ||
168 | ret = i2c_smbus_write_byte_data(chip->client, | |
169 | (reg << bank_shift) + offset, val); | |
170 | ||
171 | if (ret < 0) { | |
172 | dev_err(&chip->client->dev, "failed writing register\n"); | |
173 | return ret; | |
174 | } | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
7acc66e3 | 179 | static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 180 | { |
7acc66e3 BG |
181 | return i2c_smbus_write_byte_data(chip->client, reg, *val); |
182 | } | |
f5e8ff48 | 183 | |
7acc66e3 BG |
184 | static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) |
185 | { | |
186 | __le16 word = cpu_to_le16(get_unaligned((u16 *)val)); | |
c4d1cbd7 | 187 | |
7acc66e3 BG |
188 | return i2c_smbus_write_word_data(chip->client, |
189 | reg << 1, (__force u16)word); | |
190 | } | |
191 | ||
192 | static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) | |
193 | { | |
194 | int ret; | |
195 | ||
196 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]); | |
197 | if (ret < 0) | |
198 | return ret; | |
199 | ||
200 | return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]); | |
201 | } | |
f5e8ff48 | 202 | |
7acc66e3 BG |
203 | static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) |
204 | { | |
205 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
206 | ||
207 | return i2c_smbus_write_i2c_block_data(chip->client, | |
208 | (reg << bank_shift) | REG_ADDR_AI, | |
209 | NBANK(chip), val); | |
210 | } | |
211 | ||
212 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
213 | { | |
214 | int ret = 0; | |
215 | ||
216 | ret = chip->write_regs(chip, reg, val); | |
f5e8ff48 GL |
217 | if (ret < 0) { |
218 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 219 | return ret; |
f5e8ff48 GL |
220 | } |
221 | ||
222 | return 0; | |
9e60fdcf | 223 | } |
224 | ||
c6e3cf01 | 225 | static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 226 | { |
227 | int ret; | |
228 | ||
c6e3cf01 BG |
229 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
230 | *val = ret; | |
f5f0b7aa | 231 | |
c6e3cf01 BG |
232 | return ret; |
233 | } | |
234 | ||
235 | static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val) | |
236 | { | |
237 | int ret; | |
238 | ||
239 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); | |
240 | val[0] = (u16)ret & 0xFF; | |
241 | val[1] = (u16)ret >> 8; | |
242 | ||
243 | return ret; | |
244 | } | |
245 | ||
246 | static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val) | |
247 | { | |
248 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
249 | ||
250 | return i2c_smbus_read_i2c_block_data(chip->client, | |
251 | (reg << bank_shift) | REG_ADDR_AI, | |
252 | NBANK(chip), val); | |
253 | } | |
254 | ||
255 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
256 | { | |
257 | int ret; | |
258 | ||
259 | ret = chip->read_regs(chip, reg, val); | |
9e60fdcf | 260 | if (ret < 0) { |
261 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 262 | return ret; |
9e60fdcf | 263 | } |
264 | ||
9e60fdcf | 265 | return 0; |
266 | } | |
267 | ||
f3dc3630 | 268 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 269 | { |
468e67f6 | 270 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 271 | u8 reg_val; |
53661f3b | 272 | int ret; |
9e60fdcf | 273 | |
6e20fb18 | 274 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 275 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd | 276 | |
53661f3b | 277 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 278 | if (ret) |
6e20fb18 | 279 | goto exit; |
9e60fdcf | 280 | |
f5f0b7aa | 281 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
282 | exit: |
283 | mutex_unlock(&chip->i2c_lock); | |
284 | return ret; | |
9e60fdcf | 285 | } |
286 | ||
f3dc3630 | 287 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 288 | unsigned off, int val) |
289 | { | |
468e67f6 | 290 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 291 | u8 reg_val; |
53661f3b | 292 | int ret; |
9e60fdcf | 293 | |
6e20fb18 | 294 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 295 | /* set output level */ |
296 | if (val) | |
f5f0b7aa GC |
297 | reg_val = chip->reg_output[off / BANK_SZ] |
298 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 299 | else |
f5f0b7aa GC |
300 | reg_val = chip->reg_output[off / BANK_SZ] |
301 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 302 | |
53661f3b | 303 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 304 | if (ret) |
6e20fb18 | 305 | goto exit; |
9e60fdcf | 306 | |
f5f0b7aa | 307 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 308 | |
309 | /* then direction */ | |
f5f0b7aa | 310 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
53661f3b | 311 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 312 | if (ret) |
6e20fb18 | 313 | goto exit; |
9e60fdcf | 314 | |
f5f0b7aa | 315 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
316 | exit: |
317 | mutex_unlock(&chip->i2c_lock); | |
318 | return ret; | |
9e60fdcf | 319 | } |
320 | ||
f3dc3630 | 321 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 322 | { |
468e67f6 | 323 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ae79c190 | 324 | u32 reg_val; |
53661f3b | 325 | int ret; |
9e60fdcf | 326 | |
6e20fb18 | 327 | mutex_lock(&chip->i2c_lock); |
53661f3b | 328 | ret = pca953x_read_single(chip, chip->regs->input, ®_val, off); |
6e20fb18 | 329 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 330 | if (ret < 0) { |
331 | /* NOTE: diagnostic already emitted; that's all we should | |
332 | * do unless gpio_*_value_cansleep() calls become different | |
333 | * from their nonsleeping siblings (and report faults). | |
334 | */ | |
335 | return 0; | |
336 | } | |
337 | ||
40a625da | 338 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 339 | } |
340 | ||
f3dc3630 | 341 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 342 | { |
468e67f6 | 343 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 344 | u8 reg_val; |
53661f3b | 345 | int ret; |
9e60fdcf | 346 | |
6e20fb18 | 347 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 348 | if (val) |
f5f0b7aa GC |
349 | reg_val = chip->reg_output[off / BANK_SZ] |
350 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 351 | else |
f5f0b7aa GC |
352 | reg_val = chip->reg_output[off / BANK_SZ] |
353 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 354 | |
53661f3b | 355 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 356 | if (ret) |
6e20fb18 | 357 | goto exit; |
9e60fdcf | 358 | |
f5f0b7aa | 359 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
360 | exit: |
361 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 362 | } |
363 | ||
b4818afe PR |
364 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
365 | unsigned long *mask, unsigned long *bits) | |
366 | { | |
468e67f6 | 367 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
b4818afe | 368 | u8 reg_val[MAX_BANK]; |
53661f3b | 369 | int ret; |
b4818afe PR |
370 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
371 | int bank; | |
372 | ||
b4818afe PR |
373 | memcpy(reg_val, chip->reg_output, NBANK(chip)); |
374 | mutex_lock(&chip->i2c_lock); | |
375 | for(bank=0; bank<NBANK(chip); bank++) { | |
e0a8604f GU |
376 | unsigned bankmask = mask[bank / sizeof(*mask)] >> |
377 | ((bank % sizeof(*mask)) * 8); | |
b4818afe | 378 | if(bankmask) { |
e0a8604f GU |
379 | unsigned bankval = bits[bank / sizeof(*bits)] >> |
380 | ((bank % sizeof(*bits)) * 8); | |
b4818afe PR |
381 | reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval; |
382 | } | |
383 | } | |
53661f3b BG |
384 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
385 | chip->regs->output << bank_shift, | |
386 | NBANK(chip), reg_val); | |
b4818afe PR |
387 | if (ret) |
388 | goto exit; | |
389 | ||
390 | memcpy(chip->reg_output, reg_val, NBANK(chip)); | |
391 | exit: | |
392 | mutex_unlock(&chip->i2c_lock); | |
393 | } | |
394 | ||
f5e8ff48 | 395 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 396 | { |
397 | struct gpio_chip *gc; | |
398 | ||
399 | gc = &chip->gpio_chip; | |
400 | ||
f3dc3630 GL |
401 | gc->direction_input = pca953x_gpio_direction_input; |
402 | gc->direction_output = pca953x_gpio_direction_output; | |
403 | gc->get = pca953x_gpio_get_value; | |
404 | gc->set = pca953x_gpio_set_value; | |
b4818afe | 405 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 406 | gc->can_sleep = true; |
9e60fdcf | 407 | |
408 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
409 | gc->ngpio = gpios; |
410 | gc->label = chip->client->name; | |
58383c78 | 411 | gc->parent = &chip->client->dev; |
d72cbed0 | 412 | gc->owner = THIS_MODULE; |
77906a54 | 413 | gc->names = chip->names; |
9e60fdcf | 414 | } |
415 | ||
89ea8bbe | 416 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 417 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 418 | { |
7bcbce55 | 419 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 420 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 421 | |
f5f0b7aa | 422 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
423 | } |
424 | ||
6f5cfc0e | 425 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 426 | { |
7bcbce55 | 427 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 428 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 429 | |
f5f0b7aa | 430 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
431 | } |
432 | ||
6f5cfc0e | 433 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 434 | { |
7bcbce55 | 435 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 436 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
437 | |
438 | mutex_lock(&chip->irq_lock); | |
439 | } | |
440 | ||
6f5cfc0e | 441 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 442 | { |
7bcbce55 | 443 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 444 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
445 | u8 new_irqs; |
446 | int level, i; | |
44896bea YL |
447 | u8 invert_irq_mask[MAX_BANK]; |
448 | ||
449 | if (chip->driver_data & PCA_PCAL) { | |
450 | /* Enable latch on interrupt-enabled inputs */ | |
451 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
452 | ||
453 | for (i = 0; i < NBANK(chip); i++) | |
454 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
455 | ||
456 | /* Unmask enabled interrupts */ | |
457 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
458 | } | |
a2cb9aeb MZ |
459 | |
460 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
461 | for (i = 0; i < NBANK(chip); i++) { |
462 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
463 | new_irqs &= ~chip->reg_direction[i]; | |
464 | ||
465 | while (new_irqs) { | |
466 | level = __ffs(new_irqs); | |
467 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
468 | level + (BANK_SZ * i)); | |
469 | new_irqs &= ~(1 << level); | |
470 | } | |
a2cb9aeb | 471 | } |
89ea8bbe MZ |
472 | |
473 | mutex_unlock(&chip->irq_lock); | |
474 | } | |
475 | ||
6f5cfc0e | 476 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 477 | { |
7bcbce55 | 478 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 479 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
480 | int bank_nb = d->hwirq / BANK_SZ; |
481 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
482 | |
483 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
484 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 485 | d->irq, type); |
89ea8bbe MZ |
486 | return -EINVAL; |
487 | } | |
488 | ||
489 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 490 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 491 | else |
f5f0b7aa | 492 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
493 | |
494 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 495 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 496 | else |
f5f0b7aa | 497 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 498 | |
a2cb9aeb | 499 | return 0; |
89ea8bbe MZ |
500 | } |
501 | ||
502 | static struct irq_chip pca953x_irq_chip = { | |
503 | .name = "pca953x", | |
6f5cfc0e LB |
504 | .irq_mask = pca953x_irq_mask, |
505 | .irq_unmask = pca953x_irq_unmask, | |
506 | .irq_bus_lock = pca953x_irq_bus_lock, | |
507 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
508 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
509 | }; |
510 | ||
b6ac1280 | 511 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 512 | { |
f5f0b7aa GC |
513 | u8 cur_stat[MAX_BANK]; |
514 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
515 | bool pending_seen = false; |
516 | bool trigger_seen = false; | |
517 | u8 trigger[MAX_BANK]; | |
53661f3b | 518 | int ret, i; |
33226ffd | 519 | |
44896bea YL |
520 | if (chip->driver_data & PCA_PCAL) { |
521 | /* Read the current interrupt status from the device */ | |
522 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
523 | if (ret) | |
524 | return false; | |
525 | ||
526 | /* Check latched inputs and clear interrupt status */ | |
527 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
528 | if (ret) | |
529 | return false; | |
530 | ||
531 | for (i = 0; i < NBANK(chip); i++) { | |
532 | /* Apply filter for rising/falling edge selection */ | |
533 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
534 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
535 | pending[i] &= trigger[i]; | |
536 | if (pending[i]) | |
537 | pending_seen = true; | |
538 | } | |
539 | ||
540 | return pending_seen; | |
541 | } | |
542 | ||
53661f3b | 543 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 544 | if (ret) |
b6ac1280 | 545 | return false; |
89ea8bbe MZ |
546 | |
547 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
548 | for (i = 0; i < NBANK(chip); i++) |
549 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 550 | |
f5f0b7aa | 551 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 552 | |
f5f0b7aa GC |
553 | for (i = 0; i < NBANK(chip); i++) { |
554 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
555 | if (trigger[i]) |
556 | trigger_seen = true; | |
f5f0b7aa GC |
557 | } |
558 | ||
b6ac1280 JS |
559 | if (!trigger_seen) |
560 | return false; | |
89ea8bbe | 561 | |
f5f0b7aa | 562 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 563 | |
f5f0b7aa GC |
564 | for (i = 0; i < NBANK(chip); i++) { |
565 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
566 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
567 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
568 | if (pending[i]) |
569 | pending_seen = true; | |
f5f0b7aa | 570 | } |
89ea8bbe | 571 | |
b6ac1280 | 572 | return pending_seen; |
89ea8bbe MZ |
573 | } |
574 | ||
575 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
576 | { | |
577 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
578 | u8 pending[MAX_BANK]; |
579 | u8 level; | |
3275d072 | 580 | unsigned nhandled = 0; |
f5f0b7aa | 581 | int i; |
89ea8bbe | 582 | |
f5f0b7aa | 583 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 584 | return IRQ_NONE; |
89ea8bbe | 585 | |
f5f0b7aa GC |
586 | for (i = 0; i < NBANK(chip); i++) { |
587 | while (pending[i]) { | |
588 | level = __ffs(pending[i]); | |
7bcbce55 | 589 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain, |
f5f0b7aa GC |
590 | level + (BANK_SZ * i))); |
591 | pending[i] &= ~(1 << level); | |
3275d072 | 592 | nhandled++; |
f5f0b7aa GC |
593 | } |
594 | } | |
89ea8bbe | 595 | |
3275d072 | 596 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
597 | } |
598 | ||
599 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 600 | int irq_base) |
89ea8bbe MZ |
601 | { |
602 | struct i2c_client *client = chip->client; | |
53661f3b | 603 | int ret, i; |
89ea8bbe | 604 | |
4bb93349 | 605 | if (client->irq && irq_base != -1 |
c6664149 | 606 | && (chip->driver_data & PCA_INT)) { |
89ea8bbe | 607 | |
53661f3b BG |
608 | ret = pca953x_read_regs(chip, |
609 | chip->regs->input, chip->irq_stat); | |
89ea8bbe | 610 | if (ret) |
b42748c9 | 611 | return ret; |
89ea8bbe MZ |
612 | |
613 | /* | |
614 | * There is no way to know which GPIO line generated the | |
615 | * interrupt. We have to rely on the previous read for | |
616 | * this purpose. | |
617 | */ | |
f5f0b7aa GC |
618 | for (i = 0; i < NBANK(chip); i++) |
619 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
620 | mutex_init(&chip->irq_lock); |
621 | ||
b42748c9 LW |
622 | ret = devm_request_threaded_irq(&client->dev, |
623 | client->irq, | |
89ea8bbe MZ |
624 | NULL, |
625 | pca953x_irq_handler, | |
91329132 TS |
626 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
627 | IRQF_SHARED, | |
89ea8bbe MZ |
628 | dev_name(&client->dev), chip); |
629 | if (ret) { | |
630 | dev_err(&client->dev, "failed to request irq %d\n", | |
631 | client->irq); | |
0e8f2fda | 632 | return ret; |
89ea8bbe MZ |
633 | } |
634 | ||
7bcbce55 LW |
635 | ret = gpiochip_irqchip_add(&chip->gpio_chip, |
636 | &pca953x_irq_chip, | |
637 | irq_base, | |
638 | handle_simple_irq, | |
639 | IRQ_TYPE_NONE); | |
640 | if (ret) { | |
641 | dev_err(&client->dev, | |
642 | "could not connect irqchip to gpiochip\n"); | |
643 | return ret; | |
644 | } | |
fdd50409 GS |
645 | |
646 | gpiochip_set_chained_irqchip(&chip->gpio_chip, | |
647 | &pca953x_irq_chip, | |
648 | client->irq, NULL); | |
89ea8bbe MZ |
649 | } |
650 | ||
651 | return 0; | |
89ea8bbe MZ |
652 | } |
653 | ||
89ea8bbe MZ |
654 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
655 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 656 | int irq_base) |
89ea8bbe MZ |
657 | { |
658 | struct i2c_client *client = chip->client; | |
89ea8bbe | 659 | |
c6664149 | 660 | if (irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
661 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
662 | ||
663 | return 0; | |
664 | } | |
89ea8bbe MZ |
665 | #endif |
666 | ||
3836309d | 667 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
668 | { |
669 | int ret; | |
f5f0b7aa | 670 | u8 val[MAX_BANK]; |
33226ffd | 671 | |
53661f3b BG |
672 | chip->regs = &pca953x_regs; |
673 | ||
674 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
675 | if (ret) |
676 | goto out; | |
677 | ||
53661f3b BG |
678 | ret = pca953x_read_regs(chip, chip->regs->direction, |
679 | chip->reg_direction); | |
33226ffd HZ |
680 | if (ret) |
681 | goto out; | |
682 | ||
683 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
684 | if (invert) |
685 | memset(val, 0xFF, NBANK(chip)); | |
686 | else | |
687 | memset(val, 0, NBANK(chip)); | |
688 | ||
689 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
690 | out: |
691 | return ret; | |
692 | } | |
693 | ||
3836309d | 694 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
695 | { |
696 | int ret; | |
f5f0b7aa | 697 | u8 val[MAX_BANK]; |
33226ffd | 698 | |
53661f3b BG |
699 | chip->regs = &pca957x_regs; |
700 | ||
701 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
702 | if (ret) |
703 | goto out; | |
53661f3b BG |
704 | ret = pca953x_read_regs(chip, chip->regs->direction, |
705 | chip->reg_direction); | |
33226ffd HZ |
706 | if (ret) |
707 | goto out; | |
708 | ||
709 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
710 | if (invert) |
711 | memset(val, 0xFF, NBANK(chip)); | |
712 | else | |
713 | memset(val, 0, NBANK(chip)); | |
c75a3772 NK |
714 | ret = pca953x_write_regs(chip, PCA957X_INVRT, val); |
715 | if (ret) | |
716 | goto out; | |
33226ffd | 717 | |
20a8a968 | 718 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 719 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
720 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
721 | if (ret) | |
722 | goto out; | |
33226ffd HZ |
723 | |
724 | return 0; | |
725 | out: | |
726 | return ret; | |
727 | } | |
728 | ||
6f29c9af BD |
729 | static const struct of_device_id pca953x_dt_ids[]; |
730 | ||
3836309d | 731 | static int pca953x_probe(struct i2c_client *client, |
3760f736 | 732 | const struct i2c_device_id *id) |
9e60fdcf | 733 | { |
f3dc3630 GL |
734 | struct pca953x_platform_data *pdata; |
735 | struct pca953x_chip *chip; | |
6a7b36aa | 736 | int irq_base = 0; |
7ea2aa20 | 737 | int ret; |
6a7b36aa | 738 | u32 invert = 0; |
e23efa31 | 739 | struct regulator *reg; |
9e60fdcf | 740 | |
b42748c9 LW |
741 | chip = devm_kzalloc(&client->dev, |
742 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
743 | if (chip == NULL) |
744 | return -ENOMEM; | |
745 | ||
e56aee18 | 746 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
747 | if (pdata) { |
748 | irq_base = pdata->irq_base; | |
749 | chip->gpio_start = pdata->gpio_base; | |
750 | invert = pdata->invert; | |
751 | chip->names = pdata->names; | |
752 | } else { | |
4bb93349 MP |
753 | chip->gpio_start = -1; |
754 | irq_base = 0; | |
1965d303 | 755 | } |
9e60fdcf | 756 | |
757 | chip->client = client; | |
758 | ||
e23efa31 PR |
759 | reg = devm_regulator_get(&client->dev, "vcc"); |
760 | if (IS_ERR(reg)) { | |
761 | ret = PTR_ERR(reg); | |
762 | if (ret != -EPROBE_DEFER) | |
763 | dev_err(&client->dev, "reg get err: %d\n", ret); | |
764 | return ret; | |
765 | } | |
766 | ret = regulator_enable(reg); | |
767 | if (ret) { | |
768 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
769 | return ret; | |
770 | } | |
771 | chip->regulator = reg; | |
772 | ||
f32517bf AS |
773 | if (id) { |
774 | chip->driver_data = id->driver_data; | |
775 | } else { | |
776 | const struct acpi_device_id *id; | |
6f29c9af | 777 | const struct of_device_id *match; |
f32517bf | 778 | |
6f29c9af BD |
779 | match = of_match_device(pca953x_dt_ids, &client->dev); |
780 | if (match) { | |
781 | chip->driver_data = (int)(uintptr_t)match->data; | |
782 | } else { | |
783 | id = acpi_match_device(pca953x_acpi_ids, &client->dev); | |
e23efa31 PR |
784 | if (!id) { |
785 | ret = -ENODEV; | |
786 | goto err_exit; | |
787 | } | |
f32517bf | 788 | |
6f29c9af BD |
789 | chip->driver_data = id->driver_data; |
790 | } | |
f32517bf AS |
791 | } |
792 | ||
6e20fb18 RS |
793 | mutex_init(&chip->i2c_lock); |
794 | ||
9e60fdcf | 795 | /* initialize cached registers from their original values. |
796 | * we can't share this chip with another i2c master. | |
797 | */ | |
c6664149 | 798 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 799 | |
7acc66e3 BG |
800 | if (chip->gpio_chip.ngpio <= 8) { |
801 | chip->write_regs = pca953x_write_regs_8; | |
c6e3cf01 | 802 | chip->read_regs = pca953x_read_regs_8; |
7acc66e3 BG |
803 | } else if (chip->gpio_chip.ngpio >= 24) { |
804 | chip->write_regs = pca953x_write_regs_24; | |
c6e3cf01 | 805 | chip->read_regs = pca953x_read_regs_24; |
7acc66e3 BG |
806 | } else { |
807 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) | |
808 | chip->write_regs = pca953x_write_regs_16; | |
809 | else | |
810 | chip->write_regs = pca957x_write_regs_16; | |
c6e3cf01 | 811 | chip->read_regs = pca953x_read_regs_16; |
7acc66e3 BG |
812 | } |
813 | ||
60f547be | 814 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) |
7ea2aa20 | 815 | ret = device_pca953x_init(chip, invert); |
33226ffd | 816 | else |
7ea2aa20 WS |
817 | ret = device_pca957x_init(chip, invert); |
818 | if (ret) | |
e23efa31 | 819 | goto err_exit; |
9e60fdcf | 820 | |
0ece84f5 | 821 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 822 | if (ret) |
e23efa31 | 823 | goto err_exit; |
f5e8ff48 | 824 | |
c6664149 | 825 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 826 | if (ret) |
e23efa31 | 827 | goto err_exit; |
9e60fdcf | 828 | |
c6dcf592 | 829 | if (pdata && pdata->setup) { |
9e60fdcf | 830 | ret = pdata->setup(client, chip->gpio_chip.base, |
831 | chip->gpio_chip.ngpio, pdata->context); | |
832 | if (ret < 0) | |
833 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
834 | } | |
835 | ||
836 | i2c_set_clientdata(client, chip); | |
837 | return 0; | |
e23efa31 PR |
838 | |
839 | err_exit: | |
840 | regulator_disable(chip->regulator); | |
841 | return ret; | |
9e60fdcf | 842 | } |
843 | ||
f3dc3630 | 844 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 845 | { |
e56aee18 | 846 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 847 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
8c7a92da | 848 | int ret; |
9e60fdcf | 849 | |
c6dcf592 | 850 | if (pdata && pdata->teardown) { |
9e60fdcf | 851 | ret = pdata->teardown(client, chip->gpio_chip.base, |
852 | chip->gpio_chip.ngpio, pdata->context); | |
e23efa31 | 853 | if (ret < 0) |
9e60fdcf | 854 | dev_err(&client->dev, "%s failed, %d\n", |
855 | "teardown", ret); | |
bf62efeb AB |
856 | } else { |
857 | ret = 0; | |
9e60fdcf | 858 | } |
859 | ||
e23efa31 PR |
860 | regulator_disable(chip->regulator); |
861 | ||
862 | return ret; | |
9e60fdcf | 863 | } |
864 | ||
6f29c9af BD |
865 | /* convenience to stop overlong match-table lines */ |
866 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
867 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
868 | ||
ed32620e | 869 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
870 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
871 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
872 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
873 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
874 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
875 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
876 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
877 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
878 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
879 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
880 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
881 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
882 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
883 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
884 | ||
885 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, | |
886 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
887 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
888 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
889 | ||
890 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 891 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
892 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
893 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
894 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
895 | ||
896 | { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), }, | |
897 | ||
898 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
899 | { } |
900 | }; | |
901 | ||
902 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
903 | ||
f3dc3630 | 904 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 905 | .driver = { |
f3dc3630 | 906 | .name = "pca953x", |
ed32620e | 907 | .of_match_table = pca953x_dt_ids, |
f32517bf | 908 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 909 | }, |
f3dc3630 GL |
910 | .probe = pca953x_probe, |
911 | .remove = pca953x_remove, | |
3760f736 | 912 | .id_table = pca953x_id, |
9e60fdcf | 913 | }; |
914 | ||
f3dc3630 | 915 | static int __init pca953x_init(void) |
9e60fdcf | 916 | { |
f3dc3630 | 917 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 918 | } |
2f8d1197 DB |
919 | /* register after i2c postcore initcall and before |
920 | * subsys initcalls that may rely on these GPIOs | |
921 | */ | |
922 | subsys_initcall(pca953x_init); | |
9e60fdcf | 923 | |
f3dc3630 | 924 | static void __exit pca953x_exit(void) |
9e60fdcf | 925 | { |
f3dc3630 | 926 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 927 | } |
f3dc3630 | 928 | module_exit(pca953x_exit); |
9e60fdcf | 929 | |
930 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 931 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 932 | MODULE_LICENSE("GPL"); |