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Commit | Line | Data |
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9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe | 17 | #include <linux/interrupt.h> |
9e60fdcf | 18 | #include <linux/i2c.h> |
5877457a | 19 | #include <linux/platform_data/pca953x.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
9b8e3ec3 | 21 | #include <asm/unaligned.h> |
1965d303 | 22 | #include <linux/of_platform.h> |
f32517bf | 23 | #include <linux/acpi.h> |
e23efa31 | 24 | #include <linux/regulator/consumer.h> |
9e60fdcf | 25 | |
33226ffd HZ |
26 | #define PCA953X_INPUT 0 |
27 | #define PCA953X_OUTPUT 1 | |
28 | #define PCA953X_INVERT 2 | |
29 | #define PCA953X_DIRECTION 3 | |
30 | ||
ae79c190 AS |
31 | #define REG_ADDR_AI 0x80 |
32 | ||
33226ffd HZ |
33 | #define PCA957X_IN 0 |
34 | #define PCA957X_INVRT 1 | |
35 | #define PCA957X_BKEN 2 | |
36 | #define PCA957X_PUPD 3 | |
37 | #define PCA957X_CFG 4 | |
38 | #define PCA957X_OUT 5 | |
39 | #define PCA957X_MSK 6 | |
40 | #define PCA957X_INTS 7 | |
41 | ||
44896bea YL |
42 | #define PCAL953X_IN_LATCH 34 |
43 | #define PCAL953X_INT_MASK 37 | |
44 | #define PCAL953X_INT_STAT 38 | |
45 | ||
33226ffd HZ |
46 | #define PCA_GPIO_MASK 0x00FF |
47 | #define PCA_INT 0x0100 | |
8c7a92da | 48 | #define PCA_PCAL 0x0200 |
33226ffd HZ |
49 | #define PCA953X_TYPE 0x1000 |
50 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
51 | #define PCA_TYPE_MASK 0xF000 |
52 | ||
53 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 54 | |
3760f736 | 55 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 56 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
57 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
58 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
59 | { "pca9536", 4 | PCA953X_TYPE, }, | |
60 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
61 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
62 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
63 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
64 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
65 | { "pca9556", 8 | PCA953X_TYPE, }, | |
66 | { "pca9557", 8 | PCA953X_TYPE, }, | |
67 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
68 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 69 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 70 | |
747e42a1 AS |
71 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
72 | ||
33226ffd HZ |
73 | { "max7310", 8 | PCA953X_TYPE, }, |
74 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
75 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
76 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
77 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, | |
78 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
79 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 80 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 81 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 82 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 83 | { } |
f5e8ff48 | 84 | }; |
3760f736 | 85 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 86 | |
f32517bf | 87 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
44896bea | 88 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
f32517bf AS |
89 | { } |
90 | }; | |
91 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
92 | ||
f5f0b7aa GC |
93 | #define MAX_BANK 5 |
94 | #define BANK_SZ 8 | |
95 | ||
a246b819 | 96 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 97 | |
53661f3b BG |
98 | struct pca953x_reg_config { |
99 | int direction; | |
100 | int output; | |
101 | int input; | |
102 | }; | |
103 | ||
104 | static const struct pca953x_reg_config pca953x_regs = { | |
105 | .direction = PCA953X_DIRECTION, | |
106 | .output = PCA953X_OUTPUT, | |
107 | .input = PCA953X_INPUT, | |
108 | }; | |
109 | ||
110 | static const struct pca953x_reg_config pca957x_regs = { | |
111 | .direction = PCA957X_CFG, | |
112 | .output = PCA957X_OUT, | |
113 | .input = PCA957X_IN, | |
114 | }; | |
115 | ||
f3dc3630 | 116 | struct pca953x_chip { |
9e60fdcf | 117 | unsigned gpio_start; |
f5f0b7aa GC |
118 | u8 reg_output[MAX_BANK]; |
119 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 120 | struct mutex i2c_lock; |
9e60fdcf | 121 | |
89ea8bbe MZ |
122 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
123 | struct mutex irq_lock; | |
f5f0b7aa GC |
124 | u8 irq_mask[MAX_BANK]; |
125 | u8 irq_stat[MAX_BANK]; | |
126 | u8 irq_trig_raise[MAX_BANK]; | |
127 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
128 | #endif |
129 | ||
9e60fdcf | 130 | struct i2c_client *client; |
131 | struct gpio_chip gpio_chip; | |
62154991 | 132 | const char *const *names; |
33226ffd | 133 | int chip_type; |
c6664149 | 134 | unsigned long driver_data; |
e23efa31 | 135 | struct regulator *regulator; |
53661f3b BG |
136 | |
137 | const struct pca953x_reg_config *regs; | |
7acc66e3 BG |
138 | |
139 | int (*write_regs)(struct pca953x_chip *, int, u8 *); | |
9e60fdcf | 140 | }; |
141 | ||
f5f0b7aa GC |
142 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
143 | int off) | |
144 | { | |
145 | int ret; | |
146 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
147 | int offset = off / BANK_SZ; | |
148 | ||
149 | ret = i2c_smbus_read_byte_data(chip->client, | |
150 | (reg << bank_shift) + offset); | |
151 | *val = ret; | |
152 | ||
153 | if (ret < 0) { | |
154 | dev_err(&chip->client->dev, "failed reading register\n"); | |
155 | return ret; | |
156 | } | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
162 | int off) | |
163 | { | |
8c7a92da | 164 | int ret; |
f5f0b7aa GC |
165 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
166 | int offset = off / BANK_SZ; | |
167 | ||
168 | ret = i2c_smbus_write_byte_data(chip->client, | |
169 | (reg << bank_shift) + offset, val); | |
170 | ||
171 | if (ret < 0) { | |
172 | dev_err(&chip->client->dev, "failed writing register\n"); | |
173 | return ret; | |
174 | } | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
7acc66e3 | 179 | static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 180 | { |
7acc66e3 BG |
181 | return i2c_smbus_write_byte_data(chip->client, reg, *val); |
182 | } | |
f5e8ff48 | 183 | |
7acc66e3 BG |
184 | static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) |
185 | { | |
186 | __le16 word = cpu_to_le16(get_unaligned((u16 *)val)); | |
c4d1cbd7 | 187 | |
7acc66e3 BG |
188 | return i2c_smbus_write_word_data(chip->client, |
189 | reg << 1, (__force u16)word); | |
190 | } | |
191 | ||
192 | static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) | |
193 | { | |
194 | int ret; | |
195 | ||
196 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]); | |
197 | if (ret < 0) | |
198 | return ret; | |
199 | ||
200 | return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]); | |
201 | } | |
f5e8ff48 | 202 | |
7acc66e3 BG |
203 | static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) |
204 | { | |
205 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
206 | ||
207 | return i2c_smbus_write_i2c_block_data(chip->client, | |
208 | (reg << bank_shift) | REG_ADDR_AI, | |
209 | NBANK(chip), val); | |
210 | } | |
211 | ||
212 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
213 | { | |
214 | int ret = 0; | |
215 | ||
216 | ret = chip->write_regs(chip, reg, val); | |
f5e8ff48 GL |
217 | if (ret < 0) { |
218 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 219 | return ret; |
f5e8ff48 GL |
220 | } |
221 | ||
222 | return 0; | |
9e60fdcf | 223 | } |
224 | ||
f5f0b7aa | 225 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 226 | { |
227 | int ret; | |
228 | ||
96b70641 | 229 | if (chip->gpio_chip.ngpio <= 8) { |
f5e8ff48 | 230 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
96b70641 | 231 | *val = ret; |
f5f0b7aa GC |
232 | } else if (chip->gpio_chip.ngpio >= 24) { |
233 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
234 | ||
96b70641 | 235 | ret = i2c_smbus_read_i2c_block_data(chip->client, |
f5f0b7aa GC |
236 | (reg << bank_shift) | REG_ADDR_AI, |
237 | NBANK(chip), val); | |
96b70641 | 238 | } else { |
f5e8ff48 | 239 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); |
f5f0b7aa GC |
240 | val[0] = (u16)ret & 0xFF; |
241 | val[1] = (u16)ret >> 8; | |
96b70641 | 242 | } |
9e60fdcf | 243 | if (ret < 0) { |
244 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 245 | return ret; |
9e60fdcf | 246 | } |
247 | ||
9e60fdcf | 248 | return 0; |
249 | } | |
250 | ||
f3dc3630 | 251 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 252 | { |
468e67f6 | 253 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 254 | u8 reg_val; |
53661f3b | 255 | int ret; |
9e60fdcf | 256 | |
6e20fb18 | 257 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 258 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd | 259 | |
53661f3b | 260 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 261 | if (ret) |
6e20fb18 | 262 | goto exit; |
9e60fdcf | 263 | |
f5f0b7aa | 264 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
265 | exit: |
266 | mutex_unlock(&chip->i2c_lock); | |
267 | return ret; | |
9e60fdcf | 268 | } |
269 | ||
f3dc3630 | 270 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 271 | unsigned off, int val) |
272 | { | |
468e67f6 | 273 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 274 | u8 reg_val; |
53661f3b | 275 | int ret; |
9e60fdcf | 276 | |
6e20fb18 | 277 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 278 | /* set output level */ |
279 | if (val) | |
f5f0b7aa GC |
280 | reg_val = chip->reg_output[off / BANK_SZ] |
281 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 282 | else |
f5f0b7aa GC |
283 | reg_val = chip->reg_output[off / BANK_SZ] |
284 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 285 | |
53661f3b | 286 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 287 | if (ret) |
6e20fb18 | 288 | goto exit; |
9e60fdcf | 289 | |
f5f0b7aa | 290 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 291 | |
292 | /* then direction */ | |
f5f0b7aa | 293 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
53661f3b | 294 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 295 | if (ret) |
6e20fb18 | 296 | goto exit; |
9e60fdcf | 297 | |
f5f0b7aa | 298 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
299 | exit: |
300 | mutex_unlock(&chip->i2c_lock); | |
301 | return ret; | |
9e60fdcf | 302 | } |
303 | ||
f3dc3630 | 304 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 305 | { |
468e67f6 | 306 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ae79c190 | 307 | u32 reg_val; |
53661f3b | 308 | int ret; |
9e60fdcf | 309 | |
6e20fb18 | 310 | mutex_lock(&chip->i2c_lock); |
53661f3b | 311 | ret = pca953x_read_single(chip, chip->regs->input, ®_val, off); |
6e20fb18 | 312 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 313 | if (ret < 0) { |
314 | /* NOTE: diagnostic already emitted; that's all we should | |
315 | * do unless gpio_*_value_cansleep() calls become different | |
316 | * from their nonsleeping siblings (and report faults). | |
317 | */ | |
318 | return 0; | |
319 | } | |
320 | ||
40a625da | 321 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 322 | } |
323 | ||
f3dc3630 | 324 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 325 | { |
468e67f6 | 326 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 327 | u8 reg_val; |
53661f3b | 328 | int ret; |
9e60fdcf | 329 | |
6e20fb18 | 330 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 331 | if (val) |
f5f0b7aa GC |
332 | reg_val = chip->reg_output[off / BANK_SZ] |
333 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 334 | else |
f5f0b7aa GC |
335 | reg_val = chip->reg_output[off / BANK_SZ] |
336 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 337 | |
53661f3b | 338 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 339 | if (ret) |
6e20fb18 | 340 | goto exit; |
9e60fdcf | 341 | |
f5f0b7aa | 342 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
343 | exit: |
344 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 345 | } |
346 | ||
b4818afe PR |
347 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
348 | unsigned long *mask, unsigned long *bits) | |
349 | { | |
468e67f6 | 350 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
b4818afe | 351 | u8 reg_val[MAX_BANK]; |
53661f3b | 352 | int ret; |
b4818afe PR |
353 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
354 | int bank; | |
355 | ||
b4818afe PR |
356 | memcpy(reg_val, chip->reg_output, NBANK(chip)); |
357 | mutex_lock(&chip->i2c_lock); | |
358 | for(bank=0; bank<NBANK(chip); bank++) { | |
e0a8604f GU |
359 | unsigned bankmask = mask[bank / sizeof(*mask)] >> |
360 | ((bank % sizeof(*mask)) * 8); | |
b4818afe | 361 | if(bankmask) { |
e0a8604f GU |
362 | unsigned bankval = bits[bank / sizeof(*bits)] >> |
363 | ((bank % sizeof(*bits)) * 8); | |
b4818afe PR |
364 | reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval; |
365 | } | |
366 | } | |
53661f3b BG |
367 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
368 | chip->regs->output << bank_shift, | |
369 | NBANK(chip), reg_val); | |
b4818afe PR |
370 | if (ret) |
371 | goto exit; | |
372 | ||
373 | memcpy(chip->reg_output, reg_val, NBANK(chip)); | |
374 | exit: | |
375 | mutex_unlock(&chip->i2c_lock); | |
376 | } | |
377 | ||
f5e8ff48 | 378 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 379 | { |
380 | struct gpio_chip *gc; | |
381 | ||
382 | gc = &chip->gpio_chip; | |
383 | ||
f3dc3630 GL |
384 | gc->direction_input = pca953x_gpio_direction_input; |
385 | gc->direction_output = pca953x_gpio_direction_output; | |
386 | gc->get = pca953x_gpio_get_value; | |
387 | gc->set = pca953x_gpio_set_value; | |
b4818afe | 388 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 389 | gc->can_sleep = true; |
9e60fdcf | 390 | |
391 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
392 | gc->ngpio = gpios; |
393 | gc->label = chip->client->name; | |
58383c78 | 394 | gc->parent = &chip->client->dev; |
d72cbed0 | 395 | gc->owner = THIS_MODULE; |
77906a54 | 396 | gc->names = chip->names; |
9e60fdcf | 397 | } |
398 | ||
89ea8bbe | 399 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 400 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 401 | { |
7bcbce55 | 402 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 403 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 404 | |
f5f0b7aa | 405 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
406 | } |
407 | ||
6f5cfc0e | 408 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 409 | { |
7bcbce55 | 410 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 411 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 412 | |
f5f0b7aa | 413 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
414 | } |
415 | ||
6f5cfc0e | 416 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 417 | { |
7bcbce55 | 418 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 419 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
420 | |
421 | mutex_lock(&chip->irq_lock); | |
422 | } | |
423 | ||
6f5cfc0e | 424 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 425 | { |
7bcbce55 | 426 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 427 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
428 | u8 new_irqs; |
429 | int level, i; | |
44896bea YL |
430 | u8 invert_irq_mask[MAX_BANK]; |
431 | ||
432 | if (chip->driver_data & PCA_PCAL) { | |
433 | /* Enable latch on interrupt-enabled inputs */ | |
434 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
435 | ||
436 | for (i = 0; i < NBANK(chip); i++) | |
437 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
438 | ||
439 | /* Unmask enabled interrupts */ | |
440 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
441 | } | |
a2cb9aeb MZ |
442 | |
443 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
444 | for (i = 0; i < NBANK(chip); i++) { |
445 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
446 | new_irqs &= ~chip->reg_direction[i]; | |
447 | ||
448 | while (new_irqs) { | |
449 | level = __ffs(new_irqs); | |
450 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
451 | level + (BANK_SZ * i)); | |
452 | new_irqs &= ~(1 << level); | |
453 | } | |
a2cb9aeb | 454 | } |
89ea8bbe MZ |
455 | |
456 | mutex_unlock(&chip->irq_lock); | |
457 | } | |
458 | ||
6f5cfc0e | 459 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 460 | { |
7bcbce55 | 461 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 462 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
463 | int bank_nb = d->hwirq / BANK_SZ; |
464 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
465 | |
466 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
467 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 468 | d->irq, type); |
89ea8bbe MZ |
469 | return -EINVAL; |
470 | } | |
471 | ||
472 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 473 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 474 | else |
f5f0b7aa | 475 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
476 | |
477 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 478 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 479 | else |
f5f0b7aa | 480 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 481 | |
a2cb9aeb | 482 | return 0; |
89ea8bbe MZ |
483 | } |
484 | ||
485 | static struct irq_chip pca953x_irq_chip = { | |
486 | .name = "pca953x", | |
6f5cfc0e LB |
487 | .irq_mask = pca953x_irq_mask, |
488 | .irq_unmask = pca953x_irq_unmask, | |
489 | .irq_bus_lock = pca953x_irq_bus_lock, | |
490 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
491 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
492 | }; |
493 | ||
b6ac1280 | 494 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 495 | { |
f5f0b7aa GC |
496 | u8 cur_stat[MAX_BANK]; |
497 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
498 | bool pending_seen = false; |
499 | bool trigger_seen = false; | |
500 | u8 trigger[MAX_BANK]; | |
53661f3b | 501 | int ret, i; |
33226ffd | 502 | |
44896bea YL |
503 | if (chip->driver_data & PCA_PCAL) { |
504 | /* Read the current interrupt status from the device */ | |
505 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
506 | if (ret) | |
507 | return false; | |
508 | ||
509 | /* Check latched inputs and clear interrupt status */ | |
510 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
511 | if (ret) | |
512 | return false; | |
513 | ||
514 | for (i = 0; i < NBANK(chip); i++) { | |
515 | /* Apply filter for rising/falling edge selection */ | |
516 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
517 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
518 | pending[i] &= trigger[i]; | |
519 | if (pending[i]) | |
520 | pending_seen = true; | |
521 | } | |
522 | ||
523 | return pending_seen; | |
524 | } | |
525 | ||
53661f3b | 526 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 527 | if (ret) |
b6ac1280 | 528 | return false; |
89ea8bbe MZ |
529 | |
530 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
531 | for (i = 0; i < NBANK(chip); i++) |
532 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 533 | |
f5f0b7aa | 534 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 535 | |
f5f0b7aa GC |
536 | for (i = 0; i < NBANK(chip); i++) { |
537 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
538 | if (trigger[i]) |
539 | trigger_seen = true; | |
f5f0b7aa GC |
540 | } |
541 | ||
b6ac1280 JS |
542 | if (!trigger_seen) |
543 | return false; | |
89ea8bbe | 544 | |
f5f0b7aa | 545 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 546 | |
f5f0b7aa GC |
547 | for (i = 0; i < NBANK(chip); i++) { |
548 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
549 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
550 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
551 | if (pending[i]) |
552 | pending_seen = true; | |
f5f0b7aa | 553 | } |
89ea8bbe | 554 | |
b6ac1280 | 555 | return pending_seen; |
89ea8bbe MZ |
556 | } |
557 | ||
558 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
559 | { | |
560 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
561 | u8 pending[MAX_BANK]; |
562 | u8 level; | |
3275d072 | 563 | unsigned nhandled = 0; |
f5f0b7aa | 564 | int i; |
89ea8bbe | 565 | |
f5f0b7aa | 566 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 567 | return IRQ_NONE; |
89ea8bbe | 568 | |
f5f0b7aa GC |
569 | for (i = 0; i < NBANK(chip); i++) { |
570 | while (pending[i]) { | |
571 | level = __ffs(pending[i]); | |
7bcbce55 | 572 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain, |
f5f0b7aa GC |
573 | level + (BANK_SZ * i))); |
574 | pending[i] &= ~(1 << level); | |
3275d072 | 575 | nhandled++; |
f5f0b7aa GC |
576 | } |
577 | } | |
89ea8bbe | 578 | |
3275d072 | 579 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
580 | } |
581 | ||
582 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 583 | int irq_base) |
89ea8bbe MZ |
584 | { |
585 | struct i2c_client *client = chip->client; | |
53661f3b | 586 | int ret, i; |
89ea8bbe | 587 | |
4bb93349 | 588 | if (client->irq && irq_base != -1 |
c6664149 | 589 | && (chip->driver_data & PCA_INT)) { |
89ea8bbe | 590 | |
53661f3b BG |
591 | ret = pca953x_read_regs(chip, |
592 | chip->regs->input, chip->irq_stat); | |
89ea8bbe | 593 | if (ret) |
b42748c9 | 594 | return ret; |
89ea8bbe MZ |
595 | |
596 | /* | |
597 | * There is no way to know which GPIO line generated the | |
598 | * interrupt. We have to rely on the previous read for | |
599 | * this purpose. | |
600 | */ | |
f5f0b7aa GC |
601 | for (i = 0; i < NBANK(chip); i++) |
602 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
603 | mutex_init(&chip->irq_lock); |
604 | ||
b42748c9 LW |
605 | ret = devm_request_threaded_irq(&client->dev, |
606 | client->irq, | |
89ea8bbe MZ |
607 | NULL, |
608 | pca953x_irq_handler, | |
91329132 TS |
609 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
610 | IRQF_SHARED, | |
89ea8bbe MZ |
611 | dev_name(&client->dev), chip); |
612 | if (ret) { | |
613 | dev_err(&client->dev, "failed to request irq %d\n", | |
614 | client->irq); | |
0e8f2fda | 615 | return ret; |
89ea8bbe MZ |
616 | } |
617 | ||
7bcbce55 LW |
618 | ret = gpiochip_irqchip_add(&chip->gpio_chip, |
619 | &pca953x_irq_chip, | |
620 | irq_base, | |
621 | handle_simple_irq, | |
622 | IRQ_TYPE_NONE); | |
623 | if (ret) { | |
624 | dev_err(&client->dev, | |
625 | "could not connect irqchip to gpiochip\n"); | |
626 | return ret; | |
627 | } | |
fdd50409 GS |
628 | |
629 | gpiochip_set_chained_irqchip(&chip->gpio_chip, | |
630 | &pca953x_irq_chip, | |
631 | client->irq, NULL); | |
89ea8bbe MZ |
632 | } |
633 | ||
634 | return 0; | |
89ea8bbe MZ |
635 | } |
636 | ||
89ea8bbe MZ |
637 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
638 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 639 | int irq_base) |
89ea8bbe MZ |
640 | { |
641 | struct i2c_client *client = chip->client; | |
89ea8bbe | 642 | |
c6664149 | 643 | if (irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
644 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
645 | ||
646 | return 0; | |
647 | } | |
89ea8bbe MZ |
648 | #endif |
649 | ||
3836309d | 650 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
651 | { |
652 | int ret; | |
f5f0b7aa | 653 | u8 val[MAX_BANK]; |
33226ffd | 654 | |
53661f3b BG |
655 | chip->regs = &pca953x_regs; |
656 | ||
657 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
658 | if (ret) |
659 | goto out; | |
660 | ||
53661f3b BG |
661 | ret = pca953x_read_regs(chip, chip->regs->direction, |
662 | chip->reg_direction); | |
33226ffd HZ |
663 | if (ret) |
664 | goto out; | |
665 | ||
666 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
667 | if (invert) |
668 | memset(val, 0xFF, NBANK(chip)); | |
669 | else | |
670 | memset(val, 0, NBANK(chip)); | |
671 | ||
672 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
673 | out: |
674 | return ret; | |
675 | } | |
676 | ||
3836309d | 677 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
678 | { |
679 | int ret; | |
f5f0b7aa | 680 | u8 val[MAX_BANK]; |
33226ffd | 681 | |
53661f3b BG |
682 | chip->regs = &pca957x_regs; |
683 | ||
684 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
685 | if (ret) |
686 | goto out; | |
53661f3b BG |
687 | ret = pca953x_read_regs(chip, chip->regs->direction, |
688 | chip->reg_direction); | |
33226ffd HZ |
689 | if (ret) |
690 | goto out; | |
691 | ||
692 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
693 | if (invert) |
694 | memset(val, 0xFF, NBANK(chip)); | |
695 | else | |
696 | memset(val, 0, NBANK(chip)); | |
c75a3772 NK |
697 | ret = pca953x_write_regs(chip, PCA957X_INVRT, val); |
698 | if (ret) | |
699 | goto out; | |
33226ffd | 700 | |
20a8a968 | 701 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 702 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
703 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
704 | if (ret) | |
705 | goto out; | |
33226ffd HZ |
706 | |
707 | return 0; | |
708 | out: | |
709 | return ret; | |
710 | } | |
711 | ||
6f29c9af BD |
712 | static const struct of_device_id pca953x_dt_ids[]; |
713 | ||
3836309d | 714 | static int pca953x_probe(struct i2c_client *client, |
3760f736 | 715 | const struct i2c_device_id *id) |
9e60fdcf | 716 | { |
f3dc3630 GL |
717 | struct pca953x_platform_data *pdata; |
718 | struct pca953x_chip *chip; | |
6a7b36aa | 719 | int irq_base = 0; |
7ea2aa20 | 720 | int ret; |
6a7b36aa | 721 | u32 invert = 0; |
e23efa31 | 722 | struct regulator *reg; |
9e60fdcf | 723 | |
b42748c9 LW |
724 | chip = devm_kzalloc(&client->dev, |
725 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
726 | if (chip == NULL) |
727 | return -ENOMEM; | |
728 | ||
e56aee18 | 729 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
730 | if (pdata) { |
731 | irq_base = pdata->irq_base; | |
732 | chip->gpio_start = pdata->gpio_base; | |
733 | invert = pdata->invert; | |
734 | chip->names = pdata->names; | |
735 | } else { | |
4bb93349 MP |
736 | chip->gpio_start = -1; |
737 | irq_base = 0; | |
1965d303 | 738 | } |
9e60fdcf | 739 | |
740 | chip->client = client; | |
741 | ||
e23efa31 PR |
742 | reg = devm_regulator_get(&client->dev, "vcc"); |
743 | if (IS_ERR(reg)) { | |
744 | ret = PTR_ERR(reg); | |
745 | if (ret != -EPROBE_DEFER) | |
746 | dev_err(&client->dev, "reg get err: %d\n", ret); | |
747 | return ret; | |
748 | } | |
749 | ret = regulator_enable(reg); | |
750 | if (ret) { | |
751 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
752 | return ret; | |
753 | } | |
754 | chip->regulator = reg; | |
755 | ||
f32517bf AS |
756 | if (id) { |
757 | chip->driver_data = id->driver_data; | |
758 | } else { | |
759 | const struct acpi_device_id *id; | |
6f29c9af | 760 | const struct of_device_id *match; |
f32517bf | 761 | |
6f29c9af BD |
762 | match = of_match_device(pca953x_dt_ids, &client->dev); |
763 | if (match) { | |
764 | chip->driver_data = (int)(uintptr_t)match->data; | |
765 | } else { | |
766 | id = acpi_match_device(pca953x_acpi_ids, &client->dev); | |
e23efa31 PR |
767 | if (!id) { |
768 | ret = -ENODEV; | |
769 | goto err_exit; | |
770 | } | |
f32517bf | 771 | |
6f29c9af BD |
772 | chip->driver_data = id->driver_data; |
773 | } | |
f32517bf AS |
774 | } |
775 | ||
c6664149 | 776 | chip->chip_type = PCA_CHIP_TYPE(chip->driver_data); |
77906a54 | 777 | |
6e20fb18 RS |
778 | mutex_init(&chip->i2c_lock); |
779 | ||
9e60fdcf | 780 | /* initialize cached registers from their original values. |
781 | * we can't share this chip with another i2c master. | |
782 | */ | |
c6664149 | 783 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 784 | |
7acc66e3 BG |
785 | if (chip->gpio_chip.ngpio <= 8) { |
786 | chip->write_regs = pca953x_write_regs_8; | |
787 | } else if (chip->gpio_chip.ngpio >= 24) { | |
788 | chip->write_regs = pca953x_write_regs_24; | |
789 | } else { | |
790 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) | |
791 | chip->write_regs = pca953x_write_regs_16; | |
792 | else | |
793 | chip->write_regs = pca957x_write_regs_16; | |
794 | } | |
795 | ||
33226ffd | 796 | if (chip->chip_type == PCA953X_TYPE) |
7ea2aa20 | 797 | ret = device_pca953x_init(chip, invert); |
33226ffd | 798 | else |
7ea2aa20 WS |
799 | ret = device_pca957x_init(chip, invert); |
800 | if (ret) | |
e23efa31 | 801 | goto err_exit; |
9e60fdcf | 802 | |
0ece84f5 | 803 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 804 | if (ret) |
e23efa31 | 805 | goto err_exit; |
f5e8ff48 | 806 | |
c6664149 | 807 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 808 | if (ret) |
e23efa31 | 809 | goto err_exit; |
9e60fdcf | 810 | |
c6dcf592 | 811 | if (pdata && pdata->setup) { |
9e60fdcf | 812 | ret = pdata->setup(client, chip->gpio_chip.base, |
813 | chip->gpio_chip.ngpio, pdata->context); | |
814 | if (ret < 0) | |
815 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
816 | } | |
817 | ||
818 | i2c_set_clientdata(client, chip); | |
819 | return 0; | |
e23efa31 PR |
820 | |
821 | err_exit: | |
822 | regulator_disable(chip->regulator); | |
823 | return ret; | |
9e60fdcf | 824 | } |
825 | ||
f3dc3630 | 826 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 827 | { |
e56aee18 | 828 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 829 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
8c7a92da | 830 | int ret; |
9e60fdcf | 831 | |
c6dcf592 | 832 | if (pdata && pdata->teardown) { |
9e60fdcf | 833 | ret = pdata->teardown(client, chip->gpio_chip.base, |
834 | chip->gpio_chip.ngpio, pdata->context); | |
e23efa31 | 835 | if (ret < 0) |
9e60fdcf | 836 | dev_err(&client->dev, "%s failed, %d\n", |
837 | "teardown", ret); | |
bf62efeb AB |
838 | } else { |
839 | ret = 0; | |
9e60fdcf | 840 | } |
841 | ||
e23efa31 PR |
842 | regulator_disable(chip->regulator); |
843 | ||
844 | return ret; | |
9e60fdcf | 845 | } |
846 | ||
6f29c9af BD |
847 | /* convenience to stop overlong match-table lines */ |
848 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
849 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
850 | ||
ed32620e | 851 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
852 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
853 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
854 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
855 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
856 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
857 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
858 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
859 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
860 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
861 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
862 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
863 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
864 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
865 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
866 | ||
867 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, | |
868 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
869 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
870 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
871 | ||
872 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 873 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
874 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
875 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
876 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
877 | ||
878 | { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), }, | |
879 | ||
880 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
881 | { } |
882 | }; | |
883 | ||
884 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
885 | ||
f3dc3630 | 886 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 887 | .driver = { |
f3dc3630 | 888 | .name = "pca953x", |
ed32620e | 889 | .of_match_table = pca953x_dt_ids, |
f32517bf | 890 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 891 | }, |
f3dc3630 GL |
892 | .probe = pca953x_probe, |
893 | .remove = pca953x_remove, | |
3760f736 | 894 | .id_table = pca953x_id, |
9e60fdcf | 895 | }; |
896 | ||
f3dc3630 | 897 | static int __init pca953x_init(void) |
9e60fdcf | 898 | { |
f3dc3630 | 899 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 900 | } |
2f8d1197 DB |
901 | /* register after i2c postcore initcall and before |
902 | * subsys initcalls that may rely on these GPIOs | |
903 | */ | |
904 | subsys_initcall(pca953x_init); | |
9e60fdcf | 905 | |
f3dc3630 | 906 | static void __exit pca953x_exit(void) |
9e60fdcf | 907 | { |
f3dc3630 | 908 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 909 | } |
f3dc3630 | 910 | module_exit(pca953x_exit); |
9e60fdcf | 911 | |
912 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 913 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 914 | MODULE_LICENSE("GPL"); |