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9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
d120c17f 16#include <linux/gpio.h>
89ea8bbe 17#include <linux/interrupt.h>
9e60fdcf 18#include <linux/i2c.h>
5877457a 19#include <linux/platform_data/pca953x.h>
5a0e3ad6 20#include <linux/slab.h>
1965d303
NC
21#ifdef CONFIG_OF_GPIO
22#include <linux/of_platform.h>
1965d303 23#endif
9e60fdcf 24
33226ffd
HZ
25#define PCA953X_INPUT 0
26#define PCA953X_OUTPUT 1
27#define PCA953X_INVERT 2
28#define PCA953X_DIRECTION 3
29
ae79c190
AS
30#define REG_ADDR_AI 0x80
31
33226ffd
HZ
32#define PCA957X_IN 0
33#define PCA957X_INVRT 1
34#define PCA957X_BKEN 2
35#define PCA957X_PUPD 3
36#define PCA957X_CFG 4
37#define PCA957X_OUT 5
38#define PCA957X_MSK 6
39#define PCA957X_INTS 7
40
41#define PCA_GPIO_MASK 0x00FF
42#define PCA_INT 0x0100
43#define PCA953X_TYPE 0x1000
44#define PCA957X_TYPE 0x2000
89ea8bbe 45
3760f736 46static const struct i2c_device_id pca953x_id[] = {
89f5df01 47 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
48 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
49 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
50 { "pca9536", 4 | PCA953X_TYPE, },
51 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
52 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
53 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
54 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
55 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
56 { "pca9556", 8 | PCA953X_TYPE, },
57 { "pca9557", 8 | PCA953X_TYPE, },
58 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
59 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 60 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd
HZ
61
62 { "max7310", 8 | PCA953X_TYPE, },
63 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
64 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
65 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
66 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
67 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
68 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 69 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
2db8aba8 70 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
e73760a6 71 { "xra1202", 8 | PCA953X_TYPE },
3760f736 72 { }
f5e8ff48 73};
3760f736 74MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 75
f5f0b7aa
GC
76#define MAX_BANK 5
77#define BANK_SZ 8
78
79#define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
80
f3dc3630 81struct pca953x_chip {
9e60fdcf 82 unsigned gpio_start;
f5f0b7aa
GC
83 u8 reg_output[MAX_BANK];
84 u8 reg_direction[MAX_BANK];
6e20fb18 85 struct mutex i2c_lock;
9e60fdcf 86
89ea8bbe
MZ
87#ifdef CONFIG_GPIO_PCA953X_IRQ
88 struct mutex irq_lock;
f5f0b7aa
GC
89 u8 irq_mask[MAX_BANK];
90 u8 irq_stat[MAX_BANK];
91 u8 irq_trig_raise[MAX_BANK];
92 u8 irq_trig_fall[MAX_BANK];
89ea8bbe
MZ
93#endif
94
9e60fdcf 95 struct i2c_client *client;
96 struct gpio_chip gpio_chip;
62154991 97 const char *const *names;
33226ffd 98 int chip_type;
9e60fdcf 99};
100
7bcbce55
LW
101static inline struct pca953x_chip *to_pca(struct gpio_chip *gc)
102{
103 return container_of(gc, struct pca953x_chip, gpio_chip);
104}
105
f5f0b7aa
GC
106static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
107 int off)
108{
109 int ret;
110 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
111 int offset = off / BANK_SZ;
112
113 ret = i2c_smbus_read_byte_data(chip->client,
114 (reg << bank_shift) + offset);
115 *val = ret;
116
117 if (ret < 0) {
118 dev_err(&chip->client->dev, "failed reading register\n");
119 return ret;
120 }
121
122 return 0;
123}
124
125static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
126 int off)
127{
128 int ret = 0;
129 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
130 int offset = off / BANK_SZ;
131
132 ret = i2c_smbus_write_byte_data(chip->client,
133 (reg << bank_shift) + offset, val);
134
135 if (ret < 0) {
136 dev_err(&chip->client->dev, "failed writing register\n");
137 return ret;
138 }
139
140 return 0;
141}
142
143static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 144{
33226ffd 145 int ret = 0;
f5e8ff48
GL
146
147 if (chip->gpio_chip.ngpio <= 8)
f5f0b7aa
GC
148 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
149 else if (chip->gpio_chip.ngpio >= 24) {
150 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
96b70641 151 ret = i2c_smbus_write_i2c_block_data(chip->client,
f5f0b7aa
GC
152 (reg << bank_shift) | REG_ADDR_AI,
153 NBANK(chip), val);
50e44430 154 } else {
33226ffd
HZ
155 switch (chip->chip_type) {
156 case PCA953X_TYPE:
157 ret = i2c_smbus_write_word_data(chip->client,
f5f0b7aa 158 reg << 1, (u16) *val);
33226ffd
HZ
159 break;
160 case PCA957X_TYPE:
161 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
f5f0b7aa 162 val[0]);
33226ffd
HZ
163 if (ret < 0)
164 break;
165 ret = i2c_smbus_write_byte_data(chip->client,
166 (reg << 1) + 1,
f5f0b7aa 167 val[1]);
33226ffd
HZ
168 break;
169 }
170 }
f5e8ff48
GL
171
172 if (ret < 0) {
173 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 174 return ret;
f5e8ff48
GL
175 }
176
177 return 0;
9e60fdcf 178}
179
f5f0b7aa 180static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 181{
182 int ret;
183
96b70641 184 if (chip->gpio_chip.ngpio <= 8) {
f5e8ff48 185 ret = i2c_smbus_read_byte_data(chip->client, reg);
96b70641 186 *val = ret;
f5f0b7aa
GC
187 } else if (chip->gpio_chip.ngpio >= 24) {
188 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
189
96b70641 190 ret = i2c_smbus_read_i2c_block_data(chip->client,
f5f0b7aa
GC
191 (reg << bank_shift) | REG_ADDR_AI,
192 NBANK(chip), val);
96b70641 193 } else {
f5e8ff48 194 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
f5f0b7aa
GC
195 val[0] = (u16)ret & 0xFF;
196 val[1] = (u16)ret >> 8;
96b70641 197 }
9e60fdcf 198 if (ret < 0) {
199 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 200 return ret;
9e60fdcf 201 }
202
9e60fdcf 203 return 0;
204}
205
f3dc3630 206static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 207{
7bcbce55 208 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa 209 u8 reg_val;
33226ffd 210 int ret, offset = 0;
9e60fdcf 211
6e20fb18 212 mutex_lock(&chip->i2c_lock);
f5f0b7aa 213 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd
HZ
214
215 switch (chip->chip_type) {
216 case PCA953X_TYPE:
217 offset = PCA953X_DIRECTION;
218 break;
219 case PCA957X_TYPE:
220 offset = PCA957X_CFG;
221 break;
222 }
f5f0b7aa 223 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 224 if (ret)
6e20fb18 225 goto exit;
9e60fdcf 226
f5f0b7aa 227 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
228 ret = 0;
229exit:
230 mutex_unlock(&chip->i2c_lock);
231 return ret;
9e60fdcf 232}
233
f3dc3630 234static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 235 unsigned off, int val)
236{
7bcbce55 237 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa 238 u8 reg_val;
33226ffd 239 int ret, offset = 0;
9e60fdcf 240
6e20fb18 241 mutex_lock(&chip->i2c_lock);
9e60fdcf 242 /* set output level */
243 if (val)
f5f0b7aa
GC
244 reg_val = chip->reg_output[off / BANK_SZ]
245 | (1u << (off % BANK_SZ));
9e60fdcf 246 else
f5f0b7aa
GC
247 reg_val = chip->reg_output[off / BANK_SZ]
248 & ~(1u << (off % BANK_SZ));
9e60fdcf 249
33226ffd
HZ
250 switch (chip->chip_type) {
251 case PCA953X_TYPE:
252 offset = PCA953X_OUTPUT;
253 break;
254 case PCA957X_TYPE:
255 offset = PCA957X_OUT;
256 break;
257 }
f5f0b7aa 258 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 259 if (ret)
6e20fb18 260 goto exit;
9e60fdcf 261
f5f0b7aa 262 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 263
264 /* then direction */
f5f0b7aa 265 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
33226ffd
HZ
266 switch (chip->chip_type) {
267 case PCA953X_TYPE:
268 offset = PCA953X_DIRECTION;
269 break;
270 case PCA957X_TYPE:
271 offset = PCA957X_CFG;
272 break;
273 }
f5f0b7aa 274 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 275 if (ret)
6e20fb18 276 goto exit;
9e60fdcf 277
f5f0b7aa 278 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
279 ret = 0;
280exit:
281 mutex_unlock(&chip->i2c_lock);
282 return ret;
9e60fdcf 283}
284
f3dc3630 285static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 286{
7bcbce55 287 struct pca953x_chip *chip = to_pca(gc);
ae79c190 288 u32 reg_val;
33226ffd 289 int ret, offset = 0;
9e60fdcf 290
6e20fb18 291 mutex_lock(&chip->i2c_lock);
33226ffd
HZ
292 switch (chip->chip_type) {
293 case PCA953X_TYPE:
294 offset = PCA953X_INPUT;
295 break;
296 case PCA957X_TYPE:
297 offset = PCA957X_IN;
298 break;
299 }
f5f0b7aa 300 ret = pca953x_read_single(chip, offset, &reg_val, off);
6e20fb18 301 mutex_unlock(&chip->i2c_lock);
9e60fdcf 302 if (ret < 0) {
303 /* NOTE: diagnostic already emitted; that's all we should
304 * do unless gpio_*_value_cansleep() calls become different
305 * from their nonsleeping siblings (and report faults).
306 */
307 return 0;
308 }
309
40a625da 310 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 311}
312
f3dc3630 313static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 314{
7bcbce55 315 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa 316 u8 reg_val;
33226ffd 317 int ret, offset = 0;
9e60fdcf 318
6e20fb18 319 mutex_lock(&chip->i2c_lock);
9e60fdcf 320 if (val)
f5f0b7aa
GC
321 reg_val = chip->reg_output[off / BANK_SZ]
322 | (1u << (off % BANK_SZ));
9e60fdcf 323 else
f5f0b7aa
GC
324 reg_val = chip->reg_output[off / BANK_SZ]
325 & ~(1u << (off % BANK_SZ));
9e60fdcf 326
33226ffd
HZ
327 switch (chip->chip_type) {
328 case PCA953X_TYPE:
329 offset = PCA953X_OUTPUT;
330 break;
331 case PCA957X_TYPE:
332 offset = PCA957X_OUT;
333 break;
334 }
f5f0b7aa 335 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 336 if (ret)
6e20fb18 337 goto exit;
9e60fdcf 338
f5f0b7aa 339 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
340exit:
341 mutex_unlock(&chip->i2c_lock);
9e60fdcf 342}
343
f5e8ff48 344static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 345{
346 struct gpio_chip *gc;
347
348 gc = &chip->gpio_chip;
349
f3dc3630
GL
350 gc->direction_input = pca953x_gpio_direction_input;
351 gc->direction_output = pca953x_gpio_direction_output;
352 gc->get = pca953x_gpio_get_value;
353 gc->set = pca953x_gpio_set_value;
9fb1f39e 354 gc->can_sleep = true;
9e60fdcf 355
356 gc->base = chip->gpio_start;
f5e8ff48
GL
357 gc->ngpio = gpios;
358 gc->label = chip->client->name;
d8f388d8 359 gc->dev = &chip->client->dev;
d72cbed0 360 gc->owner = THIS_MODULE;
77906a54 361 gc->names = chip->names;
9e60fdcf 362}
363
89ea8bbe 364#ifdef CONFIG_GPIO_PCA953X_IRQ
6f5cfc0e 365static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 366{
7bcbce55
LW
367 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
368 struct pca953x_chip *chip = to_pca(gc);
89ea8bbe 369
f5f0b7aa 370 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
371}
372
6f5cfc0e 373static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 374{
7bcbce55
LW
375 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
376 struct pca953x_chip *chip = to_pca(gc);
89ea8bbe 377
f5f0b7aa 378 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
379}
380
6f5cfc0e 381static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 382{
7bcbce55
LW
383 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
384 struct pca953x_chip *chip = to_pca(gc);
89ea8bbe
MZ
385
386 mutex_lock(&chip->irq_lock);
387}
388
6f5cfc0e 389static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 390{
7bcbce55
LW
391 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
392 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa
GC
393 u8 new_irqs;
394 int level, i;
a2cb9aeb
MZ
395
396 /* Look for any newly setup interrupt */
f5f0b7aa
GC
397 for (i = 0; i < NBANK(chip); i++) {
398 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
399 new_irqs &= ~chip->reg_direction[i];
400
401 while (new_irqs) {
402 level = __ffs(new_irqs);
403 pca953x_gpio_direction_input(&chip->gpio_chip,
404 level + (BANK_SZ * i));
405 new_irqs &= ~(1 << level);
406 }
a2cb9aeb 407 }
89ea8bbe
MZ
408
409 mutex_unlock(&chip->irq_lock);
410}
411
6f5cfc0e 412static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 413{
7bcbce55
LW
414 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
415 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa
GC
416 int bank_nb = d->hwirq / BANK_SZ;
417 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
418
419 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
420 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 421 d->irq, type);
89ea8bbe
MZ
422 return -EINVAL;
423 }
424
425 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 426 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 427 else
f5f0b7aa 428 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
429
430 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 431 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 432 else
f5f0b7aa 433 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 434
a2cb9aeb 435 return 0;
89ea8bbe
MZ
436}
437
438static struct irq_chip pca953x_irq_chip = {
439 .name = "pca953x",
6f5cfc0e
LB
440 .irq_mask = pca953x_irq_mask,
441 .irq_unmask = pca953x_irq_unmask,
442 .irq_bus_lock = pca953x_irq_bus_lock,
443 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
444 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
445};
446
b6ac1280 447static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 448{
f5f0b7aa
GC
449 u8 cur_stat[MAX_BANK];
450 u8 old_stat[MAX_BANK];
b6ac1280
JS
451 bool pending_seen = false;
452 bool trigger_seen = false;
453 u8 trigger[MAX_BANK];
f5f0b7aa 454 int ret, i, offset = 0;
33226ffd
HZ
455
456 switch (chip->chip_type) {
457 case PCA953X_TYPE:
458 offset = PCA953X_INPUT;
459 break;
460 case PCA957X_TYPE:
461 offset = PCA957X_IN;
462 break;
463 }
f5f0b7aa 464 ret = pca953x_read_regs(chip, offset, cur_stat);
89ea8bbe 465 if (ret)
b6ac1280 466 return false;
89ea8bbe
MZ
467
468 /* Remove output pins from the equation */
f5f0b7aa
GC
469 for (i = 0; i < NBANK(chip); i++)
470 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 471
f5f0b7aa 472 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 473
f5f0b7aa
GC
474 for (i = 0; i < NBANK(chip); i++) {
475 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
b6ac1280
JS
476 if (trigger[i])
477 trigger_seen = true;
f5f0b7aa
GC
478 }
479
b6ac1280
JS
480 if (!trigger_seen)
481 return false;
89ea8bbe 482
f5f0b7aa 483 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 484
f5f0b7aa
GC
485 for (i = 0; i < NBANK(chip); i++) {
486 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
487 (cur_stat[i] & chip->irq_trig_raise[i]);
488 pending[i] &= trigger[i];
b6ac1280
JS
489 if (pending[i])
490 pending_seen = true;
f5f0b7aa 491 }
89ea8bbe 492
b6ac1280 493 return pending_seen;
89ea8bbe
MZ
494}
495
496static irqreturn_t pca953x_irq_handler(int irq, void *devid)
497{
498 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
499 u8 pending[MAX_BANK];
500 u8 level;
3275d072 501 unsigned nhandled = 0;
f5f0b7aa 502 int i;
89ea8bbe 503
f5f0b7aa 504 if (!pca953x_irq_pending(chip, pending))
3275d072 505 return IRQ_NONE;
89ea8bbe 506
f5f0b7aa
GC
507 for (i = 0; i < NBANK(chip); i++) {
508 while (pending[i]) {
509 level = __ffs(pending[i]);
7bcbce55 510 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
f5f0b7aa
GC
511 level + (BANK_SZ * i)));
512 pending[i] &= ~(1 << level);
3275d072 513 nhandled++;
f5f0b7aa
GC
514 }
515 }
89ea8bbe 516
3275d072 517 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
89ea8bbe
MZ
518}
519
520static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592
DJ
521 const struct i2c_device_id *id,
522 int irq_base)
89ea8bbe
MZ
523{
524 struct i2c_client *client = chip->client;
f5f0b7aa 525 int ret, i, offset = 0;
89ea8bbe 526
4bb93349 527 if (client->irq && irq_base != -1
33226ffd 528 && (id->driver_data & PCA_INT)) {
89ea8bbe 529
33226ffd
HZ
530 switch (chip->chip_type) {
531 case PCA953X_TYPE:
532 offset = PCA953X_INPUT;
533 break;
534 case PCA957X_TYPE:
535 offset = PCA957X_IN;
536 break;
537 }
f5f0b7aa 538 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
89ea8bbe 539 if (ret)
b42748c9 540 return ret;
89ea8bbe
MZ
541
542 /*
543 * There is no way to know which GPIO line generated the
544 * interrupt. We have to rely on the previous read for
545 * this purpose.
546 */
f5f0b7aa
GC
547 for (i = 0; i < NBANK(chip); i++)
548 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
549 mutex_init(&chip->irq_lock);
550
b42748c9
LW
551 ret = devm_request_threaded_irq(&client->dev,
552 client->irq,
89ea8bbe
MZ
553 NULL,
554 pca953x_irq_handler,
91329132
TS
555 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
556 IRQF_SHARED,
89ea8bbe
MZ
557 dev_name(&client->dev), chip);
558 if (ret) {
559 dev_err(&client->dev, "failed to request irq %d\n",
560 client->irq);
0e8f2fda 561 return ret;
89ea8bbe
MZ
562 }
563
7bcbce55
LW
564 ret = gpiochip_irqchip_add(&chip->gpio_chip,
565 &pca953x_irq_chip,
566 irq_base,
567 handle_simple_irq,
568 IRQ_TYPE_NONE);
569 if (ret) {
570 dev_err(&client->dev,
571 "could not connect irqchip to gpiochip\n");
572 return ret;
573 }
fdd50409
GS
574
575 gpiochip_set_chained_irqchip(&chip->gpio_chip,
576 &pca953x_irq_chip,
577 client->irq, NULL);
89ea8bbe
MZ
578 }
579
580 return 0;
89ea8bbe
MZ
581}
582
89ea8bbe
MZ
583#else /* CONFIG_GPIO_PCA953X_IRQ */
584static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592
DJ
585 const struct i2c_device_id *id,
586 int irq_base)
89ea8bbe
MZ
587{
588 struct i2c_client *client = chip->client;
89ea8bbe 589
c6dcf592 590 if (irq_base != -1 && (id->driver_data & PCA_INT))
89ea8bbe
MZ
591 dev_warn(&client->dev, "interrupt support not compiled in\n");
592
593 return 0;
594}
89ea8bbe
MZ
595#endif
596
3836309d 597static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
598{
599 int ret;
f5f0b7aa 600 u8 val[MAX_BANK];
33226ffd 601
f5f0b7aa 602 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
33226ffd
HZ
603 if (ret)
604 goto out;
605
f5f0b7aa
GC
606 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
607 chip->reg_direction);
33226ffd
HZ
608 if (ret)
609 goto out;
610
611 /* set platform specific polarity inversion */
f5f0b7aa
GC
612 if (invert)
613 memset(val, 0xFF, NBANK(chip));
614 else
615 memset(val, 0, NBANK(chip));
616
617 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
618out:
619 return ret;
620}
621
3836309d 622static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
623{
624 int ret;
f5f0b7aa 625 u8 val[MAX_BANK];
33226ffd 626
f5f0b7aa 627 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
33226ffd
HZ
628 if (ret)
629 goto out;
f5f0b7aa 630 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
33226ffd
HZ
631 if (ret)
632 goto out;
633
634 /* set platform specific polarity inversion */
f5f0b7aa
GC
635 if (invert)
636 memset(val, 0xFF, NBANK(chip));
637 else
638 memset(val, 0, NBANK(chip));
c75a3772
NK
639 ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
640 if (ret)
641 goto out;
33226ffd 642
20a8a968 643 /* To enable register 6, 7 to control pull up and pull down */
f5f0b7aa 644 memset(val, 0x02, NBANK(chip));
c75a3772
NK
645 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
646 if (ret)
647 goto out;
33226ffd
HZ
648
649 return 0;
650out:
651 return ret;
652}
653
3836309d 654static int pca953x_probe(struct i2c_client *client,
3760f736 655 const struct i2c_device_id *id)
9e60fdcf 656{
f3dc3630
GL
657 struct pca953x_platform_data *pdata;
658 struct pca953x_chip *chip;
6a7b36aa 659 int irq_base = 0;
7ea2aa20 660 int ret;
6a7b36aa 661 u32 invert = 0;
9e60fdcf 662
b42748c9
LW
663 chip = devm_kzalloc(&client->dev,
664 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
665 if (chip == NULL)
666 return -ENOMEM;
667
e56aee18 668 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
669 if (pdata) {
670 irq_base = pdata->irq_base;
671 chip->gpio_start = pdata->gpio_base;
672 invert = pdata->invert;
673 chip->names = pdata->names;
674 } else {
4bb93349
MP
675 chip->gpio_start = -1;
676 irq_base = 0;
1965d303 677 }
9e60fdcf 678
679 chip->client = client;
680
33226ffd 681 chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
77906a54 682
6e20fb18
RS
683 mutex_init(&chip->i2c_lock);
684
9e60fdcf 685 /* initialize cached registers from their original values.
686 * we can't share this chip with another i2c master.
687 */
33226ffd 688 pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
f5e8ff48 689
33226ffd 690 if (chip->chip_type == PCA953X_TYPE)
7ea2aa20 691 ret = device_pca953x_init(chip, invert);
33226ffd 692 else
7ea2aa20
WS
693 ret = device_pca957x_init(chip, invert);
694 if (ret)
b42748c9 695 return ret;
9e60fdcf 696
7bcbce55 697 ret = gpiochip_add(&chip->gpio_chip);
89ea8bbe 698 if (ret)
b42748c9 699 return ret;
f5e8ff48 700
7bcbce55 701 ret = pca953x_irq_setup(chip, id, irq_base);
9e60fdcf 702 if (ret)
b42748c9 703 return ret;
9e60fdcf 704
c6dcf592 705 if (pdata && pdata->setup) {
9e60fdcf 706 ret = pdata->setup(client, chip->gpio_chip.base,
707 chip->gpio_chip.ngpio, pdata->context);
708 if (ret < 0)
709 dev_warn(&client->dev, "setup failed, %d\n", ret);
710 }
711
712 i2c_set_clientdata(client, chip);
713 return 0;
9e60fdcf 714}
715
f3dc3630 716static int pca953x_remove(struct i2c_client *client)
9e60fdcf 717{
e56aee18 718 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 719 struct pca953x_chip *chip = i2c_get_clientdata(client);
9e60fdcf 720 int ret = 0;
721
c6dcf592 722 if (pdata && pdata->teardown) {
9e60fdcf 723 ret = pdata->teardown(client, chip->gpio_chip.base,
724 chip->gpio_chip.ngpio, pdata->context);
725 if (ret < 0) {
726 dev_err(&client->dev, "%s failed, %d\n",
727 "teardown", ret);
728 return ret;
729 }
730 }
731
9f5132ae 732 gpiochip_remove(&chip->gpio_chip);
9e60fdcf 733
9e60fdcf 734 return 0;
735}
736
ed32620e 737static const struct of_device_id pca953x_dt_ids[] = {
89f5df01 738 { .compatible = "nxp,pca9505", },
ed32620e
MR
739 { .compatible = "nxp,pca9534", },
740 { .compatible = "nxp,pca9535", },
741 { .compatible = "nxp,pca9536", },
742 { .compatible = "nxp,pca9537", },
743 { .compatible = "nxp,pca9538", },
744 { .compatible = "nxp,pca9539", },
745 { .compatible = "nxp,pca9554", },
746 { .compatible = "nxp,pca9555", },
747 { .compatible = "nxp,pca9556", },
748 { .compatible = "nxp,pca9557", },
749 { .compatible = "nxp,pca9574", },
750 { .compatible = "nxp,pca9575", },
eb32b5aa 751 { .compatible = "nxp,pca9698", },
ed32620e
MR
752
753 { .compatible = "maxim,max7310", },
754 { .compatible = "maxim,max7312", },
755 { .compatible = "maxim,max7313", },
756 { .compatible = "maxim,max7315", },
757
758 { .compatible = "ti,pca6107", },
759 { .compatible = "ti,tca6408", },
760 { .compatible = "ti,tca6416", },
761 { .compatible = "ti,tca6424", },
e73760a6
AS
762
763 { .compatible = "exar,xra1202", },
ed32620e
MR
764 { }
765};
766
767MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
768
f3dc3630 769static struct i2c_driver pca953x_driver = {
9e60fdcf 770 .driver = {
f3dc3630 771 .name = "pca953x",
ed32620e 772 .of_match_table = pca953x_dt_ids,
9e60fdcf 773 },
f3dc3630
GL
774 .probe = pca953x_probe,
775 .remove = pca953x_remove,
3760f736 776 .id_table = pca953x_id,
9e60fdcf 777};
778
f3dc3630 779static int __init pca953x_init(void)
9e60fdcf 780{
f3dc3630 781 return i2c_add_driver(&pca953x_driver);
9e60fdcf 782}
2f8d1197
DB
783/* register after i2c postcore initcall and before
784 * subsys initcalls that may rely on these GPIOs
785 */
786subsys_initcall(pca953x_init);
9e60fdcf 787
f3dc3630 788static void __exit pca953x_exit(void)
9e60fdcf 789{
f3dc3630 790 i2c_del_driver(&pca953x_driver);
9e60fdcf 791}
f3dc3630 792module_exit(pca953x_exit);
9e60fdcf 793
794MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 795MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 796MODULE_LICENSE("GPL");