]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/gpio/gpio-pca953x.c
gpio: pca953x: store driver_data for future use
[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-pca953x.c
CommitLineData
9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
d120c17f 16#include <linux/gpio.h>
89ea8bbe 17#include <linux/interrupt.h>
9e60fdcf 18#include <linux/i2c.h>
5877457a 19#include <linux/platform_data/pca953x.h>
5a0e3ad6 20#include <linux/slab.h>
1965d303
NC
21#ifdef CONFIG_OF_GPIO
22#include <linux/of_platform.h>
1965d303 23#endif
9e60fdcf 24
33226ffd
HZ
25#define PCA953X_INPUT 0
26#define PCA953X_OUTPUT 1
27#define PCA953X_INVERT 2
28#define PCA953X_DIRECTION 3
29
ae79c190
AS
30#define REG_ADDR_AI 0x80
31
33226ffd
HZ
32#define PCA957X_IN 0
33#define PCA957X_INVRT 1
34#define PCA957X_BKEN 2
35#define PCA957X_PUPD 3
36#define PCA957X_CFG 4
37#define PCA957X_OUT 5
38#define PCA957X_MSK 6
39#define PCA957X_INTS 7
40
41#define PCA_GPIO_MASK 0x00FF
42#define PCA_INT 0x0100
43#define PCA953X_TYPE 0x1000
44#define PCA957X_TYPE 0x2000
c6664149
AS
45#define PCA_TYPE_MASK 0xF000
46
47#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
89ea8bbe 48
3760f736 49static const struct i2c_device_id pca953x_id[] = {
89f5df01 50 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
51 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
52 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
53 { "pca9536", 4 | PCA953X_TYPE, },
54 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
55 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
56 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
57 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
58 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
59 { "pca9556", 8 | PCA953X_TYPE, },
60 { "pca9557", 8 | PCA953X_TYPE, },
61 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
62 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 63 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd
HZ
64
65 { "max7310", 8 | PCA953X_TYPE, },
66 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
67 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
68 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
69 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
70 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
71 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 72 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
2db8aba8 73 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
e73760a6 74 { "xra1202", 8 | PCA953X_TYPE },
3760f736 75 { }
f5e8ff48 76};
3760f736 77MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 78
f5f0b7aa
GC
79#define MAX_BANK 5
80#define BANK_SZ 8
81
82#define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
83
f3dc3630 84struct pca953x_chip {
9e60fdcf 85 unsigned gpio_start;
f5f0b7aa
GC
86 u8 reg_output[MAX_BANK];
87 u8 reg_direction[MAX_BANK];
6e20fb18 88 struct mutex i2c_lock;
9e60fdcf 89
89ea8bbe
MZ
90#ifdef CONFIG_GPIO_PCA953X_IRQ
91 struct mutex irq_lock;
f5f0b7aa
GC
92 u8 irq_mask[MAX_BANK];
93 u8 irq_stat[MAX_BANK];
94 u8 irq_trig_raise[MAX_BANK];
95 u8 irq_trig_fall[MAX_BANK];
89ea8bbe
MZ
96#endif
97
9e60fdcf 98 struct i2c_client *client;
99 struct gpio_chip gpio_chip;
62154991 100 const char *const *names;
33226ffd 101 int chip_type;
c6664149 102 unsigned long driver_data;
9e60fdcf 103};
104
7bcbce55
LW
105static inline struct pca953x_chip *to_pca(struct gpio_chip *gc)
106{
107 return container_of(gc, struct pca953x_chip, gpio_chip);
108}
109
f5f0b7aa
GC
110static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
111 int off)
112{
113 int ret;
114 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
115 int offset = off / BANK_SZ;
116
117 ret = i2c_smbus_read_byte_data(chip->client,
118 (reg << bank_shift) + offset);
119 *val = ret;
120
121 if (ret < 0) {
122 dev_err(&chip->client->dev, "failed reading register\n");
123 return ret;
124 }
125
126 return 0;
127}
128
129static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
130 int off)
131{
132 int ret = 0;
133 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
134 int offset = off / BANK_SZ;
135
136 ret = i2c_smbus_write_byte_data(chip->client,
137 (reg << bank_shift) + offset, val);
138
139 if (ret < 0) {
140 dev_err(&chip->client->dev, "failed writing register\n");
141 return ret;
142 }
143
144 return 0;
145}
146
147static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 148{
33226ffd 149 int ret = 0;
f5e8ff48
GL
150
151 if (chip->gpio_chip.ngpio <= 8)
f5f0b7aa
GC
152 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
153 else if (chip->gpio_chip.ngpio >= 24) {
154 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
96b70641 155 ret = i2c_smbus_write_i2c_block_data(chip->client,
f5f0b7aa
GC
156 (reg << bank_shift) | REG_ADDR_AI,
157 NBANK(chip), val);
50e44430 158 } else {
33226ffd
HZ
159 switch (chip->chip_type) {
160 case PCA953X_TYPE:
161 ret = i2c_smbus_write_word_data(chip->client,
f5f0b7aa 162 reg << 1, (u16) *val);
33226ffd
HZ
163 break;
164 case PCA957X_TYPE:
165 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
f5f0b7aa 166 val[0]);
33226ffd
HZ
167 if (ret < 0)
168 break;
169 ret = i2c_smbus_write_byte_data(chip->client,
170 (reg << 1) + 1,
f5f0b7aa 171 val[1]);
33226ffd
HZ
172 break;
173 }
174 }
f5e8ff48
GL
175
176 if (ret < 0) {
177 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 178 return ret;
f5e8ff48
GL
179 }
180
181 return 0;
9e60fdcf 182}
183
f5f0b7aa 184static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 185{
186 int ret;
187
96b70641 188 if (chip->gpio_chip.ngpio <= 8) {
f5e8ff48 189 ret = i2c_smbus_read_byte_data(chip->client, reg);
96b70641 190 *val = ret;
f5f0b7aa
GC
191 } else if (chip->gpio_chip.ngpio >= 24) {
192 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
193
96b70641 194 ret = i2c_smbus_read_i2c_block_data(chip->client,
f5f0b7aa
GC
195 (reg << bank_shift) | REG_ADDR_AI,
196 NBANK(chip), val);
96b70641 197 } else {
f5e8ff48 198 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
f5f0b7aa
GC
199 val[0] = (u16)ret & 0xFF;
200 val[1] = (u16)ret >> 8;
96b70641 201 }
9e60fdcf 202 if (ret < 0) {
203 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 204 return ret;
9e60fdcf 205 }
206
9e60fdcf 207 return 0;
208}
209
f3dc3630 210static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 211{
7bcbce55 212 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa 213 u8 reg_val;
33226ffd 214 int ret, offset = 0;
9e60fdcf 215
6e20fb18 216 mutex_lock(&chip->i2c_lock);
f5f0b7aa 217 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd
HZ
218
219 switch (chip->chip_type) {
220 case PCA953X_TYPE:
221 offset = PCA953X_DIRECTION;
222 break;
223 case PCA957X_TYPE:
224 offset = PCA957X_CFG;
225 break;
226 }
f5f0b7aa 227 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 228 if (ret)
6e20fb18 229 goto exit;
9e60fdcf 230
f5f0b7aa 231 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
232 ret = 0;
233exit:
234 mutex_unlock(&chip->i2c_lock);
235 return ret;
9e60fdcf 236}
237
f3dc3630 238static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 239 unsigned off, int val)
240{
7bcbce55 241 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa 242 u8 reg_val;
33226ffd 243 int ret, offset = 0;
9e60fdcf 244
6e20fb18 245 mutex_lock(&chip->i2c_lock);
9e60fdcf 246 /* set output level */
247 if (val)
f5f0b7aa
GC
248 reg_val = chip->reg_output[off / BANK_SZ]
249 | (1u << (off % BANK_SZ));
9e60fdcf 250 else
f5f0b7aa
GC
251 reg_val = chip->reg_output[off / BANK_SZ]
252 & ~(1u << (off % BANK_SZ));
9e60fdcf 253
33226ffd
HZ
254 switch (chip->chip_type) {
255 case PCA953X_TYPE:
256 offset = PCA953X_OUTPUT;
257 break;
258 case PCA957X_TYPE:
259 offset = PCA957X_OUT;
260 break;
261 }
f5f0b7aa 262 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 263 if (ret)
6e20fb18 264 goto exit;
9e60fdcf 265
f5f0b7aa 266 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 267
268 /* then direction */
f5f0b7aa 269 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
33226ffd
HZ
270 switch (chip->chip_type) {
271 case PCA953X_TYPE:
272 offset = PCA953X_DIRECTION;
273 break;
274 case PCA957X_TYPE:
275 offset = PCA957X_CFG;
276 break;
277 }
f5f0b7aa 278 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 279 if (ret)
6e20fb18 280 goto exit;
9e60fdcf 281
f5f0b7aa 282 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
283 ret = 0;
284exit:
285 mutex_unlock(&chip->i2c_lock);
286 return ret;
9e60fdcf 287}
288
f3dc3630 289static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 290{
7bcbce55 291 struct pca953x_chip *chip = to_pca(gc);
ae79c190 292 u32 reg_val;
33226ffd 293 int ret, offset = 0;
9e60fdcf 294
6e20fb18 295 mutex_lock(&chip->i2c_lock);
33226ffd
HZ
296 switch (chip->chip_type) {
297 case PCA953X_TYPE:
298 offset = PCA953X_INPUT;
299 break;
300 case PCA957X_TYPE:
301 offset = PCA957X_IN;
302 break;
303 }
f5f0b7aa 304 ret = pca953x_read_single(chip, offset, &reg_val, off);
6e20fb18 305 mutex_unlock(&chip->i2c_lock);
9e60fdcf 306 if (ret < 0) {
307 /* NOTE: diagnostic already emitted; that's all we should
308 * do unless gpio_*_value_cansleep() calls become different
309 * from their nonsleeping siblings (and report faults).
310 */
311 return 0;
312 }
313
40a625da 314 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 315}
316
f3dc3630 317static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 318{
7bcbce55 319 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa 320 u8 reg_val;
33226ffd 321 int ret, offset = 0;
9e60fdcf 322
6e20fb18 323 mutex_lock(&chip->i2c_lock);
9e60fdcf 324 if (val)
f5f0b7aa
GC
325 reg_val = chip->reg_output[off / BANK_SZ]
326 | (1u << (off % BANK_SZ));
9e60fdcf 327 else
f5f0b7aa
GC
328 reg_val = chip->reg_output[off / BANK_SZ]
329 & ~(1u << (off % BANK_SZ));
9e60fdcf 330
33226ffd
HZ
331 switch (chip->chip_type) {
332 case PCA953X_TYPE:
333 offset = PCA953X_OUTPUT;
334 break;
335 case PCA957X_TYPE:
336 offset = PCA957X_OUT;
337 break;
338 }
f5f0b7aa 339 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 340 if (ret)
6e20fb18 341 goto exit;
9e60fdcf 342
f5f0b7aa 343 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
344exit:
345 mutex_unlock(&chip->i2c_lock);
9e60fdcf 346}
347
f5e8ff48 348static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 349{
350 struct gpio_chip *gc;
351
352 gc = &chip->gpio_chip;
353
f3dc3630
GL
354 gc->direction_input = pca953x_gpio_direction_input;
355 gc->direction_output = pca953x_gpio_direction_output;
356 gc->get = pca953x_gpio_get_value;
357 gc->set = pca953x_gpio_set_value;
9fb1f39e 358 gc->can_sleep = true;
9e60fdcf 359
360 gc->base = chip->gpio_start;
f5e8ff48
GL
361 gc->ngpio = gpios;
362 gc->label = chip->client->name;
d8f388d8 363 gc->dev = &chip->client->dev;
d72cbed0 364 gc->owner = THIS_MODULE;
77906a54 365 gc->names = chip->names;
9e60fdcf 366}
367
89ea8bbe 368#ifdef CONFIG_GPIO_PCA953X_IRQ
6f5cfc0e 369static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 370{
7bcbce55
LW
371 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
372 struct pca953x_chip *chip = to_pca(gc);
89ea8bbe 373
f5f0b7aa 374 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
375}
376
6f5cfc0e 377static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 378{
7bcbce55
LW
379 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
380 struct pca953x_chip *chip = to_pca(gc);
89ea8bbe 381
f5f0b7aa 382 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
383}
384
6f5cfc0e 385static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 386{
7bcbce55
LW
387 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
388 struct pca953x_chip *chip = to_pca(gc);
89ea8bbe
MZ
389
390 mutex_lock(&chip->irq_lock);
391}
392
6f5cfc0e 393static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 394{
7bcbce55
LW
395 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
396 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa
GC
397 u8 new_irqs;
398 int level, i;
a2cb9aeb
MZ
399
400 /* Look for any newly setup interrupt */
f5f0b7aa
GC
401 for (i = 0; i < NBANK(chip); i++) {
402 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
403 new_irqs &= ~chip->reg_direction[i];
404
405 while (new_irqs) {
406 level = __ffs(new_irqs);
407 pca953x_gpio_direction_input(&chip->gpio_chip,
408 level + (BANK_SZ * i));
409 new_irqs &= ~(1 << level);
410 }
a2cb9aeb 411 }
89ea8bbe
MZ
412
413 mutex_unlock(&chip->irq_lock);
414}
415
6f5cfc0e 416static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 417{
7bcbce55
LW
418 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
419 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa
GC
420 int bank_nb = d->hwirq / BANK_SZ;
421 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
422
423 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
424 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 425 d->irq, type);
89ea8bbe
MZ
426 return -EINVAL;
427 }
428
429 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 430 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 431 else
f5f0b7aa 432 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
433
434 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 435 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 436 else
f5f0b7aa 437 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 438
a2cb9aeb 439 return 0;
89ea8bbe
MZ
440}
441
442static struct irq_chip pca953x_irq_chip = {
443 .name = "pca953x",
6f5cfc0e
LB
444 .irq_mask = pca953x_irq_mask,
445 .irq_unmask = pca953x_irq_unmask,
446 .irq_bus_lock = pca953x_irq_bus_lock,
447 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
448 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
449};
450
b6ac1280 451static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 452{
f5f0b7aa
GC
453 u8 cur_stat[MAX_BANK];
454 u8 old_stat[MAX_BANK];
b6ac1280
JS
455 bool pending_seen = false;
456 bool trigger_seen = false;
457 u8 trigger[MAX_BANK];
f5f0b7aa 458 int ret, i, offset = 0;
33226ffd
HZ
459
460 switch (chip->chip_type) {
461 case PCA953X_TYPE:
462 offset = PCA953X_INPUT;
463 break;
464 case PCA957X_TYPE:
465 offset = PCA957X_IN;
466 break;
467 }
f5f0b7aa 468 ret = pca953x_read_regs(chip, offset, cur_stat);
89ea8bbe 469 if (ret)
b6ac1280 470 return false;
89ea8bbe
MZ
471
472 /* Remove output pins from the equation */
f5f0b7aa
GC
473 for (i = 0; i < NBANK(chip); i++)
474 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 475
f5f0b7aa 476 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 477
f5f0b7aa
GC
478 for (i = 0; i < NBANK(chip); i++) {
479 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
b6ac1280
JS
480 if (trigger[i])
481 trigger_seen = true;
f5f0b7aa
GC
482 }
483
b6ac1280
JS
484 if (!trigger_seen)
485 return false;
89ea8bbe 486
f5f0b7aa 487 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 488
f5f0b7aa
GC
489 for (i = 0; i < NBANK(chip); i++) {
490 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
491 (cur_stat[i] & chip->irq_trig_raise[i]);
492 pending[i] &= trigger[i];
b6ac1280
JS
493 if (pending[i])
494 pending_seen = true;
f5f0b7aa 495 }
89ea8bbe 496
b6ac1280 497 return pending_seen;
89ea8bbe
MZ
498}
499
500static irqreturn_t pca953x_irq_handler(int irq, void *devid)
501{
502 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
503 u8 pending[MAX_BANK];
504 u8 level;
3275d072 505 unsigned nhandled = 0;
f5f0b7aa 506 int i;
89ea8bbe 507
f5f0b7aa 508 if (!pca953x_irq_pending(chip, pending))
3275d072 509 return IRQ_NONE;
89ea8bbe 510
f5f0b7aa
GC
511 for (i = 0; i < NBANK(chip); i++) {
512 while (pending[i]) {
513 level = __ffs(pending[i]);
7bcbce55 514 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
f5f0b7aa
GC
515 level + (BANK_SZ * i)));
516 pending[i] &= ~(1 << level);
3275d072 517 nhandled++;
f5f0b7aa
GC
518 }
519 }
89ea8bbe 520
3275d072 521 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
89ea8bbe
MZ
522}
523
524static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 525 int irq_base)
89ea8bbe
MZ
526{
527 struct i2c_client *client = chip->client;
f5f0b7aa 528 int ret, i, offset = 0;
89ea8bbe 529
4bb93349 530 if (client->irq && irq_base != -1
c6664149 531 && (chip->driver_data & PCA_INT)) {
89ea8bbe 532
33226ffd
HZ
533 switch (chip->chip_type) {
534 case PCA953X_TYPE:
535 offset = PCA953X_INPUT;
536 break;
537 case PCA957X_TYPE:
538 offset = PCA957X_IN;
539 break;
540 }
f5f0b7aa 541 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
89ea8bbe 542 if (ret)
b42748c9 543 return ret;
89ea8bbe
MZ
544
545 /*
546 * There is no way to know which GPIO line generated the
547 * interrupt. We have to rely on the previous read for
548 * this purpose.
549 */
f5f0b7aa
GC
550 for (i = 0; i < NBANK(chip); i++)
551 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
552 mutex_init(&chip->irq_lock);
553
b42748c9
LW
554 ret = devm_request_threaded_irq(&client->dev,
555 client->irq,
89ea8bbe
MZ
556 NULL,
557 pca953x_irq_handler,
91329132
TS
558 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
559 IRQF_SHARED,
89ea8bbe
MZ
560 dev_name(&client->dev), chip);
561 if (ret) {
562 dev_err(&client->dev, "failed to request irq %d\n",
563 client->irq);
0e8f2fda 564 return ret;
89ea8bbe
MZ
565 }
566
7bcbce55
LW
567 ret = gpiochip_irqchip_add(&chip->gpio_chip,
568 &pca953x_irq_chip,
569 irq_base,
570 handle_simple_irq,
571 IRQ_TYPE_NONE);
572 if (ret) {
573 dev_err(&client->dev,
574 "could not connect irqchip to gpiochip\n");
575 return ret;
576 }
fdd50409
GS
577
578 gpiochip_set_chained_irqchip(&chip->gpio_chip,
579 &pca953x_irq_chip,
580 client->irq, NULL);
89ea8bbe
MZ
581 }
582
583 return 0;
89ea8bbe
MZ
584}
585
89ea8bbe
MZ
586#else /* CONFIG_GPIO_PCA953X_IRQ */
587static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 588 int irq_base)
89ea8bbe
MZ
589{
590 struct i2c_client *client = chip->client;
89ea8bbe 591
c6664149 592 if (irq_base != -1 && (chip->driver_data & PCA_INT))
89ea8bbe
MZ
593 dev_warn(&client->dev, "interrupt support not compiled in\n");
594
595 return 0;
596}
89ea8bbe
MZ
597#endif
598
3836309d 599static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
600{
601 int ret;
f5f0b7aa 602 u8 val[MAX_BANK];
33226ffd 603
f5f0b7aa 604 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
33226ffd
HZ
605 if (ret)
606 goto out;
607
f5f0b7aa
GC
608 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
609 chip->reg_direction);
33226ffd
HZ
610 if (ret)
611 goto out;
612
613 /* set platform specific polarity inversion */
f5f0b7aa
GC
614 if (invert)
615 memset(val, 0xFF, NBANK(chip));
616 else
617 memset(val, 0, NBANK(chip));
618
619 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
620out:
621 return ret;
622}
623
3836309d 624static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
625{
626 int ret;
f5f0b7aa 627 u8 val[MAX_BANK];
33226ffd 628
f5f0b7aa 629 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
33226ffd
HZ
630 if (ret)
631 goto out;
f5f0b7aa 632 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
33226ffd
HZ
633 if (ret)
634 goto out;
635
636 /* set platform specific polarity inversion */
f5f0b7aa
GC
637 if (invert)
638 memset(val, 0xFF, NBANK(chip));
639 else
640 memset(val, 0, NBANK(chip));
c75a3772
NK
641 ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
642 if (ret)
643 goto out;
33226ffd 644
20a8a968 645 /* To enable register 6, 7 to control pull up and pull down */
f5f0b7aa 646 memset(val, 0x02, NBANK(chip));
c75a3772
NK
647 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
648 if (ret)
649 goto out;
33226ffd
HZ
650
651 return 0;
652out:
653 return ret;
654}
655
3836309d 656static int pca953x_probe(struct i2c_client *client,
3760f736 657 const struct i2c_device_id *id)
9e60fdcf 658{
f3dc3630
GL
659 struct pca953x_platform_data *pdata;
660 struct pca953x_chip *chip;
6a7b36aa 661 int irq_base = 0;
7ea2aa20 662 int ret;
6a7b36aa 663 u32 invert = 0;
9e60fdcf 664
b42748c9
LW
665 chip = devm_kzalloc(&client->dev,
666 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
667 if (chip == NULL)
668 return -ENOMEM;
669
e56aee18 670 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
671 if (pdata) {
672 irq_base = pdata->irq_base;
673 chip->gpio_start = pdata->gpio_base;
674 invert = pdata->invert;
675 chip->names = pdata->names;
676 } else {
4bb93349
MP
677 chip->gpio_start = -1;
678 irq_base = 0;
1965d303 679 }
9e60fdcf 680
681 chip->client = client;
682
c6664149
AS
683 chip->driver_data = id->driver_data;
684 chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
77906a54 685
6e20fb18
RS
686 mutex_init(&chip->i2c_lock);
687
9e60fdcf 688 /* initialize cached registers from their original values.
689 * we can't share this chip with another i2c master.
690 */
c6664149 691 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
f5e8ff48 692
33226ffd 693 if (chip->chip_type == PCA953X_TYPE)
7ea2aa20 694 ret = device_pca953x_init(chip, invert);
33226ffd 695 else
7ea2aa20
WS
696 ret = device_pca957x_init(chip, invert);
697 if (ret)
b42748c9 698 return ret;
9e60fdcf 699
7bcbce55 700 ret = gpiochip_add(&chip->gpio_chip);
89ea8bbe 701 if (ret)
b42748c9 702 return ret;
f5e8ff48 703
c6664149 704 ret = pca953x_irq_setup(chip, irq_base);
9e60fdcf 705 if (ret)
b42748c9 706 return ret;
9e60fdcf 707
c6dcf592 708 if (pdata && pdata->setup) {
9e60fdcf 709 ret = pdata->setup(client, chip->gpio_chip.base,
710 chip->gpio_chip.ngpio, pdata->context);
711 if (ret < 0)
712 dev_warn(&client->dev, "setup failed, %d\n", ret);
713 }
714
715 i2c_set_clientdata(client, chip);
716 return 0;
9e60fdcf 717}
718
f3dc3630 719static int pca953x_remove(struct i2c_client *client)
9e60fdcf 720{
e56aee18 721 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 722 struct pca953x_chip *chip = i2c_get_clientdata(client);
9e60fdcf 723 int ret = 0;
724
c6dcf592 725 if (pdata && pdata->teardown) {
9e60fdcf 726 ret = pdata->teardown(client, chip->gpio_chip.base,
727 chip->gpio_chip.ngpio, pdata->context);
728 if (ret < 0) {
729 dev_err(&client->dev, "%s failed, %d\n",
730 "teardown", ret);
731 return ret;
732 }
733 }
734
9f5132ae 735 gpiochip_remove(&chip->gpio_chip);
9e60fdcf 736
9e60fdcf 737 return 0;
738}
739
ed32620e 740static const struct of_device_id pca953x_dt_ids[] = {
89f5df01 741 { .compatible = "nxp,pca9505", },
ed32620e
MR
742 { .compatible = "nxp,pca9534", },
743 { .compatible = "nxp,pca9535", },
744 { .compatible = "nxp,pca9536", },
745 { .compatible = "nxp,pca9537", },
746 { .compatible = "nxp,pca9538", },
747 { .compatible = "nxp,pca9539", },
748 { .compatible = "nxp,pca9554", },
749 { .compatible = "nxp,pca9555", },
750 { .compatible = "nxp,pca9556", },
751 { .compatible = "nxp,pca9557", },
752 { .compatible = "nxp,pca9574", },
753 { .compatible = "nxp,pca9575", },
eb32b5aa 754 { .compatible = "nxp,pca9698", },
ed32620e
MR
755
756 { .compatible = "maxim,max7310", },
757 { .compatible = "maxim,max7312", },
758 { .compatible = "maxim,max7313", },
759 { .compatible = "maxim,max7315", },
760
761 { .compatible = "ti,pca6107", },
762 { .compatible = "ti,tca6408", },
763 { .compatible = "ti,tca6416", },
764 { .compatible = "ti,tca6424", },
e73760a6
AS
765
766 { .compatible = "exar,xra1202", },
ed32620e
MR
767 { }
768};
769
770MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
771
f3dc3630 772static struct i2c_driver pca953x_driver = {
9e60fdcf 773 .driver = {
f3dc3630 774 .name = "pca953x",
ed32620e 775 .of_match_table = pca953x_dt_ids,
9e60fdcf 776 },
f3dc3630
GL
777 .probe = pca953x_probe,
778 .remove = pca953x_remove,
3760f736 779 .id_table = pca953x_id,
9e60fdcf 780};
781
f3dc3630 782static int __init pca953x_init(void)
9e60fdcf 783{
f3dc3630 784 return i2c_add_driver(&pca953x_driver);
9e60fdcf 785}
2f8d1197
DB
786/* register after i2c postcore initcall and before
787 * subsys initcalls that may rely on these GPIOs
788 */
789subsys_initcall(pca953x_init);
9e60fdcf 790
f3dc3630 791static void __exit pca953x_exit(void)
9e60fdcf 792{
f3dc3630 793 i2c_del_driver(&pca953x_driver);
9e60fdcf 794}
f3dc3630 795module_exit(pca953x_exit);
9e60fdcf 796
797MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 798MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 799MODULE_LICENSE("GPL");