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b886d83c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
9e60fdcf | 2 | /* |
1e191695 | 3 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 4 | * |
5 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
6 | * Copyright (C) 2007 Marvell International Ltd. | |
7 | * | |
8 | * Derived from drivers/i2c/chips/pca9539.c | |
9e60fdcf | 9 | */ |
10 | ||
b413d7a0 | 11 | #include <linux/acpi.h> |
35d13d94 | 12 | #include <linux/bitmap.h> |
644f3da0 | 13 | #include <linux/gpio/driver.h> |
054ccdef | 14 | #include <linux/gpio/consumer.h> |
9e60fdcf | 15 | #include <linux/i2c.h> |
b413d7a0 AS |
16 | #include <linux/init.h> |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of_platform.h> | |
5877457a | 20 | #include <linux/platform_data/pca953x.h> |
49427232 | 21 | #include <linux/regmap.h> |
b413d7a0 | 22 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
b413d7a0 | 24 | |
9b8e3ec3 | 25 | #include <asm/unaligned.h> |
9e60fdcf | 26 | |
0950c19a NS |
27 | #define PCA953X_INPUT 0x00 |
28 | #define PCA953X_OUTPUT 0x01 | |
29 | #define PCA953X_INVERT 0x02 | |
30 | #define PCA953X_DIRECTION 0x03 | |
33226ffd | 31 | |
63b484c2 AS |
32 | #define REG_ADDR_MASK GENMASK(5, 0) |
33 | #define REG_ADDR_EXT BIT(6) | |
34 | #define REG_ADDR_AI BIT(7) | |
ae79c190 | 35 | |
0950c19a NS |
36 | #define PCA957X_IN 0x00 |
37 | #define PCA957X_INVRT 0x01 | |
38 | #define PCA957X_BKEN 0x02 | |
39 | #define PCA957X_PUPD 0x03 | |
40 | #define PCA957X_CFG 0x04 | |
41 | #define PCA957X_OUT 0x05 | |
42 | #define PCA957X_MSK 0x06 | |
43 | #define PCA957X_INTS 0x07 | |
33226ffd | 44 | |
6315d231 | 45 | #define PCAL953X_OUT_STRENGTH 0x20 |
0950c19a | 46 | #define PCAL953X_IN_LATCH 0x22 |
6315d231 NS |
47 | #define PCAL953X_PULL_EN 0x23 |
48 | #define PCAL953X_PULL_SEL 0x24 | |
0950c19a NS |
49 | #define PCAL953X_INT_MASK 0x25 |
50 | #define PCAL953X_INT_STAT 0x26 | |
6315d231 | 51 | #define PCAL953X_OUT_CONF 0x27 |
44896bea | 52 | |
a0ecbccc NS |
53 | #define PCAL6524_INT_EDGE 0x28 |
54 | #define PCAL6524_INT_CLR 0x2a | |
55 | #define PCAL6524_IN_STATUS 0x2b | |
56 | #define PCAL6524_OUT_INDCONF 0x2c | |
57 | #define PCAL6524_DEBOUNCE 0x2d | |
58 | ||
63b484c2 | 59 | #define PCA_GPIO_MASK GENMASK(7, 0) |
394aeef8 | 60 | |
63b484c2 AS |
61 | #define PCAL_GPIO_MASK GENMASK(4, 0) |
62 | #define PCAL_PINCTRL_MASK GENMASK(6, 5) | |
394aeef8 | 63 | |
63b484c2 AS |
64 | #define PCA_INT BIT(8) |
65 | #define PCA_PCAL BIT(9) | |
2870b3c5 | 66 | #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) |
63b484c2 AS |
67 | #define PCA953X_TYPE BIT(12) |
68 | #define PCA957X_TYPE BIT(13) | |
69 | #define PCA_TYPE_MASK GENMASK(15, 12) | |
c6664149 AS |
70 | |
71 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 72 | |
3760f736 | 73 | static const struct i2c_device_id pca953x_id[] = { |
12c7a4fc | 74 | { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, |
89f5df01 | 75 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
1421b447 | 76 | { "pca9506", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
77 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
78 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
79 | { "pca9536", 4 | PCA953X_TYPE, }, | |
80 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
81 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
82 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
83 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
84 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
85 | { "pca9556", 8 | PCA953X_TYPE, }, | |
86 | { "pca9557", 8 | PCA953X_TYPE, }, | |
87 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
88 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 89 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 90 | |
2870b3c5 AS |
91 | { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, |
92 | { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, | |
3ba3ff5c | 93 | { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, |
237d9616 | 94 | { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, |
2870b3c5 | 95 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, |
747e42a1 | 96 | |
33226ffd HZ |
97 | { "max7310", 8 | PCA953X_TYPE, }, |
98 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
99 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
100 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
1208c935 | 101 | { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
102 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, |
103 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
104 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 105 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 106 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
1b9a0c25 | 107 | { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 108 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 109 | { } |
f5e8ff48 | 110 | }; |
3760f736 | 111 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 112 | |
ba8c90c6 AS |
113 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
114 | ||
115 | #include <linux/dmi.h> | |
eb441337 AS |
116 | |
117 | static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; | |
118 | ||
119 | static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { | |
120 | { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, | |
121 | { } | |
122 | }; | |
123 | ||
124 | static int pca953x_acpi_get_irq(struct device *dev) | |
125 | { | |
126 | int ret; | |
127 | ||
128 | ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); | |
129 | if (ret) | |
130 | dev_warn(dev, "can't add GPIO ACPI mapping\n"); | |
131 | ||
132 | ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0); | |
133 | if (ret < 0) | |
134 | return ret; | |
135 | ||
136 | dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); | |
137 | return ret; | |
138 | } | |
ba8c90c6 AS |
139 | |
140 | static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { | |
141 | { | |
142 | /* | |
143 | * On Intel Galileo Gen 2 board the IRQ pin of one of | |
144 | * the I²C GPIO expanders, which has GpioInt() resource, | |
145 | * is provided as an absolute number instead of being | |
146 | * relative. Since first controller (gpio-sch.c) and | |
147 | * second (gpio-dwapb.c) are at the fixed bases, we may | |
148 | * safely refer to the number in the global space to get | |
149 | * an IRQ out of it. | |
150 | */ | |
151 | .matches = { | |
152 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), | |
153 | }, | |
154 | }, | |
155 | {} | |
156 | }; | |
ba8c90c6 AS |
157 | #endif |
158 | ||
f32517bf | 159 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
2870b3c5 | 160 | { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, |
f32517bf AS |
161 | { } |
162 | }; | |
163 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
164 | ||
f5f0b7aa GC |
165 | #define MAX_BANK 5 |
166 | #define BANK_SZ 8 | |
35d13d94 | 167 | #define MAX_LINE (MAX_BANK * BANK_SZ) |
f5f0b7aa | 168 | |
a246b819 | 169 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 170 | |
53661f3b BG |
171 | struct pca953x_reg_config { |
172 | int direction; | |
173 | int output; | |
174 | int input; | |
7a04aaa3 | 175 | int invert; |
53661f3b BG |
176 | }; |
177 | ||
178 | static const struct pca953x_reg_config pca953x_regs = { | |
179 | .direction = PCA953X_DIRECTION, | |
180 | .output = PCA953X_OUTPUT, | |
181 | .input = PCA953X_INPUT, | |
7a04aaa3 | 182 | .invert = PCA953X_INVERT, |
53661f3b BG |
183 | }; |
184 | ||
185 | static const struct pca953x_reg_config pca957x_regs = { | |
186 | .direction = PCA957X_CFG, | |
187 | .output = PCA957X_OUT, | |
188 | .input = PCA957X_IN, | |
7a04aaa3 | 189 | .invert = PCA957X_INVRT, |
53661f3b BG |
190 | }; |
191 | ||
f3dc3630 | 192 | struct pca953x_chip { |
9e60fdcf | 193 | unsigned gpio_start; |
6e20fb18 | 194 | struct mutex i2c_lock; |
49427232 | 195 | struct regmap *regmap; |
9e60fdcf | 196 | |
89ea8bbe MZ |
197 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
198 | struct mutex irq_lock; | |
35d13d94 AS |
199 | DECLARE_BITMAP(irq_mask, MAX_LINE); |
200 | DECLARE_BITMAP(irq_stat, MAX_LINE); | |
201 | DECLARE_BITMAP(irq_trig_raise, MAX_LINE); | |
202 | DECLARE_BITMAP(irq_trig_fall, MAX_LINE); | |
5c4fee63 | 203 | struct irq_chip irq_chip; |
89ea8bbe | 204 | #endif |
f70fbc15 | 205 | atomic_t wakeup_path; |
89ea8bbe | 206 | |
9e60fdcf | 207 | struct i2c_client *client; |
208 | struct gpio_chip gpio_chip; | |
62154991 | 209 | const char *const *names; |
c6664149 | 210 | unsigned long driver_data; |
e23efa31 | 211 | struct regulator *regulator; |
53661f3b BG |
212 | |
213 | const struct pca953x_reg_config *regs; | |
9e60fdcf | 214 | }; |
215 | ||
873d1e8e | 216 | static int pca953x_bank_shift(struct pca953x_chip *chip) |
f5f0b7aa | 217 | { |
873d1e8e MV |
218 | return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
219 | } | |
f5f0b7aa | 220 | |
49427232 MV |
221 | #define PCA953x_BANK_INPUT BIT(0) |
222 | #define PCA953x_BANK_OUTPUT BIT(1) | |
223 | #define PCA953x_BANK_POLARITY BIT(2) | |
224 | #define PCA953x_BANK_CONFIG BIT(3) | |
f5f0b7aa | 225 | |
49427232 MV |
226 | #define PCA957x_BANK_INPUT BIT(0) |
227 | #define PCA957x_BANK_POLARITY BIT(1) | |
228 | #define PCA957x_BANK_BUSHOLD BIT(2) | |
229 | #define PCA957x_BANK_CONFIG BIT(4) | |
230 | #define PCA957x_BANK_OUTPUT BIT(5) | |
231 | ||
232 | #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) | |
15add068 TP |
233 | #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) |
234 | #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) | |
49427232 MV |
235 | #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) |
236 | #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) | |
237 | ||
238 | /* | |
239 | * We care about the following registers: | |
240 | * - Standard set, below 0x40, each port can be replicated up to 8 times | |
241 | * - PCA953x standard | |
242 | * Input port 0x00 + 0 * bank_size R | |
243 | * Output port 0x00 + 1 * bank_size RW | |
244 | * Polarity Inversion port 0x00 + 2 * bank_size RW | |
245 | * Configuration port 0x00 + 3 * bank_size RW | |
246 | * - PCA957x with mixed up registers | |
247 | * Input port 0x00 + 0 * bank_size R | |
248 | * Polarity Inversion port 0x00 + 1 * bank_size RW | |
249 | * Bus hold port 0x00 + 2 * bank_size RW | |
250 | * Configuration port 0x00 + 4 * bank_size RW | |
251 | * Output port 0x00 + 5 * bank_size RW | |
252 | * | |
253 | * - Extended set, above 0x40, often chip specific. | |
254 | * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: | |
255 | * Input latch register 0x40 + 2 * bank_size RW | |
15add068 TP |
256 | * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW |
257 | * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW | |
49427232 MV |
258 | * Interrupt mask register 0x40 + 5 * bank_size RW |
259 | * Interrupt status register 0x40 + 6 * bank_size R | |
260 | * | |
261 | * - Registers with bit 0x80 set, the AI bit | |
262 | * The bit is cleared and the registers fall into one of the | |
263 | * categories above. | |
264 | */ | |
265 | ||
266 | static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, | |
267 | u32 checkbank) | |
268 | { | |
269 | int bank_shift = pca953x_bank_shift(chip); | |
270 | int bank = (reg & REG_ADDR_MASK) >> bank_shift; | |
271 | int offset = reg & (BIT(bank_shift) - 1); | |
272 | ||
273 | /* Special PCAL extended register check. */ | |
274 | if (reg & REG_ADDR_EXT) { | |
275 | if (!(chip->driver_data & PCA_PCAL)) | |
276 | return false; | |
277 | bank += 8; | |
f5f0b7aa GC |
278 | } |
279 | ||
49427232 MV |
280 | /* Register is not in the matching bank. */ |
281 | if (!(BIT(bank) & checkbank)) | |
282 | return false; | |
283 | ||
284 | /* Register is not within allowed range of bank. */ | |
285 | if (offset >= NBANK(chip)) | |
286 | return false; | |
287 | ||
288 | return true; | |
f5f0b7aa GC |
289 | } |
290 | ||
49427232 | 291 | static bool pca953x_readable_register(struct device *dev, unsigned int reg) |
f5f0b7aa | 292 | { |
49427232 MV |
293 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
294 | u32 bank; | |
f5f0b7aa | 295 | |
49427232 MV |
296 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
297 | bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | | |
298 | PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; | |
299 | } else { | |
300 | bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | | |
301 | PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | | |
302 | PCA957x_BANK_BUSHOLD; | |
303 | } | |
f5f0b7aa | 304 | |
49427232 | 305 | if (chip->driver_data & PCA_PCAL) { |
15add068 TP |
306 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | |
307 | PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | | |
49427232 | 308 | PCAL9xxx_BANK_IRQ_STAT; |
f5f0b7aa GC |
309 | } |
310 | ||
49427232 | 311 | return pca953x_check_register(chip, reg, bank); |
f5f0b7aa GC |
312 | } |
313 | ||
49427232 | 314 | static bool pca953x_writeable_register(struct device *dev, unsigned int reg) |
9e60fdcf | 315 | { |
49427232 MV |
316 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
317 | u32 bank; | |
f5e8ff48 | 318 | |
49427232 MV |
319 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
320 | bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | | |
321 | PCA953x_BANK_CONFIG; | |
322 | } else { | |
323 | bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | | |
324 | PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; | |
325 | } | |
c4d1cbd7 | 326 | |
49427232 | 327 | if (chip->driver_data & PCA_PCAL) |
15add068 TP |
328 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | |
329 | PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; | |
49427232 MV |
330 | |
331 | return pca953x_check_register(chip, reg, bank); | |
7acc66e3 BG |
332 | } |
333 | ||
49427232 | 334 | static bool pca953x_volatile_register(struct device *dev, unsigned int reg) |
7acc66e3 | 335 | { |
49427232 MV |
336 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
337 | u32 bank; | |
7acc66e3 | 338 | |
49427232 MV |
339 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) |
340 | bank = PCA953x_BANK_INPUT; | |
341 | else | |
342 | bank = PCA957x_BANK_INPUT; | |
343 | ||
344 | if (chip->driver_data & PCA_PCAL) | |
345 | bank |= PCAL9xxx_BANK_IRQ_STAT; | |
7acc66e3 | 346 | |
49427232 | 347 | return pca953x_check_register(chip, reg, bank); |
7acc66e3 | 348 | } |
f5e8ff48 | 349 | |
d04e779f | 350 | static const struct regmap_config pca953x_i2c_regmap = { |
49427232 MV |
351 | .reg_bits = 8, |
352 | .val_bits = 8, | |
353 | ||
354 | .readable_reg = pca953x_readable_register, | |
355 | .writeable_reg = pca953x_writeable_register, | |
356 | .volatile_reg = pca953x_volatile_register, | |
357 | ||
aa58a21a | 358 | .disable_locking = true, |
49427232 | 359 | .cache_type = REGCACHE_RBTREE, |
bcf41dc4 UKK |
360 | .max_register = 0x7f, |
361 | }; | |
362 | ||
363 | static const struct regmap_config pca953x_ai_i2c_regmap = { | |
364 | .reg_bits = 8, | |
365 | .val_bits = 8, | |
366 | ||
367 | .read_flag_mask = REG_ADDR_AI, | |
368 | .write_flag_mask = REG_ADDR_AI, | |
369 | ||
370 | .readable_reg = pca953x_readable_register, | |
371 | .writeable_reg = pca953x_writeable_register, | |
372 | .volatile_reg = pca953x_volatile_register, | |
373 | ||
ec3decd2 | 374 | .disable_locking = true, |
bcf41dc4 UKK |
375 | .cache_type = REGCACHE_RBTREE, |
376 | .max_register = 0x7f, | |
49427232 MV |
377 | }; |
378 | ||
6fdeb6cb | 379 | static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) |
7acc66e3 | 380 | { |
b32cecb4 | 381 | int bank_shift = pca953x_bank_shift(chip); |
d5dbf9c2 NS |
382 | int addr = (reg & PCAL_GPIO_MASK) << bank_shift; |
383 | int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; | |
b32cecb4 MV |
384 | u8 regaddr = pinctrl | addr | (off / BANK_SZ); |
385 | ||
b32cecb4 | 386 | return regaddr; |
7acc66e3 BG |
387 | } |
388 | ||
35d13d94 | 389 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) |
7acc66e3 | 390 | { |
6fdeb6cb | 391 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0); |
35d13d94 AS |
392 | u8 value[MAX_BANK]; |
393 | int i, ret; | |
394 | ||
395 | for (i = 0; i < NBANK(chip); i++) | |
396 | value[i] = bitmap_get_value8(val, i * BANK_SZ); | |
7acc66e3 | 397 | |
35d13d94 | 398 | ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); |
f5e8ff48 GL |
399 | if (ret < 0) { |
400 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 401 | return ret; |
f5e8ff48 GL |
402 | } |
403 | ||
404 | return 0; | |
9e60fdcf | 405 | } |
406 | ||
35d13d94 | 407 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) |
c6e3cf01 | 408 | { |
6fdeb6cb | 409 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0); |
35d13d94 AS |
410 | u8 value[MAX_BANK]; |
411 | int i, ret; | |
c6e3cf01 | 412 | |
35d13d94 | 413 | ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); |
9e60fdcf | 414 | if (ret < 0) { |
415 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 416 | return ret; |
9e60fdcf | 417 | } |
418 | ||
35d13d94 AS |
419 | for (i = 0; i < NBANK(chip); i++) |
420 | bitmap_set_value8(val, value[i], i * BANK_SZ); | |
421 | ||
9e60fdcf | 422 | return 0; |
423 | } | |
424 | ||
f3dc3630 | 425 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 426 | { |
468e67f6 | 427 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
6fdeb6cb | 428 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off); |
0f25fda8 | 429 | u8 bit = BIT(off % BANK_SZ); |
53661f3b | 430 | int ret; |
9e60fdcf | 431 | |
6e20fb18 | 432 | mutex_lock(&chip->i2c_lock); |
0f25fda8 | 433 | ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); |
6e20fb18 RS |
434 | mutex_unlock(&chip->i2c_lock); |
435 | return ret; | |
9e60fdcf | 436 | } |
437 | ||
f3dc3630 | 438 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 439 | unsigned off, int val) |
440 | { | |
468e67f6 | 441 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
6fdeb6cb UKK |
442 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off); |
443 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off); | |
0f25fda8 | 444 | u8 bit = BIT(off % BANK_SZ); |
53661f3b | 445 | int ret; |
9e60fdcf | 446 | |
6e20fb18 | 447 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 448 | /* set output level */ |
ec82d1eb | 449 | ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
9e60fdcf | 450 | if (ret) |
6e20fb18 | 451 | goto exit; |
9e60fdcf | 452 | |
9e60fdcf | 453 | /* then direction */ |
0f25fda8 | 454 | ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); |
6e20fb18 RS |
455 | exit: |
456 | mutex_unlock(&chip->i2c_lock); | |
457 | return ret; | |
9e60fdcf | 458 | } |
459 | ||
f3dc3630 | 460 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 461 | { |
468e67f6 | 462 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
6fdeb6cb | 463 | u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off); |
87813cf3 | 464 | u8 bit = BIT(off % BANK_SZ); |
ae79c190 | 465 | u32 reg_val; |
53661f3b | 466 | int ret; |
9e60fdcf | 467 | |
6e20fb18 | 468 | mutex_lock(&chip->i2c_lock); |
87813cf3 | 469 | ret = regmap_read(chip->regmap, inreg, ®_val); |
6e20fb18 | 470 | mutex_unlock(&chip->i2c_lock); |
540cffba AG |
471 | if (ret < 0) |
472 | return ret; | |
9e60fdcf | 473 | |
87813cf3 | 474 | return !!(reg_val & bit); |
9e60fdcf | 475 | } |
476 | ||
f3dc3630 | 477 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 478 | { |
468e67f6 | 479 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
6fdeb6cb | 480 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off); |
ec82d1eb | 481 | u8 bit = BIT(off % BANK_SZ); |
9e60fdcf | 482 | |
6e20fb18 | 483 | mutex_lock(&chip->i2c_lock); |
ec82d1eb | 484 | regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
6e20fb18 | 485 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 486 | } |
487 | ||
66e57192 AS |
488 | static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) |
489 | { | |
490 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
6fdeb6cb | 491 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off); |
0f25fda8 | 492 | u8 bit = BIT(off % BANK_SZ); |
66e57192 AS |
493 | u32 reg_val; |
494 | int ret; | |
495 | ||
496 | mutex_lock(&chip->i2c_lock); | |
0f25fda8 | 497 | ret = regmap_read(chip->regmap, dirreg, ®_val); |
66e57192 AS |
498 | mutex_unlock(&chip->i2c_lock); |
499 | if (ret < 0) | |
500 | return ret; | |
501 | ||
e42615ec MV |
502 | if (reg_val & bit) |
503 | return GPIO_LINE_DIRECTION_IN; | |
504 | ||
505 | return GPIO_LINE_DIRECTION_OUT; | |
66e57192 AS |
506 | } |
507 | ||
96d7c7b3 | 508 | static int pca953x_gpio_get_multiple(struct gpio_chip *gc, |
6f793485 | 509 | unsigned long *mask, unsigned long *bits) |
96d7c7b3 PT |
510 | { |
511 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
6f793485 AS |
512 | DECLARE_BITMAP(reg_val, MAX_LINE); |
513 | int ret; | |
514 | ||
515 | mutex_lock(&chip->i2c_lock); | |
516 | ret = pca953x_read_regs(chip, chip->regs->input, reg_val); | |
517 | mutex_unlock(&chip->i2c_lock); | |
518 | if (ret) | |
519 | return ret; | |
520 | ||
521 | bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); | |
522 | return 0; | |
96d7c7b3 PT |
523 | } |
524 | ||
b4818afe | 525 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
ea3d579d | 526 | unsigned long *mask, unsigned long *bits) |
b4818afe | 527 | { |
468e67f6 | 528 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
35d13d94 | 529 | DECLARE_BITMAP(reg_val, MAX_LINE); |
53661f3b | 530 | int ret; |
ea3d579d | 531 | |
b4818afe | 532 | mutex_lock(&chip->i2c_lock); |
ec82d1eb MV |
533 | ret = pca953x_read_regs(chip, chip->regs->output, reg_val); |
534 | if (ret) | |
535 | goto exit; | |
536 | ||
35d13d94 | 537 | bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); |
ea3d579d | 538 | |
ec82d1eb | 539 | pca953x_write_regs(chip, chip->regs->output, reg_val); |
b4818afe PR |
540 | exit: |
541 | mutex_unlock(&chip->i2c_lock); | |
542 | } | |
543 | ||
15add068 TP |
544 | static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, |
545 | unsigned int offset, | |
546 | unsigned long config) | |
547 | { | |
6fdeb6cb UKK |
548 | u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset); |
549 | u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset); | |
15add068 TP |
550 | u8 bit = BIT(offset % BANK_SZ); |
551 | int ret; | |
552 | ||
553 | /* | |
554 | * pull-up/pull-down configuration requires PCAL extended | |
555 | * registers | |
556 | */ | |
557 | if (!(chip->driver_data & PCA_PCAL)) | |
558 | return -ENOTSUPP; | |
559 | ||
560 | mutex_lock(&chip->i2c_lock); | |
561 | ||
15add068 TP |
562 | /* Configure pull-up/pull-down */ |
563 | if (config == PIN_CONFIG_BIAS_PULL_UP) | |
564 | ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); | |
565 | else if (config == PIN_CONFIG_BIAS_PULL_DOWN) | |
566 | ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); | |
55a9968c AS |
567 | else |
568 | ret = 0; | |
15add068 TP |
569 | if (ret) |
570 | goto exit; | |
571 | ||
55a9968c AS |
572 | /* Disable/Enable pull-up/pull-down */ |
573 | if (config == PIN_CONFIG_BIAS_DISABLE) | |
574 | ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); | |
575 | else | |
576 | ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); | |
15add068 TP |
577 | |
578 | exit: | |
579 | mutex_unlock(&chip->i2c_lock); | |
580 | return ret; | |
581 | } | |
582 | ||
583 | static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, | |
584 | unsigned long config) | |
585 | { | |
586 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
587 | ||
dc87f6dd | 588 | switch (pinconf_to_config_param(config)) { |
15add068 | 589 | case PIN_CONFIG_BIAS_PULL_UP: |
55a9968c | 590 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: |
15add068 | 591 | case PIN_CONFIG_BIAS_PULL_DOWN: |
55a9968c | 592 | case PIN_CONFIG_BIAS_DISABLE: |
15add068 TP |
593 | return pca953x_gpio_set_pull_up_down(chip, offset, config); |
594 | default: | |
595 | return -ENOTSUPP; | |
596 | } | |
597 | } | |
598 | ||
f5e8ff48 | 599 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 600 | { |
601 | struct gpio_chip *gc; | |
602 | ||
603 | gc = &chip->gpio_chip; | |
604 | ||
f3dc3630 GL |
605 | gc->direction_input = pca953x_gpio_direction_input; |
606 | gc->direction_output = pca953x_gpio_direction_output; | |
607 | gc->get = pca953x_gpio_get_value; | |
608 | gc->set = pca953x_gpio_set_value; | |
66e57192 | 609 | gc->get_direction = pca953x_gpio_get_direction; |
96d7c7b3 | 610 | gc->get_multiple = pca953x_gpio_get_multiple; |
b4818afe | 611 | gc->set_multiple = pca953x_gpio_set_multiple; |
15add068 | 612 | gc->set_config = pca953x_gpio_set_config; |
9fb1f39e | 613 | gc->can_sleep = true; |
9e60fdcf | 614 | |
615 | gc->base = chip->gpio_start; | |
f5e8ff48 | 616 | gc->ngpio = gpios; |
5128f8d4 | 617 | gc->label = dev_name(&chip->client->dev); |
58383c78 | 618 | gc->parent = &chip->client->dev; |
d72cbed0 | 619 | gc->owner = THIS_MODULE; |
77906a54 | 620 | gc->names = chip->names; |
9e60fdcf | 621 | } |
622 | ||
89ea8bbe | 623 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 624 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 625 | { |
7bcbce55 | 626 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 627 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
2688302b | 628 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
89ea8bbe | 629 | |
2688302b | 630 | clear_bit(hwirq, chip->irq_mask); |
89ea8bbe MZ |
631 | } |
632 | ||
6f5cfc0e | 633 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 634 | { |
7bcbce55 | 635 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 636 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
2688302b | 637 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
89ea8bbe | 638 | |
2688302b | 639 | set_bit(hwirq, chip->irq_mask); |
89ea8bbe MZ |
640 | } |
641 | ||
2a9a2f27 GU |
642 | static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) |
643 | { | |
644 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
645 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
646 | ||
f70fbc15 GU |
647 | if (on) |
648 | atomic_inc(&chip->wakeup_path); | |
649 | else | |
650 | atomic_dec(&chip->wakeup_path); | |
651 | ||
2a9a2f27 GU |
652 | return irq_set_irq_wake(chip->client->irq, on); |
653 | } | |
654 | ||
6f5cfc0e | 655 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 656 | { |
7bcbce55 | 657 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 658 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
659 | |
660 | mutex_lock(&chip->irq_lock); | |
661 | } | |
662 | ||
6f5cfc0e | 663 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 664 | { |
7bcbce55 | 665 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 666 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
35d13d94 AS |
667 | DECLARE_BITMAP(irq_mask, MAX_LINE); |
668 | DECLARE_BITMAP(reg_direction, MAX_LINE); | |
669 | int level; | |
0f25fda8 | 670 | |
44896bea YL |
671 | if (chip->driver_data & PCA_PCAL) { |
672 | /* Enable latch on interrupt-enabled inputs */ | |
673 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
674 | ||
35d13d94 | 675 | bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); |
44896bea YL |
676 | |
677 | /* Unmask enabled interrupts */ | |
35d13d94 | 678 | pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); |
44896bea | 679 | } |
a2cb9aeb | 680 | |
0b22c25e AS |
681 | /* Switch direction to input if needed */ |
682 | pca953x_read_regs(chip, chip->regs->direction, reg_direction); | |
683 | ||
35d13d94 | 684 | bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); |
0b22c25e | 685 | bitmap_complement(reg_direction, reg_direction, gc->ngpio); |
35d13d94 AS |
686 | bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio); |
687 | ||
a2cb9aeb | 688 | /* Look for any newly setup interrupt */ |
35d13d94 AS |
689 | for_each_set_bit(level, irq_mask, gc->ngpio) |
690 | pca953x_gpio_direction_input(&chip->gpio_chip, level); | |
89ea8bbe MZ |
691 | |
692 | mutex_unlock(&chip->irq_lock); | |
693 | } | |
694 | ||
6f5cfc0e | 695 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 696 | { |
7bcbce55 | 697 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 698 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
2688302b | 699 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
89ea8bbe MZ |
700 | |
701 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
702 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 703 | d->irq, type); |
89ea8bbe MZ |
704 | return -EINVAL; |
705 | } | |
706 | ||
2688302b AS |
707 | assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); |
708 | assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); | |
89ea8bbe | 709 | |
a2cb9aeb | 710 | return 0; |
89ea8bbe MZ |
711 | } |
712 | ||
0a70fe00 GD |
713 | static void pca953x_irq_shutdown(struct irq_data *d) |
714 | { | |
c378b3aa MW |
715 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
716 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
2688302b | 717 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
0a70fe00 | 718 | |
2688302b AS |
719 | clear_bit(hwirq, chip->irq_trig_raise); |
720 | clear_bit(hwirq, chip->irq_trig_fall); | |
0a70fe00 GD |
721 | } |
722 | ||
35d13d94 | 723 | static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) |
89ea8bbe | 724 | { |
35d13d94 AS |
725 | struct gpio_chip *gc = &chip->gpio_chip; |
726 | DECLARE_BITMAP(reg_direction, MAX_LINE); | |
727 | DECLARE_BITMAP(old_stat, MAX_LINE); | |
728 | DECLARE_BITMAP(cur_stat, MAX_LINE); | |
729 | DECLARE_BITMAP(new_stat, MAX_LINE); | |
730 | DECLARE_BITMAP(trigger, MAX_LINE); | |
731 | int ret; | |
33226ffd | 732 | |
44896bea YL |
733 | if (chip->driver_data & PCA_PCAL) { |
734 | /* Read the current interrupt status from the device */ | |
735 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
736 | if (ret) | |
737 | return false; | |
738 | ||
739 | /* Check latched inputs and clear interrupt status */ | |
0a0a0219 | 740 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
44896bea YL |
741 | if (ret) |
742 | return false; | |
743 | ||
35d13d94 AS |
744 | /* Apply filter for rising/falling edge selection */ |
745 | bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio); | |
746 | ||
747 | bitmap_and(pending, new_stat, trigger, gc->ngpio); | |
44896bea | 748 | |
35d13d94 | 749 | return !bitmap_empty(pending, gc->ngpio); |
44896bea YL |
750 | } |
751 | ||
53661f3b | 752 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 753 | if (ret) |
b6ac1280 | 754 | return false; |
89ea8bbe MZ |
755 | |
756 | /* Remove output pins from the equation */ | |
438b6c20 | 757 | pca953x_read_regs(chip, chip->regs->direction, reg_direction); |
89ea8bbe | 758 | |
35d13d94 | 759 | bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); |
89ea8bbe | 760 | |
35d13d94 AS |
761 | bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); |
762 | bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); | |
763 | bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); | |
f5f0b7aa | 764 | |
35d13d94 | 765 | if (bitmap_empty(trigger, gc->ngpio)) |
b6ac1280 | 766 | return false; |
89ea8bbe | 767 | |
35d13d94 | 768 | bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); |
89ea8bbe | 769 | |
35d13d94 AS |
770 | bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); |
771 | bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); | |
772 | bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio); | |
773 | bitmap_and(pending, new_stat, trigger, gc->ngpio); | |
89ea8bbe | 774 | |
35d13d94 | 775 | return !bitmap_empty(pending, gc->ngpio); |
89ea8bbe MZ |
776 | } |
777 | ||
778 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
779 | { | |
780 | struct pca953x_chip *chip = devid; | |
35d13d94 | 781 | struct gpio_chip *gc = &chip->gpio_chip; |
e09e200e | 782 | DECLARE_BITMAP(pending, MAX_LINE); |
35d13d94 | 783 | int level; |
064c73af | 784 | bool ret; |
89ea8bbe | 785 | |
e09e200e AS |
786 | bitmap_zero(pending, MAX_LINE); |
787 | ||
064c73af AS |
788 | mutex_lock(&chip->i2c_lock); |
789 | ret = pca953x_irq_pending(chip, pending); | |
790 | mutex_unlock(&chip->i2c_lock); | |
89ea8bbe | 791 | |
8b81edd8 MZ |
792 | if (ret) { |
793 | ret = 0; | |
794 | ||
795 | for_each_set_bit(level, pending, gc->ngpio) { | |
796 | int nested_irq = irq_find_mapping(gc->irq.domain, level); | |
797 | ||
798 | if (unlikely(nested_irq <= 0)) { | |
799 | dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); | |
800 | continue; | |
801 | } | |
802 | ||
803 | handle_nested_irq(nested_irq); | |
804 | ret = 1; | |
805 | } | |
806 | } | |
89ea8bbe | 807 | |
064c73af | 808 | return IRQ_RETVAL(ret); |
89ea8bbe MZ |
809 | } |
810 | ||
b27d8517 | 811 | static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) |
89ea8bbe MZ |
812 | { |
813 | struct i2c_client *client = chip->client; | |
5c4fee63 | 814 | struct irq_chip *irq_chip = &chip->irq_chip; |
35d13d94 AS |
815 | DECLARE_BITMAP(reg_direction, MAX_LINE); |
816 | DECLARE_BITMAP(irq_stat, MAX_LINE); | |
edee3bc6 | 817 | struct gpio_irq_chip *girq; |
35d13d94 | 818 | int ret; |
89ea8bbe | 819 | |
ba8c90c6 AS |
820 | if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { |
821 | ret = pca953x_acpi_get_irq(&client->dev); | |
822 | if (ret > 0) | |
823 | client->irq = ret; | |
824 | } | |
825 | ||
7341fa7a TP |
826 | if (!client->irq) |
827 | return 0; | |
89ea8bbe | 828 | |
7341fa7a TP |
829 | if (irq_base == -1) |
830 | return 0; | |
89ea8bbe | 831 | |
7341fa7a TP |
832 | if (!(chip->driver_data & PCA_INT)) |
833 | return 0; | |
fdd50409 | 834 | |
35d13d94 | 835 | ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); |
7341fa7a TP |
836 | if (ret) |
837 | return ret; | |
838 | ||
839 | /* | |
840 | * There is no way to know which GPIO line generated the | |
841 | * interrupt. We have to rely on the previous read for | |
842 | * this purpose. | |
843 | */ | |
438b6c20 | 844 | pca953x_read_regs(chip, chip->regs->direction, reg_direction); |
35d13d94 | 845 | bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio); |
7341fa7a TP |
846 | mutex_init(&chip->irq_lock); |
847 | ||
2a93a0da | 848 | irq_chip->name = dev_name(&client->dev); |
5c4fee63 TP |
849 | irq_chip->irq_mask = pca953x_irq_mask; |
850 | irq_chip->irq_unmask = pca953x_irq_unmask; | |
2a9a2f27 | 851 | irq_chip->irq_set_wake = pca953x_irq_set_wake; |
5c4fee63 TP |
852 | irq_chip->irq_bus_lock = pca953x_irq_bus_lock; |
853 | irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock; | |
854 | irq_chip->irq_set_type = pca953x_irq_set_type; | |
855 | irq_chip->irq_shutdown = pca953x_irq_shutdown; | |
856 | ||
edee3bc6 LW |
857 | girq = &chip->gpio_chip.irq; |
858 | girq->chip = irq_chip; | |
859 | /* This will let us handle the parent IRQ in the driver */ | |
860 | girq->parent_handler = NULL; | |
861 | girq->num_parents = 0; | |
862 | girq->parents = NULL; | |
863 | girq->default_type = IRQ_TYPE_NONE; | |
864 | girq->handler = handle_simple_irq; | |
865 | girq->threaded = true; | |
866 | girq->first = irq_base; /* FIXME: get rid of this */ | |
7341fa7a | 867 | |
2a93a0da AS |
868 | ret = devm_request_threaded_irq(&client->dev, client->irq, |
869 | NULL, pca953x_irq_handler, | |
870 | IRQF_ONESHOT | IRQF_SHARED, | |
871 | dev_name(&client->dev), chip); | |
872 | if (ret) { | |
873 | dev_err(&client->dev, "failed to request irq %d\n", | |
874 | client->irq); | |
875 | return ret; | |
876 | } | |
877 | ||
89ea8bbe | 878 | return 0; |
89ea8bbe MZ |
879 | } |
880 | ||
89ea8bbe MZ |
881 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
882 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 883 | int irq_base) |
89ea8bbe MZ |
884 | { |
885 | struct i2c_client *client = chip->client; | |
89ea8bbe | 886 | |
72b38caf | 887 | if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
888 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
889 | ||
890 | return 0; | |
891 | } | |
89ea8bbe MZ |
892 | #endif |
893 | ||
7a04aaa3 | 894 | static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) |
33226ffd | 895 | { |
35d13d94 | 896 | DECLARE_BITMAP(val, MAX_LINE); |
33226ffd HZ |
897 | int ret; |
898 | ||
ec82d1eb MV |
899 | ret = regcache_sync_region(chip->regmap, chip->regs->output, |
900 | chip->regs->output + NBANK(chip)); | |
6dd6a2d2 | 901 | if (ret) |
33226ffd HZ |
902 | goto out; |
903 | ||
0f25fda8 MV |
904 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, |
905 | chip->regs->direction + NBANK(chip)); | |
6dd6a2d2 | 906 | if (ret) |
33226ffd HZ |
907 | goto out; |
908 | ||
909 | /* set platform specific polarity inversion */ | |
f5f0b7aa | 910 | if (invert) |
35d13d94 | 911 | bitmap_fill(val, MAX_LINE); |
f5f0b7aa | 912 | else |
35d13d94 | 913 | bitmap_zero(val, MAX_LINE); |
f5f0b7aa | 914 | |
7a04aaa3 | 915 | ret = pca953x_write_regs(chip, chip->regs->invert, val); |
33226ffd HZ |
916 | out: |
917 | return ret; | |
918 | } | |
919 | ||
3836309d | 920 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd | 921 | { |
35d13d94 | 922 | DECLARE_BITMAP(val, MAX_LINE); |
8c1f1c34 | 923 | unsigned int i; |
33226ffd | 924 | int ret; |
33226ffd | 925 | |
7a04aaa3 | 926 | ret = device_pca95xx_init(chip, invert); |
c75a3772 NK |
927 | if (ret) |
928 | goto out; | |
33226ffd | 929 | |
20a8a968 | 930 | /* To enable register 6, 7 to control pull up and pull down */ |
8c1f1c34 AS |
931 | for (i = 0; i < NBANK(chip); i++) |
932 | bitmap_set_value8(val, 0x02, i * BANK_SZ); | |
933 | ||
c75a3772 NK |
934 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
935 | if (ret) | |
936 | goto out; | |
33226ffd HZ |
937 | |
938 | return 0; | |
939 | out: | |
940 | return ret; | |
941 | } | |
942 | ||
3836309d | 943 | static int pca953x_probe(struct i2c_client *client, |
b27d8517 | 944 | const struct i2c_device_id *i2c_id) |
9e60fdcf | 945 | { |
f3dc3630 GL |
946 | struct pca953x_platform_data *pdata; |
947 | struct pca953x_chip *chip; | |
6a7b36aa | 948 | int irq_base = 0; |
7ea2aa20 | 949 | int ret; |
6a7b36aa | 950 | u32 invert = 0; |
e23efa31 | 951 | struct regulator *reg; |
bcf41dc4 | 952 | const struct regmap_config *regmap_config; |
9e60fdcf | 953 | |
b27d8517 | 954 | chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); |
1965d303 NC |
955 | if (chip == NULL) |
956 | return -ENOMEM; | |
957 | ||
e56aee18 | 958 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
959 | if (pdata) { |
960 | irq_base = pdata->irq_base; | |
961 | chip->gpio_start = pdata->gpio_base; | |
962 | invert = pdata->invert; | |
963 | chip->names = pdata->names; | |
964 | } else { | |
054ccdef SL |
965 | struct gpio_desc *reset_gpio; |
966 | ||
4bb93349 MP |
967 | chip->gpio_start = -1; |
968 | irq_base = 0; | |
054ccdef | 969 | |
96530b37 AS |
970 | /* |
971 | * See if we need to de-assert a reset pin. | |
972 | * | |
973 | * There is no known ACPI-enabled platforms that are | |
974 | * using "reset" GPIO. Otherwise any of those platform | |
975 | * must use _DSD method with corresponding property. | |
976 | */ | |
054ccdef SL |
977 | reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", |
978 | GPIOD_OUT_LOW); | |
979 | if (IS_ERR(reset_gpio)) | |
980 | return PTR_ERR(reset_gpio); | |
1965d303 | 981 | } |
9e60fdcf | 982 | |
983 | chip->client = client; | |
984 | ||
e23efa31 | 985 | reg = devm_regulator_get(&client->dev, "vcc"); |
ca6a77eb KK |
986 | if (IS_ERR(reg)) |
987 | return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n"); | |
988 | ||
e23efa31 PR |
989 | ret = regulator_enable(reg); |
990 | if (ret) { | |
991 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
992 | return ret; | |
993 | } | |
994 | chip->regulator = reg; | |
995 | ||
6212e1d6 WS |
996 | if (i2c_id) { |
997 | chip->driver_data = i2c_id->driver_data; | |
f32517bf | 998 | } else { |
8eeb467d AS |
999 | const void *match; |
1000 | ||
1001 | match = device_get_match_data(&client->dev); | |
1002 | if (!match) { | |
1003 | ret = -ENODEV; | |
1004 | goto err_exit; | |
6f29c9af | 1005 | } |
8eeb467d AS |
1006 | |
1007 | chip->driver_data = (uintptr_t)match; | |
f32517bf AS |
1008 | } |
1009 | ||
49427232 MV |
1010 | i2c_set_clientdata(client, chip); |
1011 | ||
bcf41dc4 UKK |
1012 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
1013 | ||
1014 | if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { | |
1015 | dev_info(&client->dev, "using AI\n"); | |
1016 | regmap_config = &pca953x_ai_i2c_regmap; | |
1017 | } else { | |
1018 | dev_info(&client->dev, "using no AI\n"); | |
1019 | regmap_config = &pca953x_i2c_regmap; | |
1020 | } | |
1021 | ||
1022 | chip->regmap = devm_regmap_init_i2c(client, regmap_config); | |
49427232 MV |
1023 | if (IS_ERR(chip->regmap)) { |
1024 | ret = PTR_ERR(chip->regmap); | |
1025 | goto err_exit; | |
1026 | } | |
1027 | ||
0f25fda8 MV |
1028 | regcache_mark_dirty(chip->regmap); |
1029 | ||
6e20fb18 | 1030 | mutex_init(&chip->i2c_lock); |
74f47f07 BG |
1031 | /* |
1032 | * In case we have an i2c-mux controlled by a GPIO provided by an | |
1033 | * expander using the same driver higher on the device tree, read the | |
1034 | * i2c adapter nesting depth and use the retrieved value as lockdep | |
1035 | * subclass for chip->i2c_lock. | |
1036 | * | |
1037 | * REVISIT: This solution is not complete. It protects us from lockdep | |
1038 | * false positives when the expander controlling the i2c-mux is on | |
1039 | * a different level on the device tree, but not when it's on the same | |
1040 | * level on a different branch (in which case the subclass number | |
1041 | * would be the same). | |
1042 | * | |
1043 | * TODO: Once a correct solution is developed, a similar fix should be | |
1044 | * applied to all other i2c-controlled GPIO expanders (and potentially | |
1045 | * regmap-i2c). | |
1046 | */ | |
559b4699 BG |
1047 | lockdep_set_subclass(&chip->i2c_lock, |
1048 | i2c_adapter_depth(client->adapter)); | |
6e20fb18 | 1049 | |
9e60fdcf | 1050 | /* initialize cached registers from their original values. |
1051 | * we can't share this chip with another i2c master. | |
1052 | */ | |
f5e8ff48 | 1053 | |
7a04aaa3 MV |
1054 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
1055 | chip->regs = &pca953x_regs; | |
1056 | ret = device_pca95xx_init(chip, invert); | |
7acc66e3 | 1057 | } else { |
7a04aaa3 | 1058 | chip->regs = &pca957x_regs; |
7ea2aa20 | 1059 | ret = device_pca957x_init(chip, invert); |
7a04aaa3 | 1060 | } |
7ea2aa20 | 1061 | if (ret) |
e23efa31 | 1062 | goto err_exit; |
9e60fdcf | 1063 | |
edee3bc6 | 1064 | ret = pca953x_irq_setup(chip, irq_base); |
89ea8bbe | 1065 | if (ret) |
e23efa31 | 1066 | goto err_exit; |
f5e8ff48 | 1067 | |
edee3bc6 | 1068 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
9e60fdcf | 1069 | if (ret) |
e23efa31 | 1070 | goto err_exit; |
9e60fdcf | 1071 | |
c6dcf592 | 1072 | if (pdata && pdata->setup) { |
9e60fdcf | 1073 | ret = pdata->setup(client, chip->gpio_chip.base, |
b27d8517 | 1074 | chip->gpio_chip.ngpio, pdata->context); |
9e60fdcf | 1075 | if (ret < 0) |
1076 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
1077 | } | |
1078 | ||
9e60fdcf | 1079 | return 0; |
e23efa31 PR |
1080 | |
1081 | err_exit: | |
1082 | regulator_disable(chip->regulator); | |
1083 | return ret; | |
9e60fdcf | 1084 | } |
1085 | ||
f3dc3630 | 1086 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 1087 | { |
e56aee18 | 1088 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 1089 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
d147d548 | 1090 | int ret; |
9e60fdcf | 1091 | |
c6dcf592 | 1092 | if (pdata && pdata->teardown) { |
9e60fdcf | 1093 | ret = pdata->teardown(client, chip->gpio_chip.base, |
b27d8517 | 1094 | chip->gpio_chip.ngpio, pdata->context); |
e23efa31 | 1095 | if (ret < 0) |
f4160faa | 1096 | dev_err(&client->dev, "teardown failed, %d\n", ret); |
bf62efeb AB |
1097 | } else { |
1098 | ret = 0; | |
9e60fdcf | 1099 | } |
1100 | ||
e23efa31 PR |
1101 | regulator_disable(chip->regulator); |
1102 | ||
1103 | return ret; | |
9e60fdcf | 1104 | } |
1105 | ||
b7657430 MV |
1106 | #ifdef CONFIG_PM_SLEEP |
1107 | static int pca953x_regcache_sync(struct device *dev) | |
1108 | { | |
1109 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1110 | int ret; | |
1111 | ||
1112 | /* | |
1113 | * The ordering between direction and output is important, | |
1114 | * sync these registers first and only then sync the rest. | |
1115 | */ | |
1116 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, | |
1117 | chip->regs->direction + NBANK(chip)); | |
6dd6a2d2 | 1118 | if (ret) { |
b7657430 MV |
1119 | dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); |
1120 | return ret; | |
1121 | } | |
1122 | ||
1123 | ret = regcache_sync_region(chip->regmap, chip->regs->output, | |
1124 | chip->regs->output + NBANK(chip)); | |
6dd6a2d2 | 1125 | if (ret) { |
b7657430 MV |
1126 | dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); |
1127 | return ret; | |
1128 | } | |
1129 | ||
1130 | #ifdef CONFIG_GPIO_PCA953X_IRQ | |
1131 | if (chip->driver_data & PCA_PCAL) { | |
1132 | ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, | |
1133 | PCAL953X_IN_LATCH + NBANK(chip)); | |
6dd6a2d2 | 1134 | if (ret) { |
b7657430 MV |
1135 | dev_err(dev, "Failed to sync INT latch registers: %d\n", |
1136 | ret); | |
1137 | return ret; | |
1138 | } | |
1139 | ||
1140 | ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, | |
1141 | PCAL953X_INT_MASK + NBANK(chip)); | |
6dd6a2d2 | 1142 | if (ret) { |
b7657430 MV |
1143 | dev_err(dev, "Failed to sync INT mask registers: %d\n", |
1144 | ret); | |
1145 | return ret; | |
1146 | } | |
1147 | } | |
1148 | #endif | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | static int pca953x_suspend(struct device *dev) | |
1154 | { | |
1155 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1156 | ||
1157 | regcache_cache_only(chip->regmap, true); | |
1158 | ||
f70fbc15 GU |
1159 | if (atomic_read(&chip->wakeup_path)) |
1160 | device_set_wakeup_path(dev); | |
1161 | else | |
1162 | regulator_disable(chip->regulator); | |
b7657430 MV |
1163 | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | static int pca953x_resume(struct device *dev) | |
1168 | { | |
1169 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1170 | int ret; | |
1171 | ||
f70fbc15 GU |
1172 | if (!atomic_read(&chip->wakeup_path)) { |
1173 | ret = regulator_enable(chip->regulator); | |
6dd6a2d2 | 1174 | if (ret) { |
f70fbc15 GU |
1175 | dev_err(dev, "Failed to enable regulator: %d\n", ret); |
1176 | return 0; | |
1177 | } | |
b7657430 MV |
1178 | } |
1179 | ||
1180 | regcache_cache_only(chip->regmap, false); | |
1181 | regcache_mark_dirty(chip->regmap); | |
1182 | ret = pca953x_regcache_sync(dev); | |
1183 | if (ret) | |
1184 | return ret; | |
1185 | ||
1186 | ret = regcache_sync(chip->regmap); | |
6dd6a2d2 | 1187 | if (ret) { |
b7657430 MV |
1188 | dev_err(dev, "Failed to restore register map: %d\n", ret); |
1189 | return ret; | |
1190 | } | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | #endif | |
1195 | ||
6f29c9af BD |
1196 | /* convenience to stop overlong match-table lines */ |
1197 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
1198 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
1199 | ||
ed32620e | 1200 | static const struct of_device_id pca953x_dt_ids[] = { |
12c7a4fc | 1201 | { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, |
6f29c9af | 1202 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
1421b447 | 1203 | { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, |
6f29c9af BD |
1204 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, |
1205 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
1206 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
1207 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
1208 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
1209 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
1210 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
1211 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
1212 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
1213 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
1214 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
1215 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
1216 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
1217 | ||
01769c47 | 1218 | { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, |
0cdf21b3 | 1219 | { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, |
3ba3ff5c | 1220 | { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, |
237d9616 | 1221 | { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, |
0cdf21b3 | 1222 | { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, |
3a711e0d | 1223 | |
6f29c9af BD |
1224 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, |
1225 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
1226 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
1227 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
1208c935 | 1228 | { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
1229 | |
1230 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 1231 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
1232 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
1233 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
1234 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
8b74ae41 | 1235 | { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, |
6f29c9af | 1236 | |
932002f0 | 1237 | { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, |
8a64e557 | 1238 | { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, |
6d49b3a0 | 1239 | { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
1240 | |
1241 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
1242 | { } |
1243 | }; | |
1244 | ||
1245 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
1246 | ||
b7657430 MV |
1247 | static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); |
1248 | ||
f3dc3630 | 1249 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 1250 | .driver = { |
f3dc3630 | 1251 | .name = "pca953x", |
b7657430 | 1252 | .pm = &pca953x_pm_ops, |
ed32620e | 1253 | .of_match_table = pca953x_dt_ids, |
74910e15 | 1254 | .acpi_match_table = pca953x_acpi_ids, |
9e60fdcf | 1255 | }, |
f3dc3630 GL |
1256 | .probe = pca953x_probe, |
1257 | .remove = pca953x_remove, | |
3760f736 | 1258 | .id_table = pca953x_id, |
9e60fdcf | 1259 | }; |
1260 | ||
f3dc3630 | 1261 | static int __init pca953x_init(void) |
9e60fdcf | 1262 | { |
f3dc3630 | 1263 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 1264 | } |
2f8d1197 DB |
1265 | /* register after i2c postcore initcall and before |
1266 | * subsys initcalls that may rely on these GPIOs | |
1267 | */ | |
1268 | subsys_initcall(pca953x_init); | |
9e60fdcf | 1269 | |
f3dc3630 | 1270 | static void __exit pca953x_exit(void) |
9e60fdcf | 1271 | { |
f3dc3630 | 1272 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 1273 | } |
f3dc3630 | 1274 | module_exit(pca953x_exit); |
9e60fdcf | 1275 | |
1276 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 1277 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 1278 | MODULE_LICENSE("GPL"); |