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gpio: pcf857x: call the gpio user handler iff gpio_to_irq is done
[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-pcf857x.c
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15fae37d 1/*
c103de24 2 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
15fae37d
DB
3 *
4 * Copyright (C) 2007 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
d120c17f 21#include <linux/gpio.h>
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DB
22#include <linux/i2c.h>
23#include <linux/i2c/pcf857x.h>
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KM
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/irqdomain.h>
c990d6cb 27#include <linux/kernel.h>
bb207ef1 28#include <linux/module.h>
c990d6cb 29#include <linux/slab.h>
6e20a0a4 30#include <linux/spinlock.h>
15fae37d 31
15fae37d 32
3760f736
JD
33static const struct i2c_device_id pcf857x_id[] = {
34 { "pcf8574", 8 },
4ba2ccb8 35 { "pcf8574a", 8 },
3760f736
JD
36 { "pca8574", 8 },
37 { "pca9670", 8 },
38 { "pca9672", 8 },
39 { "pca9674", 8 },
40 { "pcf8575", 16 },
41 { "pca8575", 16 },
42 { "pca9671", 16 },
43 { "pca9673", 16 },
44 { "pca9675", 16 },
1673ad52
DB
45 { "max7328", 8 },
46 { "max7329", 8 },
02130490 47 { "tca9554", 8 },
3760f736
JD
48 { }
49};
50MODULE_DEVICE_TABLE(i2c, pcf857x_id);
51
15fae37d
DB
52/*
53 * The pcf857x, pca857x, and pca967x chips only expose one read and one
54 * write register. Writing a "one" bit (to match the reset state) lets
55 * that pin be used as an input; it's not an open-drain model, but acts
56 * a bit like one. This is described as "quasi-bidirectional"; read the
57 * chip documentation for details.
58 *
59 * Many other I2C GPIO expander chips (like the pca953x models) have
60 * more complex register models and more conventional circuitry using
61 * push/pull drivers. They often use the same 0x20..0x27 addresses as
62 * pcf857x parts, making the "legacy" I2C driver model problematic.
63 */
64struct pcf857x {
65 struct gpio_chip chip;
66 struct i2c_client *client;
1673ad52 67 struct mutex lock; /* protect 'out' */
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68 struct irq_domain *irq_domain; /* for irq demux */
69 spinlock_t slock; /* protect irq demux */
15fae37d 70 unsigned out; /* software latch */
6e20a0a4 71 unsigned status; /* current status */
21fd3cd1 72 unsigned irq_mapped; /* mapped gpio irqs */
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KM
73
74 int (*write)(struct i2c_client *client, unsigned data);
75 int (*read)(struct i2c_client *client);
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76};
77
78/*-------------------------------------------------------------------------*/
79
80/* Talk to 8-bit I/O expander */
81
0c65ddd4 82static int i2c_write_le8(struct i2c_client *client, unsigned data)
15fae37d 83{
0c65ddd4 84 return i2c_smbus_write_byte(client, data);
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DB
85}
86
0c65ddd4 87static int i2c_read_le8(struct i2c_client *client)
15fae37d 88{
0c65ddd4 89 return (int)i2c_smbus_read_byte(client);
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DB
90}
91
15fae37d
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92/* Talk to 16-bit I/O expander */
93
0c65ddd4 94static int i2c_write_le16(struct i2c_client *client, unsigned word)
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DB
95{
96 u8 buf[2] = { word & 0xff, word >> 8, };
97 int status;
98
99 status = i2c_master_send(client, buf, 2);
100 return (status < 0) ? status : 0;
101}
102
103static int i2c_read_le16(struct i2c_client *client)
104{
105 u8 buf[2];
106 int status;
107
108 status = i2c_master_recv(client, buf, 2);
109 if (status < 0)
110 return status;
111 return (buf[1] << 8) | buf[0];
112}
113
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KM
114/*-------------------------------------------------------------------------*/
115
116static int pcf857x_input(struct gpio_chip *chip, unsigned offset)
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DB
117{
118 struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
1673ad52 119 int status;
15fae37d 120
1673ad52 121 mutex_lock(&gpio->lock);
15fae37d 122 gpio->out |= (1 << offset);
0c65ddd4 123 status = gpio->write(gpio->client, gpio->out);
1673ad52
DB
124 mutex_unlock(&gpio->lock);
125
126 return status;
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DB
127}
128
0c65ddd4 129static int pcf857x_get(struct gpio_chip *chip, unsigned offset)
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130{
131 struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
132 int value;
133
0c65ddd4 134 value = gpio->read(gpio->client);
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DB
135 return (value < 0) ? 0 : (value & (1 << offset));
136}
137
0c65ddd4 138static int pcf857x_output(struct gpio_chip *chip, unsigned offset, int value)
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DB
139{
140 struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
141 unsigned bit = 1 << offset;
1673ad52 142 int status;
15fae37d 143
1673ad52 144 mutex_lock(&gpio->lock);
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DB
145 if (value)
146 gpio->out |= bit;
147 else
148 gpio->out &= ~bit;
0c65ddd4 149 status = gpio->write(gpio->client, gpio->out);
1673ad52
DB
150 mutex_unlock(&gpio->lock);
151
152 return status;
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153}
154
0c65ddd4 155static void pcf857x_set(struct gpio_chip *chip, unsigned offset, int value)
15fae37d 156{
0c65ddd4 157 pcf857x_output(chip, offset, value);
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158}
159
160/*-------------------------------------------------------------------------*/
161
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162static int pcf857x_to_irq(struct gpio_chip *chip, unsigned offset)
163{
164 struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
21fd3cd1 165 int ret;
6e20a0a4 166
21fd3cd1
GC
167 ret = irq_create_mapping(gpio->irq_domain, offset);
168 if (ret > 0)
169 gpio->irq_mapped |= (1 << offset);
170
171 return ret;
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KM
172}
173
5c21d008
GC
174static irqreturn_t pcf857x_irq(int irq, void *data)
175{
176 struct pcf857x *gpio = data;
177 unsigned long change, i, status, flags;
178
179 status = gpio->read(gpio->client);
180
181 spin_lock_irqsave(&gpio->slock, flags);
182
21fd3cd1
GC
183 /*
184 * call the interrupt handler iff gpio is used as
185 * interrupt source, just to avoid bad irqs
186 */
187
188 change = ((gpio->status ^ status) & gpio->irq_mapped);
5c21d008
GC
189 for_each_set_bit(i, &change, gpio->chip.ngpio)
190 generic_handle_irq(irq_find_mapping(gpio->irq_domain, i));
191 gpio->status = status;
192
193 spin_unlock_irqrestore(&gpio->slock, flags);
194
195 return IRQ_HANDLED;
196}
197
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KM
198static int pcf857x_irq_domain_map(struct irq_domain *domain, unsigned int virq,
199 irq_hw_number_t hw)
200{
21fd3cd1
GC
201 struct pcf857x *gpio = domain->host_data;
202
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KM
203 irq_set_chip_and_handler(virq,
204 &dummy_irq_chip,
205 handle_level_irq);
21fd3cd1
GC
206 set_irq_flags(virq, IRQF_VALID);
207 gpio->irq_mapped |= (1 << hw);
208
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KM
209 return 0;
210}
211
212static struct irq_domain_ops pcf857x_irq_domain_ops = {
213 .map = pcf857x_irq_domain_map,
214};
215
216static void pcf857x_irq_domain_cleanup(struct pcf857x *gpio)
217{
218 if (gpio->irq_domain)
219 irq_domain_remove(gpio->irq_domain);
220
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KM
221}
222
223static int pcf857x_irq_domain_init(struct pcf857x *gpio,
805f864e 224 struct i2c_client *client)
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225{
226 int status;
227
805f864e 228 gpio->irq_domain = irq_domain_add_linear(client->dev.of_node,
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229 gpio->chip.ngpio,
230 &pcf857x_irq_domain_ops,
21fd3cd1 231 gpio);
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232 if (!gpio->irq_domain)
233 goto fail;
234
235 /* enable real irq */
5c21d008
GC
236 status = devm_request_threaded_irq(&client->dev, client->irq,
237 NULL, pcf857x_irq, IRQF_ONESHOT |
238 IRQF_TRIGGER_FALLING,
239 dev_name(&client->dev), gpio);
240
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KM
241 if (status)
242 goto fail;
243
244 /* enable gpio_to_irq() */
6e20a0a4 245 gpio->chip.to_irq = pcf857x_to_irq;
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KM
246
247 return 0;
248
249fail:
250 pcf857x_irq_domain_cleanup(gpio);
251 return -EINVAL;
252}
253
254/*-------------------------------------------------------------------------*/
255
d2653e92
JD
256static int pcf857x_probe(struct i2c_client *client,
257 const struct i2c_device_id *id)
15fae37d
DB
258{
259 struct pcf857x_platform_data *pdata;
260 struct pcf857x *gpio;
261 int status;
262
e56aee18 263 pdata = dev_get_platdata(&client->dev);
a342d215
BD
264 if (!pdata) {
265 dev_dbg(&client->dev, "no platform data\n");
a342d215 266 }
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267
268 /* Allocate, initialize, and register this gpio_chip. */
f39f54af 269 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL);
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DB
270 if (!gpio)
271 return -ENOMEM;
272
1673ad52 273 mutex_init(&gpio->lock);
6e20a0a4 274 spin_lock_init(&gpio->slock);
1673ad52 275
0c65ddd4
KM
276 gpio->chip.base = pdata ? pdata->gpio_base : -1;
277 gpio->chip.can_sleep = 1;
278 gpio->chip.dev = &client->dev;
279 gpio->chip.owner = THIS_MODULE;
280 gpio->chip.get = pcf857x_get;
281 gpio->chip.set = pcf857x_set;
282 gpio->chip.direction_input = pcf857x_input;
283 gpio->chip.direction_output = pcf857x_output;
284 gpio->chip.ngpio = id->driver_data;
15fae37d 285
6e20a0a4 286 /* enable gpio_to_irq() if platform has settings */
655c4e79
LP
287 if (client->irq) {
288 status = pcf857x_irq_domain_init(gpio, client);
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KM
289 if (status < 0) {
290 dev_err(&client->dev, "irq_domain init failed\n");
291 goto fail;
292 }
293 }
294
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DB
295 /* NOTE: the OnSemi jlc1562b is also largely compatible with
296 * these parts, notably for output. It has a low-resolution
297 * DAC instead of pin change IRQs; and its inputs can be the
298 * result of comparators.
299 */
300
301 /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f;
302 * 9670, 9672, 9764, and 9764a use quite a variety.
303 *
304 * NOTE: we don't distinguish here between *4 and *4a parts.
305 */
3760f736 306 if (gpio->chip.ngpio == 8) {
0c65ddd4
KM
307 gpio->write = i2c_write_le8;
308 gpio->read = i2c_read_le8;
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DB
309
310 if (!i2c_check_functionality(client->adapter,
311 I2C_FUNC_SMBUS_BYTE))
312 status = -EIO;
313
314 /* fail if there's no chip present */
315 else
316 status = i2c_smbus_read_byte(client);
317
318 /* '75/'75c addresses are 0x20..0x27, just like the '74;
319 * the '75c doesn't have a current source pulling high.
320 * 9671, 9673, and 9765 use quite a variety of addresses.
321 *
322 * NOTE: we don't distinguish here between '75 and '75c parts.
323 */
3760f736 324 } else if (gpio->chip.ngpio == 16) {
0c65ddd4
KM
325 gpio->write = i2c_write_le16;
326 gpio->read = i2c_read_le16;
15fae37d
DB
327
328 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
329 status = -EIO;
330
331 /* fail if there's no chip present */
332 else
333 status = i2c_read_le16(client);
334
a342d215
BD
335 } else {
336 dev_dbg(&client->dev, "unsupported number of gpios\n");
337 status = -EINVAL;
338 }
15fae37d
DB
339
340 if (status < 0)
341 goto fail;
342
343 gpio->chip.label = client->name;
344
345 gpio->client = client;
346 i2c_set_clientdata(client, gpio);
347
348 /* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
349 * We can't actually know whether a pin is configured (a) as output
350 * and driving the signal low, or (b) as input and reporting a low
351 * value ... without knowing the last value written since the chip
352 * came out of reset (if any). We can't read the latched output.
353 *
354 * In short, the only reliable solution for setting up pin direction
355 * is to do it explicitly. The setup() method can do that, but it
356 * may cause transient glitching since it can't know the last value
357 * written (some pins may need to be driven low).
358 *
359 * Using pdata->n_latch avoids that trouble. When left initialized
360 * to zero, our software copy of the "latch" then matches the chip's
361 * all-ones reset state. Otherwise it flags pins to be driven low.
362 */
49946f68 363 gpio->out = pdata ? ~pdata->n_latch : ~0;
6e20a0a4 364 gpio->status = gpio->out;
15fae37d
DB
365
366 status = gpiochip_add(&gpio->chip);
367 if (status < 0)
368 goto fail;
369
15fae37d
DB
370 /* Let platform code set up the GPIOs and their users.
371 * Now is the first time anyone could use them.
372 */
49946f68 373 if (pdata && pdata->setup) {
15fae37d
DB
374 status = pdata->setup(client,
375 gpio->chip.base, gpio->chip.ngpio,
376 pdata->context);
377 if (status < 0)
378 dev_warn(&client->dev, "setup --> %d\n", status);
379 }
380
805f864e
KM
381 dev_info(&client->dev, "probed\n");
382
15fae37d
DB
383 return 0;
384
385fail:
386 dev_dbg(&client->dev, "probe error %d for '%s'\n",
387 status, client->name);
6e20a0a4 388
655c4e79 389 if (client->irq)
6e20a0a4
KM
390 pcf857x_irq_domain_cleanup(gpio);
391
15fae37d
DB
392 return status;
393}
394
395static int pcf857x_remove(struct i2c_client *client)
396{
e56aee18 397 struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
15fae37d
DB
398 struct pcf857x *gpio = i2c_get_clientdata(client);
399 int status = 0;
400
49946f68 401 if (pdata && pdata->teardown) {
15fae37d
DB
402 status = pdata->teardown(client,
403 gpio->chip.base, gpio->chip.ngpio,
404 pdata->context);
405 if (status < 0) {
406 dev_err(&client->dev, "%s --> %d\n",
407 "teardown", status);
408 return status;
409 }
410 }
411
655c4e79 412 if (client->irq)
6e20a0a4
KM
413 pcf857x_irq_domain_cleanup(gpio);
414
15fae37d 415 status = gpiochip_remove(&gpio->chip);
f39f54af 416 if (status)
15fae37d
DB
417 dev_err(&client->dev, "%s --> %d\n", "remove", status);
418 return status;
419}
420
421static struct i2c_driver pcf857x_driver = {
422 .driver = {
423 .name = "pcf857x",
424 .owner = THIS_MODULE,
425 },
426 .probe = pcf857x_probe,
427 .remove = pcf857x_remove,
3760f736 428 .id_table = pcf857x_id,
15fae37d
DB
429};
430
431static int __init pcf857x_init(void)
432{
433 return i2c_add_driver(&pcf857x_driver);
434}
2f8d1197
DB
435/* register after i2c postcore initcall and before
436 * subsys initcalls that may rely on these GPIOs
437 */
438subsys_initcall(pcf857x_init);
15fae37d
DB
439
440static void __exit pcf857x_exit(void)
441{
442 i2c_del_driver(&pcf857x_driver);
443}
444module_exit(pcf857x_exit);
445
446MODULE_LICENSE("GPL");
447MODULE_AUTHOR("David Brownell");