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15fae37d 1/*
c103de24 2 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
15fae37d
DB
3 *
4 * Copyright (C) 2007 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
d120c17f 21#include <linux/gpio.h>
15fae37d
DB
22#include <linux/i2c.h>
23#include <linux/i2c/pcf857x.h>
6e20a0a4
KM
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/irqdomain.h>
c990d6cb 27#include <linux/kernel.h>
bb207ef1 28#include <linux/module.h>
63f57cd4
LP
29#include <linux/of.h>
30#include <linux/of_device.h>
c990d6cb 31#include <linux/slab.h>
6e20a0a4 32#include <linux/spinlock.h>
15fae37d 33
15fae37d 34
3760f736
JD
35static const struct i2c_device_id pcf857x_id[] = {
36 { "pcf8574", 8 },
4ba2ccb8 37 { "pcf8574a", 8 },
3760f736
JD
38 { "pca8574", 8 },
39 { "pca9670", 8 },
40 { "pca9672", 8 },
41 { "pca9674", 8 },
42 { "pcf8575", 16 },
43 { "pca8575", 16 },
44 { "pca9671", 16 },
45 { "pca9673", 16 },
46 { "pca9675", 16 },
1673ad52
DB
47 { "max7328", 8 },
48 { "max7329", 8 },
02130490 49 { "tca9554", 8 },
3760f736
JD
50 { }
51};
52MODULE_DEVICE_TABLE(i2c, pcf857x_id);
53
63f57cd4
LP
54#ifdef CONFIG_OF
55static const struct of_device_id pcf857x_of_table[] = {
56 { .compatible = "nxp,pcf8574" },
57 { .compatible = "nxp,pcf8574a" },
58 { .compatible = "nxp,pca8574" },
59 { .compatible = "nxp,pca9670" },
60 { .compatible = "nxp,pca9672" },
61 { .compatible = "nxp,pca9674" },
62 { .compatible = "nxp,pcf8575" },
63 { .compatible = "nxp,pca8575" },
64 { .compatible = "nxp,pca9671" },
65 { .compatible = "nxp,pca9673" },
66 { .compatible = "nxp,pca9675" },
67 { .compatible = "maxim,max7328" },
68 { .compatible = "maxim,max7329" },
69 { .compatible = "ti,tca9554" },
70 { }
71};
72MODULE_DEVICE_TABLE(of, pcf857x_of_table);
73#endif
74
15fae37d
DB
75/*
76 * The pcf857x, pca857x, and pca967x chips only expose one read and one
77 * write register. Writing a "one" bit (to match the reset state) lets
78 * that pin be used as an input; it's not an open-drain model, but acts
79 * a bit like one. This is described as "quasi-bidirectional"; read the
80 * chip documentation for details.
81 *
82 * Many other I2C GPIO expander chips (like the pca953x models) have
83 * more complex register models and more conventional circuitry using
84 * push/pull drivers. They often use the same 0x20..0x27 addresses as
85 * pcf857x parts, making the "legacy" I2C driver model problematic.
86 */
87struct pcf857x {
88 struct gpio_chip chip;
89 struct i2c_client *client;
1673ad52 90 struct mutex lock; /* protect 'out' */
6e20a0a4 91 spinlock_t slock; /* protect irq demux */
15fae37d 92 unsigned out; /* software latch */
6e20a0a4 93 unsigned status; /* current status */
ffb8e44b 94 unsigned int irq_parent;
0c65ddd4
KM
95
96 int (*write)(struct i2c_client *client, unsigned data);
97 int (*read)(struct i2c_client *client);
15fae37d
DB
98};
99
100/*-------------------------------------------------------------------------*/
101
102/* Talk to 8-bit I/O expander */
103
0c65ddd4 104static int i2c_write_le8(struct i2c_client *client, unsigned data)
15fae37d 105{
0c65ddd4 106 return i2c_smbus_write_byte(client, data);
15fae37d
DB
107}
108
0c65ddd4 109static int i2c_read_le8(struct i2c_client *client)
15fae37d 110{
0c65ddd4 111 return (int)i2c_smbus_read_byte(client);
15fae37d
DB
112}
113
15fae37d
DB
114/* Talk to 16-bit I/O expander */
115
0c65ddd4 116static int i2c_write_le16(struct i2c_client *client, unsigned word)
15fae37d
DB
117{
118 u8 buf[2] = { word & 0xff, word >> 8, };
119 int status;
120
121 status = i2c_master_send(client, buf, 2);
122 return (status < 0) ? status : 0;
123}
124
125static int i2c_read_le16(struct i2c_client *client)
126{
127 u8 buf[2];
128 int status;
129
130 status = i2c_master_recv(client, buf, 2);
131 if (status < 0)
132 return status;
133 return (buf[1] << 8) | buf[0];
134}
135
0c65ddd4
KM
136/*-------------------------------------------------------------------------*/
137
138static int pcf857x_input(struct gpio_chip *chip, unsigned offset)
15fae37d
DB
139{
140 struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
1673ad52 141 int status;
15fae37d 142
1673ad52 143 mutex_lock(&gpio->lock);
15fae37d 144 gpio->out |= (1 << offset);
0c65ddd4 145 status = gpio->write(gpio->client, gpio->out);
1673ad52
DB
146 mutex_unlock(&gpio->lock);
147
148 return status;
15fae37d
DB
149}
150
0c65ddd4 151static int pcf857x_get(struct gpio_chip *chip, unsigned offset)
15fae37d
DB
152{
153 struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
154 int value;
155
0c65ddd4 156 value = gpio->read(gpio->client);
15fae37d
DB
157 return (value < 0) ? 0 : (value & (1 << offset));
158}
159
0c65ddd4 160static int pcf857x_output(struct gpio_chip *chip, unsigned offset, int value)
15fae37d
DB
161{
162 struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
163 unsigned bit = 1 << offset;
1673ad52 164 int status;
15fae37d 165
1673ad52 166 mutex_lock(&gpio->lock);
15fae37d
DB
167 if (value)
168 gpio->out |= bit;
169 else
170 gpio->out &= ~bit;
0c65ddd4 171 status = gpio->write(gpio->client, gpio->out);
1673ad52
DB
172 mutex_unlock(&gpio->lock);
173
174 return status;
15fae37d
DB
175}
176
0c65ddd4 177static void pcf857x_set(struct gpio_chip *chip, unsigned offset, int value)
15fae37d 178{
0c65ddd4 179 pcf857x_output(chip, offset, value);
15fae37d
DB
180}
181
182/*-------------------------------------------------------------------------*/
183
5c21d008
GC
184static irqreturn_t pcf857x_irq(int irq, void *data)
185{
186 struct pcf857x *gpio = data;
187 unsigned long change, i, status, flags;
188
189 status = gpio->read(gpio->client);
190
191 spin_lock_irqsave(&gpio->slock, flags);
192
21fd3cd1
GC
193 /*
194 * call the interrupt handler iff gpio is used as
195 * interrupt source, just to avoid bad irqs
196 */
197
a39294bd 198 change = (gpio->status ^ status);
5c21d008 199 for_each_set_bit(i, &change, gpio->chip.ngpio)
a39294bd 200 handle_nested_irq(irq_find_mapping(gpio->chip.irqdomain, i));
5c21d008
GC
201 gpio->status = status;
202
203 spin_unlock_irqrestore(&gpio->slock, flags);
204
205 return IRQ_HANDLED;
206}
207
b80eef95
GU
208/*
209 * NOP functions
210 */
211static void noop(struct irq_data *data) { }
212
213static unsigned int noop_ret(struct irq_data *data)
214{
215 return 0;
216}
217
218static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on)
219{
220 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
ffb8e44b
GU
221 int error = 0;
222
223 if (gpio->irq_parent) {
224 error = irq_set_irq_wake(gpio->irq_parent, on);
225 if (error) {
226 dev_dbg(&gpio->client->dev,
227 "irq %u doesn't support irq_set_wake\n",
228 gpio->irq_parent);
229 gpio->irq_parent = 0;
230 }
231 }
b80eef95 232
ffb8e44b 233 return error;
b80eef95
GU
234}
235
236static struct irq_chip pcf857x_irq_chip = {
237 .name = "pcf857x",
238 .irq_startup = noop_ret,
239 .irq_shutdown = noop,
240 .irq_enable = noop,
241 .irq_disable = noop,
242 .irq_ack = noop,
243 .irq_mask = noop,
244 .irq_unmask = noop,
245 .irq_set_wake = pcf857x_irq_set_wake,
246};
247
6e20a0a4
KM
248/*-------------------------------------------------------------------------*/
249
d2653e92
JD
250static int pcf857x_probe(struct i2c_client *client,
251 const struct i2c_device_id *id)
15fae37d 252{
63f57cd4
LP
253 struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
254 struct device_node *np = client->dev.of_node;
15fae37d 255 struct pcf857x *gpio;
63f57cd4 256 unsigned int n_latch = 0;
15fae37d
DB
257 int status;
258
63f57cd4
LP
259 if (IS_ENABLED(CONFIG_OF) && np)
260 of_property_read_u32(np, "lines-initial-states", &n_latch);
261 else if (pdata)
262 n_latch = pdata->n_latch;
263 else
a342d215 264 dev_dbg(&client->dev, "no platform data\n");
15fae37d
DB
265
266 /* Allocate, initialize, and register this gpio_chip. */
f39f54af 267 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL);
15fae37d
DB
268 if (!gpio)
269 return -ENOMEM;
270
1673ad52 271 mutex_init(&gpio->lock);
6e20a0a4 272 spin_lock_init(&gpio->slock);
1673ad52 273
0c65ddd4 274 gpio->chip.base = pdata ? pdata->gpio_base : -1;
9fb1f39e 275 gpio->chip.can_sleep = true;
0c65ddd4
KM
276 gpio->chip.dev = &client->dev;
277 gpio->chip.owner = THIS_MODULE;
278 gpio->chip.get = pcf857x_get;
279 gpio->chip.set = pcf857x_set;
280 gpio->chip.direction_input = pcf857x_input;
281 gpio->chip.direction_output = pcf857x_output;
282 gpio->chip.ngpio = id->driver_data;
15fae37d
DB
283
284 /* NOTE: the OnSemi jlc1562b is also largely compatible with
285 * these parts, notably for output. It has a low-resolution
286 * DAC instead of pin change IRQs; and its inputs can be the
287 * result of comparators.
288 */
289
290 /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f;
291 * 9670, 9672, 9764, and 9764a use quite a variety.
292 *
293 * NOTE: we don't distinguish here between *4 and *4a parts.
294 */
3760f736 295 if (gpio->chip.ngpio == 8) {
0c65ddd4
KM
296 gpio->write = i2c_write_le8;
297 gpio->read = i2c_read_le8;
15fae37d
DB
298
299 if (!i2c_check_functionality(client->adapter,
300 I2C_FUNC_SMBUS_BYTE))
301 status = -EIO;
302
303 /* fail if there's no chip present */
304 else
305 status = i2c_smbus_read_byte(client);
306
307 /* '75/'75c addresses are 0x20..0x27, just like the '74;
308 * the '75c doesn't have a current source pulling high.
309 * 9671, 9673, and 9765 use quite a variety of addresses.
310 *
311 * NOTE: we don't distinguish here between '75 and '75c parts.
312 */
3760f736 313 } else if (gpio->chip.ngpio == 16) {
0c65ddd4
KM
314 gpio->write = i2c_write_le16;
315 gpio->read = i2c_read_le16;
15fae37d
DB
316
317 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
318 status = -EIO;
319
320 /* fail if there's no chip present */
321 else
322 status = i2c_read_le16(client);
323
a342d215
BD
324 } else {
325 dev_dbg(&client->dev, "unsupported number of gpios\n");
326 status = -EINVAL;
327 }
15fae37d
DB
328
329 if (status < 0)
330 goto fail;
331
332 gpio->chip.label = client->name;
333
334 gpio->client = client;
335 i2c_set_clientdata(client, gpio);
336
337 /* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
338 * We can't actually know whether a pin is configured (a) as output
339 * and driving the signal low, or (b) as input and reporting a low
340 * value ... without knowing the last value written since the chip
341 * came out of reset (if any). We can't read the latched output.
342 *
343 * In short, the only reliable solution for setting up pin direction
344 * is to do it explicitly. The setup() method can do that, but it
345 * may cause transient glitching since it can't know the last value
346 * written (some pins may need to be driven low).
347 *
63f57cd4
LP
348 * Using n_latch avoids that trouble. When left initialized to zero,
349 * our software copy of the "latch" then matches the chip's all-ones
350 * reset state. Otherwise it flags pins to be driven low.
15fae37d 351 */
63f57cd4 352 gpio->out = ~n_latch;
6e20a0a4 353 gpio->status = gpio->out;
15fae37d
DB
354
355 status = gpiochip_add(&gpio->chip);
356 if (status < 0)
357 goto fail;
358
a39294bd
GU
359 /* Enable irqchip if we have an interrupt */
360 if (client->irq) {
b80eef95
GU
361 status = gpiochip_irqchip_add(&gpio->chip, &pcf857x_irq_chip,
362 0, handle_level_irq,
363 IRQ_TYPE_NONE);
a39294bd
GU
364 if (status) {
365 dev_err(&client->dev, "cannot add irqchip\n");
366 goto fail_irq;
367 }
368
369 status = devm_request_threaded_irq(&client->dev, client->irq,
370 NULL, pcf857x_irq, IRQF_ONESHOT |
371 IRQF_TRIGGER_FALLING | IRQF_SHARED,
372 dev_name(&client->dev), gpio);
373 if (status)
374 goto fail_irq;
375
b80eef95 376 gpiochip_set_chained_irqchip(&gpio->chip, &pcf857x_irq_chip,
a39294bd 377 client->irq, NULL);
ffb8e44b 378 gpio->irq_parent = client->irq;
a39294bd
GU
379 }
380
15fae37d
DB
381 /* Let platform code set up the GPIOs and their users.
382 * Now is the first time anyone could use them.
383 */
49946f68 384 if (pdata && pdata->setup) {
15fae37d
DB
385 status = pdata->setup(client,
386 gpio->chip.base, gpio->chip.ngpio,
387 pdata->context);
388 if (status < 0)
389 dev_warn(&client->dev, "setup --> %d\n", status);
390 }
391
805f864e
KM
392 dev_info(&client->dev, "probed\n");
393
15fae37d
DB
394 return 0;
395
a39294bd
GU
396fail_irq:
397 gpiochip_remove(&gpio->chip);
6e20a0a4 398
a39294bd
GU
399fail:
400 dev_dbg(&client->dev, "probe error %d for '%s'\n", status,
401 client->name);
e6b698f6 402
15fae37d
DB
403 return status;
404}
405
406static int pcf857x_remove(struct i2c_client *client)
407{
e56aee18 408 struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
15fae37d
DB
409 struct pcf857x *gpio = i2c_get_clientdata(client);
410 int status = 0;
411
49946f68 412 if (pdata && pdata->teardown) {
15fae37d
DB
413 status = pdata->teardown(client,
414 gpio->chip.base, gpio->chip.ngpio,
415 pdata->context);
416 if (status < 0) {
417 dev_err(&client->dev, "%s --> %d\n",
418 "teardown", status);
419 return status;
420 }
421 }
422
9f5132ae 423 gpiochip_remove(&gpio->chip);
15fae37d
DB
424 return status;
425}
426
427static struct i2c_driver pcf857x_driver = {
428 .driver = {
429 .name = "pcf857x",
430 .owner = THIS_MODULE,
63f57cd4 431 .of_match_table = of_match_ptr(pcf857x_of_table),
15fae37d
DB
432 },
433 .probe = pcf857x_probe,
434 .remove = pcf857x_remove,
3760f736 435 .id_table = pcf857x_id,
15fae37d
DB
436};
437
438static int __init pcf857x_init(void)
439{
440 return i2c_add_driver(&pcf857x_driver);
441}
2f8d1197
DB
442/* register after i2c postcore initcall and before
443 * subsys initcalls that may rely on these GPIOs
444 */
445subsys_initcall(pcf857x_init);
15fae37d
DB
446
447static void __exit pcf857x_exit(void)
448{
449 i2c_del_driver(&pcf857x_driver);
450}
451module_exit(pcf857x_exit);
452
453MODULE_LICENSE("GPL");
454MODULE_AUTHOR("David Brownell");