[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-pl061.c

/*
 * Copyright (C) 2008, 2009 Provigent Ltd.
 *
 * Author: Baruch Siach <baruch@tkos.co.il>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
 *
 * Data sheet: ARM DDI 0190B, September 2000
 */
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#define GPIODIR 0x400
#define GPIOIS  0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE  0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC  0x41C

#define PL061_GPIO_NR	8

#ifdef CONFIG_PM
struct pl061_context_save_regs {
	u8 gpio_data;
	u8 gpio_dir;
	u8 gpio_is;
	u8 gpio_ibe;
	u8 gpio_iev;
	u8 gpio_ie;
};
#endif

struct pl061 {
	raw_spinlock_t		lock;

	void __iomem		*base;
	struct gpio_chip	gc;
	int			parent_irq;

#ifdef CONFIG_PM
	struct pl061_context_save_regs csave_regs;
#endif
};

static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return !(readb(pl061->base + GPIODIR) & BIT(offset));
}

static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	raw_spin_lock_irqsave(&pl061->lock, flags);
	gpiodir = readb(pl061->base + GPIODIR);
	gpiodir &= ~(BIT(offset));
	writeb(gpiodir, pl061->base + GPIODIR);
	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	raw_spin_lock_irqsave(&pl061->lock, flags);
	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
	gpiodir = readb(pl061->base + GPIODIR);
	gpiodir |= BIT(offset);
	writeb(gpiodir, pl061->base + GPIODIR);

	/*
	 * gpio value is set again, because pl061 doesn't allow to set value of
	 * a gpio pin before configuring it in OUT mode.
	 */
	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return !!readb(pl061->base + (BIT(offset + 2)));
}

static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
}

static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u8 gpiois, gpioibe, gpioiev;
	u8 bit = BIT(offset);

	if (offset < 0 || offset >= PL061_GPIO_NR)
		return -EINVAL;

	if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
	    (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
	{
		dev_err(gc->parent,
			"trying to configure line %d for both level and edge "
			"detection, choose one!\n",
			offset);
		return -EINVAL;
	}


	raw_spin_lock_irqsave(&pl061->lock, flags);

	gpioiev = readb(pl061->base + GPIOIEV);
	gpiois = readb(pl061->base + GPIOIS);
	gpioibe = readb(pl061->base + GPIOIBE);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;

		/* Disable edge detection */
		gpioibe &= ~bit;
		/* Enable level detection */
		gpiois |= bit;
		/* Select polarity */
		if (polarity)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_level_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
			offset,
			polarity ? "HIGH" : "LOW");
	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		/* Disable level detection */
		gpiois &= ~bit;
		/* Select both edges, setting this makes GPIOEV be ignored */
		gpioibe |= bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
	} else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
		   (trigger & IRQ_TYPE_EDGE_FALLING)) {
		bool rising = trigger & IRQ_TYPE_EDGE_RISING;

		/* Disable level detection */
		gpiois &= ~bit;
		/* Clear detection on both edges */
		gpioibe &= ~bit;
		/* Select edge */
		if (rising)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
			offset,
			rising ? "RISING" : "FALLING");
	} else {
		/* No trigger: disable everything */
		gpiois &= ~bit;
		gpioibe &= ~bit;
		gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_bad_irq);
		dev_warn(gc->parent, "no trigger selected for line %d\n",
			 offset);
	}

	writeb(gpiois, pl061->base + GPIOIS);
	writeb(gpioibe, pl061->base + GPIOIBE);
	writeb(gpioiev, pl061->base + GPIOIEV);

	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static void pl061_irq_handler(struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readb(pl061->base + GPIOMIS);
	if (pending) {
		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
			generic_handle_irq(irq_find_mapping(gc->irqdomain,
							    offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void pl061_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	raw_spin_lock(&pl061->lock);
	gpioie = readb(pl061->base + GPIOIE) & ~mask;
	writeb(gpioie, pl061->base + GPIOIE);
	raw_spin_unlock(&pl061->lock);
}

static void pl061_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	raw_spin_lock(&pl061->lock);
	gpioie = readb(pl061->base + GPIOIE) | mask;
	writeb(gpioie, pl061->base + GPIOIE);
	raw_spin_unlock(&pl061->lock);
}

/**
 * pl061_irq_ack() - ACK an edge IRQ
 * @d: IRQ data for this IRQ
 *
 * This gets called from the edge IRQ handler to ACK the edge IRQ
 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
 * not needed: these go away when the level signal goes away.
 */
static void pl061_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);

	raw_spin_lock(&pl061->lock);
	writeb(mask, pl061->base + GPIOIC);
	raw_spin_unlock(&pl061->lock);
}

static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return irq_set_irq_wake(pl061->parent_irq, state);
}

static struct irq_chip pl061_irqchip = {
	.name		= "pl061",
	.irq_ack	= pl061_irq_ack,
	.irq_mask	= pl061_irq_mask,
	.irq_unmask	= pl061_irq_unmask,
	.irq_set_type	= pl061_irq_type,
	.irq_set_wake	= pl061_irq_set_wake,
};

static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
	struct device *dev = &adev->dev;
	struct pl061 *pl061;
	int ret, irq;

	pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
	if (pl061 == NULL)
		return -ENOMEM;

	pl061->base = devm_ioremap_resource(dev, &adev->res);
	if (IS_ERR(pl061->base))
		return PTR_ERR(pl061->base);

	raw_spin_lock_init(&pl061->lock);
	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
		pl061->gc.request = gpiochip_generic_request;
		pl061->gc.free = gpiochip_generic_free;
	}

	pl061->gc.base = -1;
	pl061->gc.get_direction = pl061_get_direction;
	pl061->gc.direction_input = pl061_direction_input;
	pl061->gc.direction_output = pl061_direction_output;
	pl061->gc.get = pl061_get_value;
	pl061->gc.set = pl061_set_value;
	pl061->gc.ngpio = PL061_GPIO_NR;
	pl061->gc.label = dev_name(dev);
	pl061->gc.parent = dev;
	pl061->gc.owner = THIS_MODULE;

	ret = gpiochip_add_data(&pl061->gc, pl061);
	if (ret)
		return ret;

	/*
	 * irq_chip support
	 */
	writeb(0, pl061->base + GPIOIE); /* disable irqs */
	irq = adev->irq[0];
	if (irq < 0) {
		dev_err(&adev->dev, "invalid IRQ\n");
		return -ENODEV;
	}
	pl061->parent_irq = irq;

	ret = gpiochip_irqchip_add(&pl061->gc, &pl061_irqchip,
				   0, handle_bad_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_info(&adev->dev, "could not add irqchip\n");
		return ret;
	}
	gpiochip_set_chained_irqchip(&pl061->gc, &pl061_irqchip,
				     irq, pl061_irq_handler);

	amba_set_drvdata(adev, pl061);
	dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
		 &adev->res.start);

	return 0;
}

#ifdef CONFIG_PM
static int pl061_suspend(struct device *dev)
{
	struct pl061 *pl061 = dev_get_drvdata(dev);
	int offset;

	pl061->csave_regs.gpio_data = 0;
	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
			pl061->csave_regs.gpio_data |=
				pl061_get_value(&pl061->gc, offset) << offset;
	}

	return 0;
}

static int pl061_resume(struct device *dev)
{
	struct pl061 *pl061 = dev_get_drvdata(dev);
	int offset;

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
			pl061_direction_output(&pl061->gc, offset,
					pl061->csave_regs.gpio_data &
					(BIT(offset)));
		else
			pl061_direction_input(&pl061->gc, offset);
	}

	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);

	return 0;
}

static const struct dev_pm_ops pl061_dev_pm_ops = {
	.suspend = pl061_suspend,
	.resume = pl061_resume,
	.freeze = pl061_suspend,
	.restore = pl061_resume,
};
#endif

static struct amba_id pl061_ids[] = {
	{
		.id	= 0x00041061,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

static struct amba_driver pl061_gpio_driver = {
	.drv = {
		.name	= "pl061_gpio",
#ifdef CONFIG_PM
		.pm	= &pl061_dev_pm_ops,
#endif
	},
	.id_table	= pl061_ids,
	.probe		= pl061_probe,
};

static int __init pl061_gpio_init(void)
{
	return amba_driver_register(&pl061_gpio_driver);
}
device_initcall(pl061_gpio_init);
Commit	Line	Data
1e9c2859	1	/*
c103de24	2	* Copyright (C) 2008, 2009 Provigent Ltd.
1e9c2859	3	*
ef3e7100 PG	4	* Author: Baruch Siach <baruch@tkos.co.il>
ef3e7100 PG	5	*
1e9c2859 BS	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
	11	*
	12	* Data sheet: ARM DDI 0190B, September 2000
	13	*/
	14	#include <linux/spinlock.h>
	15	#include <linux/errno.h>
ef3e7100	16	#include <linux/init.h>
1e9c2859 BS	17	#include <linux/io.h>
1e9c2859 BS	18	#include <linux/ioport.h>
2f46205b	19	#include <linux/interrupt.h>
1e9c2859	20	#include <linux/irq.h>
de88cbb7	21	#include <linux/irqchip/chained_irq.h>
1e9c2859	22	#include <linux/bitops.h>
1e9c2859 BS	23	#include <linux/gpio.h>
	24	#include <linux/device.h>
	25	#include <linux/amba/bus.h>
5a0e3ad6	26	#include <linux/slab.h>
39b70ee0	27	#include <linux/pinctrl/consumer.h>
e198a8de	28	#include <linux/pm.h>
1e9c2859 BS	29
	30	#define GPIODIR 0x400
	31	#define GPIOIS 0x404
	32	#define GPIOIBE 0x408
	33	#define GPIOIEV 0x40C
	34	#define GPIOIE 0x410
	35	#define GPIORIS 0x414
	36	#define GPIOMIS 0x418
	37	#define GPIOIC 0x41C
	38
	39	#define PL061_GPIO_NR 8
	40
e198a8de DS	41	#ifdef CONFIG_PM
	42	struct pl061_context_save_regs {
	43	u8 gpio_data;
	44	u8 gpio_dir;
	45	u8 gpio_is;
	46	u8 gpio_ibe;
	47	u8 gpio_iev;
	48	u8 gpio_ie;
	49	};
	50	#endif
1e9c2859	51
538f76c5	52	struct pl061 {
99b9b45d	53	raw_spinlock_t lock;
1e9c2859 BS	54
1e9c2859 BS	55	void __iomem *base;
1e9c2859	56	struct gpio_chip gc;
9c18be8e	57	int parent_irq;
e198a8de DS	58
	59	#ifdef CONFIG_PM
	60	struct pl061_context_save_regs csave_regs;
	61	#endif
1e9c2859 BS	62	};
1e9c2859 BS	63
3484f1be LW	64	static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
3484f1be LW	65	{
2796325f	66	struct pl061 *pl061 = gpiochip_get_data(gc);
3484f1be	67
2796325f	68	return !(readb(pl061->base + GPIODIR) & BIT(offset));
3484f1be LW	69	}
3484f1be LW	70
1e9c2859 BS	71	static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
1e9c2859 BS	72	{
2796325f	73	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859 BS	74	unsigned long flags;
	75	unsigned char gpiodir;
	76
99b9b45d	77	raw_spin_lock_irqsave(&pl061->lock, flags);
2796325f	78	gpiodir = readb(pl061->base + GPIODIR);
bea41504	79	gpiodir &= ~(BIT(offset));
2796325f	80	writeb(gpiodir, pl061->base + GPIODIR);
99b9b45d	81	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	82
	83	return 0;
	84	}
	85
	86	static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
	87	int value)
	88	{
2796325f	89	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859 BS	90	unsigned long flags;
	91	unsigned char gpiodir;
	92
99b9b45d	93	raw_spin_lock_irqsave(&pl061->lock, flags);
2796325f LW	94	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
2796325f LW	95	gpiodir = readb(pl061->base + GPIODIR);
bea41504	96	gpiodir \|= BIT(offset);
2796325f	97	writeb(gpiodir, pl061->base + GPIODIR);
64b997c5 VK	98
	99	/*
	100	* gpio value is set again, because pl061 doesn't allow to set value of
	101	* a gpio pin before configuring it in OUT mode.
	102	*/
2796325f	103	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
99b9b45d	104	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	105
	106	return 0;
	107	}
	108
	109	static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
	110	{
2796325f	111	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859	112
2796325f	113	return !!readb(pl061->base + (BIT(offset + 2)));
1e9c2859 BS	114	}
	115
	116	static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
	117	{
2796325f	118	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859	119
2796325f	120	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
1e9c2859 BS	121	}
1e9c2859 BS	122
b2221869	123	static int pl061_irq_type(struct irq_data *d, unsigned trigger)
1e9c2859	124	{
8d5b24bd	125	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	126	struct pl061 *pl061 = gpiochip_get_data(gc);
f1f70479	127	int offset = irqd_to_hwirq(d);
1e9c2859 BS	128	unsigned long flags;
1e9c2859 BS	129	u8 gpiois, gpioibe, gpioiev;
438a2c9a	130	u8 bit = BIT(offset);
1e9c2859	131
c1cc9b97	132	if (offset < 0 \|\| offset >= PL061_GPIO_NR)
1e9c2859 BS	133	return -EINVAL;
1e9c2859 BS	134
1dbf7f29 LW	135	if ((trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) &&
	136	(trigger & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING)))
	137	{
58383c78	138	dev_err(gc->parent,
1dbf7f29 LW	139	"trying to configure line %d for both level and edge "
	140	"detection, choose one!\n",
	141	offset);
	142	return -EINVAL;
	143	}
	144
21d4de14	145
99b9b45d	146	raw_spin_lock_irqsave(&pl061->lock, flags);
21d4de14	147
2796325f LW	148	gpioiev = readb(pl061->base + GPIOIEV);
	149	gpiois = readb(pl061->base + GPIOIS);
	150	gpioibe = readb(pl061->base + GPIOIBE);
21d4de14	151
1e9c2859	152	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
1dbf7f29 LW	153	bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
	154
	155	/* Disable edge detection */
	156	gpioibe &= ~bit;
	157	/* Enable level detection */
438a2c9a	158	gpiois \|= bit;
1dbf7f29 LW	159	/* Select polarity */
1dbf7f29 LW	160	if (polarity)
438a2c9a	161	gpioiev \|= bit;
1e9c2859	162	else
438a2c9a	163	gpioiev &= ~bit;
26ba9cd4	164	irq_set_handler_locked(d, handle_level_irq);
58383c78	165	dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
1dbf7f29 LW	166	offset,
	167	polarity ? "HIGH" : "LOW");
	168	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
	169	/* Disable level detection */
	170	gpiois &= ~bit;
	171	/* Select both edges, setting this makes GPIOEV be ignored */
438a2c9a	172	gpioibe \|= bit;
26ba9cd4	173	irq_set_handler_locked(d, handle_edge_irq);
58383c78	174	dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
1dbf7f29 LW	175	} else if ((trigger & IRQ_TYPE_EDGE_RISING) \|\|
	176	(trigger & IRQ_TYPE_EDGE_FALLING)) {
	177	bool rising = trigger & IRQ_TYPE_EDGE_RISING;
	178
	179	/* Disable level detection */
	180	gpiois &= ~bit;
	181	/* Clear detection on both edges */
438a2c9a	182	gpioibe &= ~bit;
1dbf7f29 LW	183	/* Select edge */
1dbf7f29 LW	184	if (rising)
438a2c9a	185	gpioiev \|= bit;
1dbf7f29	186	else
438a2c9a	187	gpioiev &= ~bit;
26ba9cd4	188	irq_set_handler_locked(d, handle_edge_irq);
58383c78	189	dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
1dbf7f29 LW	190	offset,
	191	rising ? "RISING" : "FALLING");
	192	} else {
	193	/* No trigger: disable everything */
	194	gpiois &= ~bit;
	195	gpioibe &= ~bit;
	196	gpioiev &= ~bit;
26ba9cd4	197	irq_set_handler_locked(d, handle_bad_irq);
58383c78	198	dev_warn(gc->parent, "no trigger selected for line %d\n",
1dbf7f29	199	offset);
1e9c2859	200	}
1e9c2859	201
2796325f LW	202	writeb(gpiois, pl061->base + GPIOIS);
	203	writeb(gpioibe, pl061->base + GPIOIBE);
	204	writeb(gpioiev, pl061->base + GPIOIEV);
1e9c2859	205
99b9b45d	206	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	207
	208	return 0;
	209	}
	210
bd0b9ac4	211	static void pl061_irq_handler(struct irq_desc *desc)
1e9c2859	212	{
2de0dbc5 RH	213	unsigned long pending;
2de0dbc5 RH	214	int offset;
8d5b24bd	215	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
2796325f	216	struct pl061 *pl061 = gpiochip_get_data(gc);
dece904d	217	struct irq_chip *irqchip = irq_desc_get_chip(desc);
1e9c2859	218
dece904d	219	chained_irq_enter(irqchip, desc);
1e9c2859	220
2796325f	221	pending = readb(pl061->base + GPIOMIS);
2de0dbc5	222	if (pending) {
984b3f57	223	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
8d5b24bd LW	224	generic_handle_irq(irq_find_mapping(gc->irqdomain,
8d5b24bd LW	225	offset));
1e9c2859	226	}
2de0dbc5	227
dece904d	228	chained_irq_exit(irqchip, desc);
1e9c2859 BS	229	}
1e9c2859 BS	230
f1f70479	231	static void pl061_irq_mask(struct irq_data *d)
3ab52475	232	{
8d5b24bd	233	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	234	struct pl061 *pl061 = gpiochip_get_data(gc);
bea41504	235	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	236	u8 gpioie;
f1f70479 HZ	237
99b9b45d	238	raw_spin_lock(&pl061->lock);
2796325f LW	239	gpioie = readb(pl061->base + GPIOIE) & ~mask;
2796325f LW	240	writeb(gpioie, pl061->base + GPIOIE);
99b9b45d	241	raw_spin_unlock(&pl061->lock);
f1f70479	242	}
3ab52475	243
f1f70479 HZ	244	static void pl061_irq_unmask(struct irq_data *d)
f1f70479 HZ	245	{
8d5b24bd	246	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	247	struct pl061 *pl061 = gpiochip_get_data(gc);
bea41504	248	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	249	u8 gpioie;
f1f70479 HZ	250
99b9b45d	251	raw_spin_lock(&pl061->lock);
2796325f LW	252	gpioie = readb(pl061->base + GPIOIE) \| mask;
2796325f LW	253	writeb(gpioie, pl061->base + GPIOIE);
99b9b45d	254	raw_spin_unlock(&pl061->lock);
f1f70479 HZ	255	}
f1f70479 HZ	256
26ba9cd4 LW	257	/**
	258	* pl061_irq_ack() - ACK an edge IRQ
	259	* @d: IRQ data for this IRQ
	260	*
	261	* This gets called from the edge IRQ handler to ACK the edge IRQ
	262	* in the GPIOIC (interrupt-clear) register. For level IRQs this is
	263	* not needed: these go away when the level signal goes away.
	264	*/
	265	static void pl061_irq_ack(struct irq_data *d)
	266	{
	267	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	268	struct pl061 *pl061 = gpiochip_get_data(gc);
26ba9cd4 LW	269	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
26ba9cd4 LW	270
99b9b45d	271	raw_spin_lock(&pl061->lock);
2796325f	272	writeb(mask, pl061->base + GPIOIC);
99b9b45d	273	raw_spin_unlock(&pl061->lock);
26ba9cd4 LW	274	}
26ba9cd4 LW	275
2f46205b SH	276	static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
	277	{
	278	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	279	struct pl061 *pl061 = gpiochip_get_data(gc);
2f46205b	280
2796325f	281	return irq_set_irq_wake(pl061->parent_irq, state);
2f46205b SH	282	}
2f46205b SH	283
f1f70479	284	static struct irq_chip pl061_irqchip = {
9ae7e9e3	285	.name = "pl061",
26ba9cd4	286	.irq_ack = pl061_irq_ack,
f1f70479 HZ	287	.irq_mask = pl061_irq_mask,
	288	.irq_unmask = pl061_irq_unmask,
	289	.irq_set_type = pl061_irq_type,
2f46205b	290	.irq_set_wake = pl061_irq_set_wake,
f1f70479 HZ	291	};
f1f70479 HZ	292
8944df72	293	static int pl061_probe(struct amba_device adev, const struct amba_id id)
1e9c2859	294	{
8944df72	295	struct device *dev = &adev->dev;
2796325f	296	struct pl061 *pl061;
6da7b0dd	297	int ret, irq;
1e9c2859	298
2796325f LW	299	pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
2796325f LW	300	if (pl061 == NULL)
1e9c2859 BS	301	return -ENOMEM;
1e9c2859 BS	302
2796325f LW	303	pl061->base = devm_ioremap_resource(dev, &adev->res);
	304	if (IS_ERR(pl061->base))
	305	return PTR_ERR(pl061->base);
1e9c2859	306
99b9b45d	307	raw_spin_lock_init(&pl061->lock);
31831f41	308	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
2796325f LW	309	pl061->gc.request = gpiochip_generic_request;
2796325f LW	310	pl061->gc.free = gpiochip_generic_free;
31831f41	311	}
1e9c2859	312
6da7b0dd	313	pl061->gc.base = -1;
2796325f LW	314	pl061->gc.get_direction = pl061_get_direction;
	315	pl061->gc.direction_input = pl061_direction_input;
	316	pl061->gc.direction_output = pl061_direction_output;
	317	pl061->gc.get = pl061_get_value;
	318	pl061->gc.set = pl061_set_value;
	319	pl061->gc.ngpio = PL061_GPIO_NR;
	320	pl061->gc.label = dev_name(dev);
	321	pl061->gc.parent = dev;
	322	pl061->gc.owner = THIS_MODULE;
	323
	324	ret = gpiochip_add_data(&pl061->gc, pl061);
1e9c2859	325	if (ret)
8944df72	326	return ret;
1e9c2859 BS	327
	328	/*
	329	* irq_chip support
	330	*/
2796325f	331	writeb(0, pl061->base + GPIOIE); /* disable irqs */
8944df72	332	irq = adev->irq[0];
7808755d LW	333	if (irq < 0) {
7808755d LW	334	dev_err(&adev->dev, "invalid IRQ\n");
8944df72	335	return -ENODEV;
7808755d	336	}
2796325f	337	pl061->parent_irq = irq;
8944df72	338
2796325f	339	ret = gpiochip_irqchip_add(&pl061->gc, &pl061_irqchip,
6da7b0dd	340	0, handle_bad_irq,
8d5b24bd LW	341	IRQ_TYPE_NONE);
	342	if (ret) {
	343	dev_info(&adev->dev, "could not add irqchip\n");
	344	return ret;
7808755d	345	}
2796325f	346	gpiochip_set_chained_irqchip(&pl061->gc, &pl061_irqchip,
8d5b24bd	347	irq, pl061_irq_handler);
2ba3154d	348
2796325f	349	amba_set_drvdata(adev, pl061);
76b3627e FE	350	dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
76b3627e FE	351	&adev->res.start);
e198a8de	352
1e9c2859	353	return 0;
1e9c2859 BS	354	}
1e9c2859 BS	355
e198a8de DS	356	#ifdef CONFIG_PM
	357	static int pl061_suspend(struct device *dev)
	358	{
2796325f	359	struct pl061 *pl061 = dev_get_drvdata(dev);
e198a8de DS	360	int offset;
e198a8de DS	361
2796325f LW	362	pl061->csave_regs.gpio_data = 0;
	363	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
	364	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
	365	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
	366	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
	367	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
e198a8de DS	368
e198a8de DS	369	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
2796325f LW	370	if (pl061->csave_regs.gpio_dir & (BIT(offset)))
	371	pl061->csave_regs.gpio_data \|=
	372	pl061_get_value(&pl061->gc, offset) << offset;
e198a8de DS	373	}
	374
	375	return 0;
	376	}
	377
	378	static int pl061_resume(struct device *dev)
	379	{
2796325f	380	struct pl061 *pl061 = dev_get_drvdata(dev);
e198a8de DS	381	int offset;
	382
	383	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
2796325f LW	384	if (pl061->csave_regs.gpio_dir & (BIT(offset)))
	385	pl061_direction_output(&pl061->gc, offset,
	386	pl061->csave_regs.gpio_data &
bea41504	387	(BIT(offset)));
e198a8de	388	else
2796325f	389	pl061_direction_input(&pl061->gc, offset);
e198a8de DS	390	}
e198a8de DS	391
2796325f LW	392	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
	393	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
	394	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
	395	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
e198a8de DS	396
	397	return 0;
	398	}
	399
6e33aced VK	400	static const struct dev_pm_ops pl061_dev_pm_ops = {
	401	.suspend = pl061_suspend,
	402	.resume = pl061_resume,
	403	.freeze = pl061_suspend,
	404	.restore = pl061_resume,
	405	};
e198a8de DS	406	#endif
e198a8de DS	407
2c39c9e1	408	static struct amba_id pl061_ids[] = {
1e9c2859 BS	409	{
	410	.id = 0x00041061,
	411	.mask = 0x000fffff,
	412	},
	413	{ 0, 0 },
	414	};
	415
	416	static struct amba_driver pl061_gpio_driver = {
	417	.drv = {
	418	.name = "pl061_gpio",
e198a8de DS	419	#ifdef CONFIG_PM
	420	.pm = &pl061_dev_pm_ops,
	421	#endif
1e9c2859 BS	422	},
	423	.id_table = pl061_ids,
	424	.probe = pl061_probe,
	425	};
	426
	427	static int __init pl061_gpio_init(void)
	428	{
	429	return amba_driver_register(&pl061_gpio_driver);
	430	}
ef3e7100	431	device_initcall(pl061_gpio_init);