[mirror_ubuntu-focal-kernel.git] / drivers / gpio / gpio-pl061.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2008, 2009 Provigent Ltd.
 *
 * Author: Baruch Siach <baruch@tkos.co.il>
 *
 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
 *
 * Data sheet: ARM DDI 0190B, September 2000
 */
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#define GPIODIR 0x400
#define GPIOIS  0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE  0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC  0x41C

#define PL061_GPIO_NR	8

#ifdef CONFIG_PM
struct pl061_context_save_regs {
	u8 gpio_data;
	u8 gpio_dir;
	u8 gpio_is;
	u8 gpio_ibe;
	u8 gpio_iev;
	u8 gpio_ie;
};
#endif

struct pl061 {
	raw_spinlock_t		lock;

	void __iomem		*base;
	struct gpio_chip	gc;
	struct irq_chip		irq_chip;
	int			parent_irq;

#ifdef CONFIG_PM
	struct pl061_context_save_regs csave_regs;
#endif
};

static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return !(readb(pl061->base + GPIODIR) & BIT(offset));
}

static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	raw_spin_lock_irqsave(&pl061->lock, flags);
	gpiodir = readb(pl061->base + GPIODIR);
	gpiodir &= ~(BIT(offset));
	writeb(gpiodir, pl061->base + GPIODIR);
	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	raw_spin_lock_irqsave(&pl061->lock, flags);
	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
	gpiodir = readb(pl061->base + GPIODIR);
	gpiodir |= BIT(offset);
	writeb(gpiodir, pl061->base + GPIODIR);

	/*
	 * gpio value is set again, because pl061 doesn't allow to set value of
	 * a gpio pin before configuring it in OUT mode.
	 */
	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return !!readb(pl061->base + (BIT(offset + 2)));
}

static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
}

static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u8 gpiois, gpioibe, gpioiev;
	u8 bit = BIT(offset);

	if (offset < 0 || offset >= PL061_GPIO_NR)
		return -EINVAL;

	if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
	    (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
	{
		dev_err(gc->parent,
			"trying to configure line %d for both level and edge "
			"detection, choose one!\n",
			offset);
		return -EINVAL;
	}


	raw_spin_lock_irqsave(&pl061->lock, flags);

	gpioiev = readb(pl061->base + GPIOIEV);
	gpiois = readb(pl061->base + GPIOIS);
	gpioibe = readb(pl061->base + GPIOIBE);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;

		/* Disable edge detection */
		gpioibe &= ~bit;
		/* Enable level detection */
		gpiois |= bit;
		/* Select polarity */
		if (polarity)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_level_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
			offset,
			polarity ? "HIGH" : "LOW");
	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		/* Disable level detection */
		gpiois &= ~bit;
		/* Select both edges, setting this makes GPIOEV be ignored */
		gpioibe |= bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
	} else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
		   (trigger & IRQ_TYPE_EDGE_FALLING)) {
		bool rising = trigger & IRQ_TYPE_EDGE_RISING;

		/* Disable level detection */
		gpiois &= ~bit;
		/* Clear detection on both edges */
		gpioibe &= ~bit;
		/* Select edge */
		if (rising)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
			offset,
			rising ? "RISING" : "FALLING");
	} else {
		/* No trigger: disable everything */
		gpiois &= ~bit;
		gpioibe &= ~bit;
		gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_bad_irq);
		dev_warn(gc->parent, "no trigger selected for line %d\n",
			 offset);
	}

	writeb(gpiois, pl061->base + GPIOIS);
	writeb(gpioibe, pl061->base + GPIOIBE);
	writeb(gpioiev, pl061->base + GPIOIEV);

	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static void pl061_irq_handler(struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readb(pl061->base + GPIOMIS);
	if (pending) {
		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
			generic_handle_irq(irq_find_mapping(gc->irq.domain,
							    offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void pl061_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	raw_spin_lock(&pl061->lock);
	gpioie = readb(pl061->base + GPIOIE) & ~mask;
	writeb(gpioie, pl061->base + GPIOIE);
	raw_spin_unlock(&pl061->lock);
}

static void pl061_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	raw_spin_lock(&pl061->lock);
	gpioie = readb(pl061->base + GPIOIE) | mask;
	writeb(gpioie, pl061->base + GPIOIE);
	raw_spin_unlock(&pl061->lock);
}

/**
 * pl061_irq_ack() - ACK an edge IRQ
 * @d: IRQ data for this IRQ
 *
 * This gets called from the edge IRQ handler to ACK the edge IRQ
 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
 * not needed: these go away when the level signal goes away.
 */
static void pl061_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);

	raw_spin_lock(&pl061->lock);
	writeb(mask, pl061->base + GPIOIC);
	raw_spin_unlock(&pl061->lock);
}

static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return irq_set_irq_wake(pl061->parent_irq, state);
}

static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
	struct device *dev = &adev->dev;
	struct pl061 *pl061;
	struct gpio_irq_chip *girq;
	int ret, irq;

	pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
	if (pl061 == NULL)
		return -ENOMEM;

	pl061->base = devm_ioremap_resource(dev, &adev->res);
	if (IS_ERR(pl061->base))
		return PTR_ERR(pl061->base);

	raw_spin_lock_init(&pl061->lock);
	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
		pl061->gc.request = gpiochip_generic_request;
		pl061->gc.free = gpiochip_generic_free;
	}

	pl061->gc.base = -1;
	pl061->gc.get_direction = pl061_get_direction;
	pl061->gc.direction_input = pl061_direction_input;
	pl061->gc.direction_output = pl061_direction_output;
	pl061->gc.get = pl061_get_value;
	pl061->gc.set = pl061_set_value;
	pl061->gc.ngpio = PL061_GPIO_NR;
	pl061->gc.label = dev_name(dev);
	pl061->gc.parent = dev;
	pl061->gc.owner = THIS_MODULE;

	/*
	 * irq_chip support
	 */
	pl061->irq_chip.name = dev_name(dev);
	pl061->irq_chip.irq_ack	= pl061_irq_ack;
	pl061->irq_chip.irq_mask = pl061_irq_mask;
	pl061->irq_chip.irq_unmask = pl061_irq_unmask;
	pl061->irq_chip.irq_set_type = pl061_irq_type;
	pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;

	writeb(0, pl061->base + GPIOIE); /* disable irqs */
	irq = adev->irq[0];
	if (irq < 0) {
		dev_err(&adev->dev, "invalid IRQ\n");
		return -ENODEV;
	}
	pl061->parent_irq = irq;

	girq = &pl061->gc.irq;
	girq->chip = &pl061->irq_chip;
	girq->parent_handler = pl061_irq_handler;
	girq->num_parents = 1;
	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
				     GFP_KERNEL);
	if (!girq->parents)
		return -ENOMEM;
	girq->parents[0] = irq;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_bad_irq;

	ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
	if (ret)
		return ret;

	amba_set_drvdata(adev, pl061);
	dev_info(dev, "PL061 GPIO chip registered\n");

	return 0;
}

#ifdef CONFIG_PM
static int pl061_suspend(struct device *dev)
{
	struct pl061 *pl061 = dev_get_drvdata(dev);
	int offset;

	pl061->csave_regs.gpio_data = 0;
	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
			pl061->csave_regs.gpio_data |=
				pl061_get_value(&pl061->gc, offset) << offset;
	}

	return 0;
}

static int pl061_resume(struct device *dev)
{
	struct pl061 *pl061 = dev_get_drvdata(dev);
	int offset;

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
			pl061_direction_output(&pl061->gc, offset,
					pl061->csave_regs.gpio_data &
					(BIT(offset)));
		else
			pl061_direction_input(&pl061->gc, offset);
	}

	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);

	return 0;
}

static const struct dev_pm_ops pl061_dev_pm_ops = {
	.suspend = pl061_suspend,
	.resume = pl061_resume,
	.freeze = pl061_suspend,
	.restore = pl061_resume,
};
#endif

static const struct amba_id pl061_ids[] = {
	{
		.id	= 0x00041061,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

static struct amba_driver pl061_gpio_driver = {
	.drv = {
		.name	= "pl061_gpio",
#ifdef CONFIG_PM
		.pm	= &pl061_dev_pm_ops,
#endif
	},
	.id_table	= pl061_ids,
	.probe		= pl061_probe,
};

static int __init pl061_gpio_init(void)
{
	return amba_driver_register(&pl061_gpio_driver);
}
device_initcall(pl061_gpio_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1e9c2859	2	/*
c103de24	3	* Copyright (C) 2008, 2009 Provigent Ltd.
1e9c2859	4	*
ef3e7100 PG	5	* Author: Baruch Siach <baruch@tkos.co.il>
ef3e7100 PG	6	*
1e9c2859 BS	7	* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
	8	*
	9	* Data sheet: ARM DDI 0190B, September 2000
	10	*/
	11	#include <linux/spinlock.h>
	12	#include <linux/errno.h>
ef3e7100	13	#include <linux/init.h>
1e9c2859 BS	14	#include <linux/io.h>
1e9c2859 BS	15	#include <linux/ioport.h>
2f46205b	16	#include <linux/interrupt.h>
1e9c2859	17	#include <linux/irq.h>
de88cbb7	18	#include <linux/irqchip/chained_irq.h>
1e9c2859	19	#include <linux/bitops.h>
dcc6ceef	20	#include <linux/gpio/driver.h>
1e9c2859 BS	21	#include <linux/device.h>
1e9c2859 BS	22	#include <linux/amba/bus.h>
5a0e3ad6	23	#include <linux/slab.h>
39b70ee0	24	#include <linux/pinctrl/consumer.h>
e198a8de	25	#include <linux/pm.h>
1e9c2859 BS	26
	27	#define GPIODIR 0x400
	28	#define GPIOIS 0x404
	29	#define GPIOIBE 0x408
	30	#define GPIOIEV 0x40C
	31	#define GPIOIE 0x410
	32	#define GPIORIS 0x414
	33	#define GPIOMIS 0x418
	34	#define GPIOIC 0x41C
	35
	36	#define PL061_GPIO_NR 8
	37
e198a8de DS	38	#ifdef CONFIG_PM
	39	struct pl061_context_save_regs {
	40	u8 gpio_data;
	41	u8 gpio_dir;
	42	u8 gpio_is;
	43	u8 gpio_ibe;
	44	u8 gpio_iev;
	45	u8 gpio_ie;
	46	};
	47	#endif
1e9c2859	48
538f76c5	49	struct pl061 {
99b9b45d	50	raw_spinlock_t lock;
1e9c2859 BS	51
1e9c2859 BS	52	void __iomem *base;
1e9c2859	53	struct gpio_chip gc;
ed8dce4c	54	struct irq_chip irq_chip;
9c18be8e	55	int parent_irq;
e198a8de DS	56
	57	#ifdef CONFIG_PM
	58	struct pl061_context_save_regs csave_regs;
	59	#endif
1e9c2859 BS	60	};
1e9c2859 BS	61
3484f1be LW	62	static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
3484f1be LW	63	{
2796325f	64	struct pl061 *pl061 = gpiochip_get_data(gc);
3484f1be	65
2796325f	66	return !(readb(pl061->base + GPIODIR) & BIT(offset));
3484f1be LW	67	}
3484f1be LW	68
1e9c2859 BS	69	static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
1e9c2859 BS	70	{
2796325f	71	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859 BS	72	unsigned long flags;
	73	unsigned char gpiodir;
	74
99b9b45d	75	raw_spin_lock_irqsave(&pl061->lock, flags);
2796325f	76	gpiodir = readb(pl061->base + GPIODIR);
bea41504	77	gpiodir &= ~(BIT(offset));
2796325f	78	writeb(gpiodir, pl061->base + GPIODIR);
99b9b45d	79	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	80
	81	return 0;
	82	}
	83
	84	static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
	85	int value)
	86	{
2796325f	87	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859 BS	88	unsigned long flags;
	89	unsigned char gpiodir;
	90
99b9b45d	91	raw_spin_lock_irqsave(&pl061->lock, flags);
2796325f LW	92	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
2796325f LW	93	gpiodir = readb(pl061->base + GPIODIR);
bea41504	94	gpiodir \|= BIT(offset);
2796325f	95	writeb(gpiodir, pl061->base + GPIODIR);
64b997c5 VK	96
	97	/*
	98	* gpio value is set again, because pl061 doesn't allow to set value of
	99	* a gpio pin before configuring it in OUT mode.
	100	*/
2796325f	101	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
99b9b45d	102	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	103
	104	return 0;
	105	}
	106
	107	static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
	108	{
2796325f	109	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859	110
2796325f	111	return !!readb(pl061->base + (BIT(offset + 2)));
1e9c2859 BS	112	}
	113
	114	static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
	115	{
2796325f	116	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859	117
2796325f	118	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
1e9c2859 BS	119	}
1e9c2859 BS	120
b2221869	121	static int pl061_irq_type(struct irq_data *d, unsigned trigger)
1e9c2859	122	{
8d5b24bd	123	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	124	struct pl061 *pl061 = gpiochip_get_data(gc);
f1f70479	125	int offset = irqd_to_hwirq(d);
1e9c2859 BS	126	unsigned long flags;
1e9c2859 BS	127	u8 gpiois, gpioibe, gpioiev;
438a2c9a	128	u8 bit = BIT(offset);
1e9c2859	129
c1cc9b97	130	if (offset < 0 \|\| offset >= PL061_GPIO_NR)
1e9c2859 BS	131	return -EINVAL;
1e9c2859 BS	132
1dbf7f29 LW	133	if ((trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) &&
	134	(trigger & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING)))
	135	{
58383c78	136	dev_err(gc->parent,
1dbf7f29 LW	137	"trying to configure line %d for both level and edge "
	138	"detection, choose one!\n",
	139	offset);
	140	return -EINVAL;
	141	}
	142
21d4de14	143
99b9b45d	144	raw_spin_lock_irqsave(&pl061->lock, flags);
21d4de14	145
2796325f LW	146	gpioiev = readb(pl061->base + GPIOIEV);
	147	gpiois = readb(pl061->base + GPIOIS);
	148	gpioibe = readb(pl061->base + GPIOIBE);
21d4de14	149
1e9c2859	150	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
1dbf7f29 LW	151	bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
	152
	153	/* Disable edge detection */
	154	gpioibe &= ~bit;
	155	/* Enable level detection */
438a2c9a	156	gpiois \|= bit;
1dbf7f29 LW	157	/* Select polarity */
1dbf7f29 LW	158	if (polarity)
438a2c9a	159	gpioiev \|= bit;
1e9c2859	160	else
438a2c9a	161	gpioiev &= ~bit;
26ba9cd4	162	irq_set_handler_locked(d, handle_level_irq);
58383c78	163	dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
1dbf7f29 LW	164	offset,
	165	polarity ? "HIGH" : "LOW");
	166	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
	167	/* Disable level detection */
	168	gpiois &= ~bit;
	169	/* Select both edges, setting this makes GPIOEV be ignored */
438a2c9a	170	gpioibe \|= bit;
26ba9cd4	171	irq_set_handler_locked(d, handle_edge_irq);
58383c78	172	dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
1dbf7f29 LW	173	} else if ((trigger & IRQ_TYPE_EDGE_RISING) \|\|
	174	(trigger & IRQ_TYPE_EDGE_FALLING)) {
	175	bool rising = trigger & IRQ_TYPE_EDGE_RISING;
	176
	177	/* Disable level detection */
	178	gpiois &= ~bit;
	179	/* Clear detection on both edges */
438a2c9a	180	gpioibe &= ~bit;
1dbf7f29 LW	181	/* Select edge */
1dbf7f29 LW	182	if (rising)
438a2c9a	183	gpioiev \|= bit;
1dbf7f29	184	else
438a2c9a	185	gpioiev &= ~bit;
26ba9cd4	186	irq_set_handler_locked(d, handle_edge_irq);
58383c78	187	dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
1dbf7f29 LW	188	offset,
	189	rising ? "RISING" : "FALLING");
	190	} else {
	191	/* No trigger: disable everything */
	192	gpiois &= ~bit;
	193	gpioibe &= ~bit;
	194	gpioiev &= ~bit;
26ba9cd4	195	irq_set_handler_locked(d, handle_bad_irq);
58383c78	196	dev_warn(gc->parent, "no trigger selected for line %d\n",
1dbf7f29	197	offset);
1e9c2859	198	}
1e9c2859	199
2796325f LW	200	writeb(gpiois, pl061->base + GPIOIS);
	201	writeb(gpioibe, pl061->base + GPIOIBE);
	202	writeb(gpioiev, pl061->base + GPIOIEV);
1e9c2859	203
99b9b45d	204	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	205
	206	return 0;
	207	}
	208
bd0b9ac4	209	static void pl061_irq_handler(struct irq_desc *desc)
1e9c2859	210	{
2de0dbc5 RH	211	unsigned long pending;
2de0dbc5 RH	212	int offset;
8d5b24bd	213	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
2796325f	214	struct pl061 *pl061 = gpiochip_get_data(gc);
dece904d	215	struct irq_chip *irqchip = irq_desc_get_chip(desc);
1e9c2859	216
dece904d	217	chained_irq_enter(irqchip, desc);
1e9c2859	218
2796325f	219	pending = readb(pl061->base + GPIOMIS);
2de0dbc5	220	if (pending) {
984b3f57	221	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
f0fbe7bc	222	generic_handle_irq(irq_find_mapping(gc->irq.domain,
8d5b24bd	223	offset));
1e9c2859	224	}
2de0dbc5	225
dece904d	226	chained_irq_exit(irqchip, desc);
1e9c2859 BS	227	}
1e9c2859 BS	228
f1f70479	229	static void pl061_irq_mask(struct irq_data *d)
3ab52475	230	{
8d5b24bd	231	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	232	struct pl061 *pl061 = gpiochip_get_data(gc);
bea41504	233	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	234	u8 gpioie;
f1f70479 HZ	235
99b9b45d	236	raw_spin_lock(&pl061->lock);
2796325f LW	237	gpioie = readb(pl061->base + GPIOIE) & ~mask;
2796325f LW	238	writeb(gpioie, pl061->base + GPIOIE);
99b9b45d	239	raw_spin_unlock(&pl061->lock);
f1f70479	240	}
3ab52475	241
f1f70479 HZ	242	static void pl061_irq_unmask(struct irq_data *d)
f1f70479 HZ	243	{
8d5b24bd	244	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	245	struct pl061 *pl061 = gpiochip_get_data(gc);
bea41504	246	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	247	u8 gpioie;
f1f70479 HZ	248
99b9b45d	249	raw_spin_lock(&pl061->lock);
2796325f LW	250	gpioie = readb(pl061->base + GPIOIE) \| mask;
2796325f LW	251	writeb(gpioie, pl061->base + GPIOIE);
99b9b45d	252	raw_spin_unlock(&pl061->lock);
f1f70479 HZ	253	}
f1f70479 HZ	254
26ba9cd4 LW	255	/**
	256	* pl061_irq_ack() - ACK an edge IRQ
	257	* @d: IRQ data for this IRQ
	258	*
	259	* This gets called from the edge IRQ handler to ACK the edge IRQ
	260	* in the GPIOIC (interrupt-clear) register. For level IRQs this is
	261	* not needed: these go away when the level signal goes away.
	262	*/
	263	static void pl061_irq_ack(struct irq_data *d)
	264	{
	265	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	266	struct pl061 *pl061 = gpiochip_get_data(gc);
26ba9cd4 LW	267	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
26ba9cd4 LW	268
99b9b45d	269	raw_spin_lock(&pl061->lock);
2796325f	270	writeb(mask, pl061->base + GPIOIC);
99b9b45d	271	raw_spin_unlock(&pl061->lock);
26ba9cd4 LW	272	}
26ba9cd4 LW	273
2f46205b SH	274	static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
	275	{
	276	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	277	struct pl061 *pl061 = gpiochip_get_data(gc);
2f46205b	278
2796325f	279	return irq_set_irq_wake(pl061->parent_irq, state);
2f46205b SH	280	}
2f46205b SH	281
8944df72	282	static int pl061_probe(struct amba_device adev, const struct amba_id id)
1e9c2859	283	{
8944df72	284	struct device *dev = &adev->dev;
2796325f	285	struct pl061 *pl061;
04ce935c	286	struct gpio_irq_chip *girq;
6da7b0dd	287	int ret, irq;
1e9c2859	288
2796325f LW	289	pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
2796325f LW	290	if (pl061 == NULL)
1e9c2859 BS	291	return -ENOMEM;
1e9c2859 BS	292
2796325f LW	293	pl061->base = devm_ioremap_resource(dev, &adev->res);
	294	if (IS_ERR(pl061->base))
	295	return PTR_ERR(pl061->base);
1e9c2859	296
99b9b45d	297	raw_spin_lock_init(&pl061->lock);
31831f41	298	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
2796325f LW	299	pl061->gc.request = gpiochip_generic_request;
2796325f LW	300	pl061->gc.free = gpiochip_generic_free;
31831f41	301	}
1e9c2859	302
6da7b0dd	303	pl061->gc.base = -1;
2796325f LW	304	pl061->gc.get_direction = pl061_get_direction;
	305	pl061->gc.direction_input = pl061_direction_input;
	306	pl061->gc.direction_output = pl061_direction_output;
	307	pl061->gc.get = pl061_get_value;
	308	pl061->gc.set = pl061_set_value;
	309	pl061->gc.ngpio = PL061_GPIO_NR;
	310	pl061->gc.label = dev_name(dev);
	311	pl061->gc.parent = dev;
	312	pl061->gc.owner = THIS_MODULE;
	313
1e9c2859 BS	314	/*
	315	* irq_chip support
	316	*/
ed8dce4c MS	317	pl061->irq_chip.name = dev_name(dev);
	318	pl061->irq_chip.irq_ack = pl061_irq_ack;
	319	pl061->irq_chip.irq_mask = pl061_irq_mask;
	320	pl061->irq_chip.irq_unmask = pl061_irq_unmask;
	321	pl061->irq_chip.irq_set_type = pl061_irq_type;
	322	pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;
	323
2796325f	324	writeb(0, pl061->base + GPIOIE); /* disable irqs */
8944df72	325	irq = adev->irq[0];
7808755d LW	326	if (irq < 0) {
7808755d LW	327	dev_err(&adev->dev, "invalid IRQ\n");
8944df72	328	return -ENODEV;
7808755d	329	}
2796325f	330	pl061->parent_irq = irq;
8944df72	331
04ce935c LW	332	girq = &pl061->gc.irq;
	333	girq->chip = &pl061->irq_chip;
	334	girq->parent_handler = pl061_irq_handler;
	335	girq->num_parents = 1;
	336	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
	337	GFP_KERNEL);
	338	if (!girq->parents)
	339	return -ENOMEM;
	340	girq->parents[0] = irq;
	341	girq->default_type = IRQ_TYPE_NONE;
	342	girq->handler = handle_bad_irq;
	343
	344	ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
	345	if (ret)
8d5b24bd	346	return ret;
2ba3154d	347
2796325f	348	amba_set_drvdata(adev, pl061);
4d19addd	349	dev_info(dev, "PL061 GPIO chip registered\n");
e198a8de	350
1e9c2859	351	return 0;
1e9c2859 BS	352	}
1e9c2859 BS	353
e198a8de DS	354	#ifdef CONFIG_PM
	355	static int pl061_suspend(struct device *dev)
	356	{
2796325f	357	struct pl061 *pl061 = dev_get_drvdata(dev);
e198a8de DS	358	int offset;
e198a8de DS	359
2796325f LW	360	pl061->csave_regs.gpio_data = 0;
	361	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
	362	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
	363	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
	364	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
	365	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
e198a8de DS	366
e198a8de DS	367	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
2796325f LW	368	if (pl061->csave_regs.gpio_dir & (BIT(offset)))
	369	pl061->csave_regs.gpio_data \|=
	370	pl061_get_value(&pl061->gc, offset) << offset;
e198a8de DS	371	}
	372
	373	return 0;
	374	}
	375
	376	static int pl061_resume(struct device *dev)
	377	{
2796325f	378	struct pl061 *pl061 = dev_get_drvdata(dev);
e198a8de DS	379	int offset;
	380
	381	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
2796325f LW	382	if (pl061->csave_regs.gpio_dir & (BIT(offset)))
	383	pl061_direction_output(&pl061->gc, offset,
	384	pl061->csave_regs.gpio_data &
bea41504	385	(BIT(offset)));
e198a8de	386	else
2796325f	387	pl061_direction_input(&pl061->gc, offset);
e198a8de DS	388	}
e198a8de DS	389
2796325f LW	390	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
	391	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
	392	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
	393	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
e198a8de DS	394
	395	return 0;
	396	}
	397
6e33aced VK	398	static const struct dev_pm_ops pl061_dev_pm_ops = {
	399	.suspend = pl061_suspend,
	400	.resume = pl061_resume,
	401	.freeze = pl061_suspend,
	402	.restore = pl061_resume,
	403	};
e198a8de DS	404	#endif
e198a8de DS	405
72c7c78e	406	static const struct amba_id pl061_ids[] = {
1e9c2859 BS	407	{
	408	.id = 0x00041061,
	409	.mask = 0x000fffff,
	410	},
	411	{ 0, 0 },
	412	};
	413
	414	static struct amba_driver pl061_gpio_driver = {
	415	.drv = {
	416	.name = "pl061_gpio",
e198a8de DS	417	#ifdef CONFIG_PM
	418	.pm = &pl061_dev_pm_ops,
	419	#endif
1e9c2859 BS	420	},
	421	.id_table = pl061_ids,
	422	.probe = pl061_probe,
	423	};
	424
	425	static int __init pl061_gpio_init(void)
	426	{
	427	return amba_driver_register(&pl061_gpio_driver);
	428	}
ef3e7100	429	device_initcall(pl061_gpio_init);