[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-pl061.c

/*
 * Copyright (C) 2008, 2009 Provigent Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
 *
 * Data sheet: ARM DDI 0190B, September 2000
 */
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/bitops.h>
#include <linux/workqueue.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/slab.h>
#include <linux/pm.h>
#include <asm/mach/irq.h>

#define GPIODIR 0x400
#define GPIOIS  0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE  0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC  0x41C

#define PL061_GPIO_NR	8

#ifdef CONFIG_PM
struct pl061_context_save_regs {
	u8 gpio_data;
	u8 gpio_dir;
	u8 gpio_is;
	u8 gpio_ibe;
	u8 gpio_iev;
	u8 gpio_ie;
};
#endif

struct pl061_gpio {
	spinlock_t		lock;

	void __iomem		*base;
	struct irq_domain	*domain;
	struct gpio_chip	gc;

#ifdef CONFIG_PM
	struct pl061_context_save_regs csave_regs;
#endif
};

static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir &= ~(1 << offset);
	writeb(gpiodir, chip->base + GPIODIR);
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir |= 1 << offset;
	writeb(gpiodir, chip->base + GPIODIR);

	/*
	 * gpio value is set again, because pl061 doesn't allow to set value of
	 * a gpio pin before configuring it in OUT mode.
	 */
	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	return !!readb(chip->base + (1 << (offset + 2)));
}

static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
}

static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	return irq_create_mapping(chip->domain, offset);
}

static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u8 gpiois, gpioibe, gpioiev;

	if (offset < 0 || offset >= PL061_GPIO_NR)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);

	gpioiev = readb(chip->base + GPIOIEV);

	gpiois = readb(chip->base + GPIOIS);
	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		gpiois |= 1 << offset;
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			gpioiev |= 1 << offset;
		else
			gpioiev &= ~(1 << offset);
	} else
		gpiois &= ~(1 << offset);
	writeb(gpiois, chip->base + GPIOIS);

	gpioibe = readb(chip->base + GPIOIBE);
	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
		gpioibe |= 1 << offset;
	else {
		gpioibe &= ~(1 << offset);
		if (trigger & IRQ_TYPE_EDGE_RISING)
			gpioiev |= 1 << offset;
		else if (trigger & IRQ_TYPE_EDGE_FALLING)
			gpioiev &= ~(1 << offset);
	}
	writeb(gpioibe, chip->base + GPIOIBE);

	writeb(gpioiev, chip->base + GPIOIEV);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readb(chip->base + GPIOMIS);
	writeb(pending, chip->base + GPIOIC);
	if (pending) {
		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
			generic_handle_irq(pl061_to_irq(&chip->gc, offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void pl061_irq_mask(struct irq_data *d)
{
	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	spin_lock(&chip->lock);
	gpioie = readb(chip->base + GPIOIE) & ~mask;
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock(&chip->lock);
}

static void pl061_irq_unmask(struct irq_data *d)
{
	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	spin_lock(&chip->lock);
	gpioie = readb(chip->base + GPIOIE) | mask;
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock(&chip->lock);
}

static struct irq_chip pl061_irqchip = {
	.name		= "pl061 gpio",
	.irq_mask	= pl061_irq_mask,
	.irq_unmask	= pl061_irq_unmask,
	.irq_set_type	= pl061_irq_type,
};

static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
			 irq_hw_number_t hw)
{
	struct pl061_gpio *chip = d->host_data;

	irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
				      "pl061");
	irq_set_chip_data(virq, chip);
	irq_set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static const struct irq_domain_ops pl061_domain_ops = {
	.map	= pl061_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
	struct device *dev = &adev->dev;
	struct pl061_platform_data *pdata = dev->platform_data;
	struct pl061_gpio *chip;
	int ret, irq, i, irq_base;

	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	if (pdata) {
		chip->gc.base = pdata->gpio_base;
		irq_base = pdata->irq_base;
		if (irq_base <= 0)
			return -ENODEV;
	} else {
		chip->gc.base = -1;
		irq_base = 0;
	}

	if (!devm_request_mem_region(dev, adev->res.start,
				     resource_size(&adev->res), "pl061"))
		return -EBUSY;

	chip->base = devm_ioremap(dev, adev->res.start,
				  resource_size(&adev->res));
	if (!chip->base)
		return -ENOMEM;

	chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
					     irq_base, &pl061_domain_ops, chip);
	if (!chip->domain)
		return -ENODEV;

	spin_lock_init(&chip->lock);

	chip->gc.direction_input = pl061_direction_input;
	chip->gc.direction_output = pl061_direction_output;
	chip->gc.get = pl061_get_value;
	chip->gc.set = pl061_set_value;
	chip->gc.to_irq = pl061_to_irq;
	chip->gc.ngpio = PL061_GPIO_NR;
	chip->gc.label = dev_name(dev);
	chip->gc.dev = dev;
	chip->gc.owner = THIS_MODULE;

	ret = gpiochip_add(&chip->gc);
	if (ret)
		return ret;

	/*
	 * irq_chip support
	 */
	writeb(0, chip->base + GPIOIE); /* disable irqs */
	irq = adev->irq[0];
	if (irq < 0)
		return -ENODEV;

	irq_set_chained_handler(irq, pl061_irq_handler);
	irq_set_handler_data(irq, chip);

	for (i = 0; i < PL061_GPIO_NR; i++) {
		if (pdata) {
			if (pdata->directions & (1 << i))
				pl061_direction_output(&chip->gc, i,
						pdata->values & (1 << i));
			else
				pl061_direction_input(&chip->gc, i);
		}
	}

	amba_set_drvdata(adev, chip);

	return 0;
}

#ifdef CONFIG_PM
static int pl061_suspend(struct device *dev)
{
	struct pl061_gpio *chip = dev_get_drvdata(dev);
	int offset;

	chip->csave_regs.gpio_data = 0;
	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (chip->csave_regs.gpio_dir & (1 << offset))
			chip->csave_regs.gpio_data |=
				pl061_get_value(&chip->gc, offset) << offset;
	}

	return 0;
}

static int pl061_resume(struct device *dev)
{
	struct pl061_gpio *chip = dev_get_drvdata(dev);
	int offset;

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (chip->csave_regs.gpio_dir & (1 << offset))
			pl061_direction_output(&chip->gc, offset,
					chip->csave_regs.gpio_data &
					(1 << offset));
		else
			pl061_direction_input(&chip->gc, offset);
	}

	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);

	return 0;
}

static const struct dev_pm_ops pl061_dev_pm_ops = {
	.suspend = pl061_suspend,
	.resume = pl061_resume,
	.freeze = pl061_suspend,
	.restore = pl061_resume,
};
#endif

static struct amba_id pl061_ids[] = {
	{
		.id	= 0x00041061,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

MODULE_DEVICE_TABLE(amba, pl061_ids);

static struct amba_driver pl061_gpio_driver = {
	.drv = {
		.name	= "pl061_gpio",
#ifdef CONFIG_PM
		.pm	= &pl061_dev_pm_ops,
#endif
	},
	.id_table	= pl061_ids,
	.probe		= pl061_probe,
};

static int __init pl061_gpio_init(void)
{
	return amba_driver_register(&pl061_gpio_driver);
}
module_init(pl061_gpio_init);

MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
MODULE_DESCRIPTION("PL061 GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1e9c2859	1	/*
c103de24	2	* Copyright (C) 2008, 2009 Provigent Ltd.
1e9c2859 BS	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
	9	*
	10	* Data sheet: ARM DDI 0190B, September 2000
	11	*/
	12	#include <linux/spinlock.h>
	13	#include <linux/errno.h>
	14	#include <linux/module.h>
1e9c2859 BS	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
f1f70479	18	#include <linux/irqdomain.h>
1e9c2859 BS	19	#include <linux/bitops.h>
	20	#include <linux/workqueue.h>
	21	#include <linux/gpio.h>
	22	#include <linux/device.h>
	23	#include <linux/amba/bus.h>
	24	#include <linux/amba/pl061.h>
5a0e3ad6	25	#include <linux/slab.h>
e198a8de	26	#include <linux/pm.h>
dece904d	27	#include <asm/mach/irq.h>
1e9c2859 BS	28
	29	#define GPIODIR 0x400
	30	#define GPIOIS 0x404
	31	#define GPIOIBE 0x408
	32	#define GPIOIEV 0x40C
	33	#define GPIOIE 0x410
	34	#define GPIORIS 0x414
	35	#define GPIOMIS 0x418
	36	#define GPIOIC 0x41C
	37
	38	#define PL061_GPIO_NR 8
	39
e198a8de DS	40	#ifdef CONFIG_PM
	41	struct pl061_context_save_regs {
	42	u8 gpio_data;
	43	u8 gpio_dir;
	44	u8 gpio_is;
	45	u8 gpio_ibe;
	46	u8 gpio_iev;
	47	u8 gpio_ie;
	48	};
	49	#endif
1e9c2859	50
1e9c2859	51	struct pl061_gpio {
835c192f	52	spinlock_t lock;
1e9c2859 BS	53
1e9c2859 BS	54	void __iomem *base;
f1f70479	55	struct irq_domain *domain;
1e9c2859	56	struct gpio_chip gc;
e198a8de DS	57
	58	#ifdef CONFIG_PM
	59	struct pl061_context_save_regs csave_regs;
	60	#endif
1e9c2859 BS	61	};
	62
	63	static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
	64	{
	65	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	66	unsigned long flags;
	67	unsigned char gpiodir;
	68
	69	if (offset >= gc->ngpio)
	70	return -EINVAL;
	71
	72	spin_lock_irqsave(&chip->lock, flags);
	73	gpiodir = readb(chip->base + GPIODIR);
	74	gpiodir &= ~(1 << offset);
	75	writeb(gpiodir, chip->base + GPIODIR);
	76	spin_unlock_irqrestore(&chip->lock, flags);
	77
	78	return 0;
	79	}
	80
	81	static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
	82	int value)
	83	{
	84	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	85	unsigned long flags;
	86	unsigned char gpiodir;
	87
	88	if (offset >= gc->ngpio)
	89	return -EINVAL;
	90
	91	spin_lock_irqsave(&chip->lock, flags);
	92	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	93	gpiodir = readb(chip->base + GPIODIR);
	94	gpiodir \|= 1 << offset;
	95	writeb(gpiodir, chip->base + GPIODIR);
64b997c5 VK	96
	97	/*
	98	* gpio value is set again, because pl061 doesn't allow to set value of
	99	* a gpio pin before configuring it in OUT mode.
	100	*/
	101	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
1e9c2859 BS	102	spin_unlock_irqrestore(&chip->lock, flags);
	103
	104	return 0;
	105	}
	106
	107	static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
	108	{
	109	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	110
	111	return !!readb(chip->base + (1 << (offset + 2)));
	112	}
	113
	114	static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
	115	{
	116	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	117
	118	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	119	}
	120
50efacf6 BS	121	static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
	122	{
	123	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	124
f1f70479	125	return irq_create_mapping(chip->domain, offset);
50efacf6 BS	126	}
50efacf6 BS	127
b2221869	128	static int pl061_irq_type(struct irq_data *d, unsigned trigger)
1e9c2859	129	{
f1f70479 HZ	130	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
f1f70479 HZ	131	int offset = irqd_to_hwirq(d);
1e9c2859 BS	132	unsigned long flags;
	133	u8 gpiois, gpioibe, gpioiev;
	134
c1cc9b97	135	if (offset < 0 \|\| offset >= PL061_GPIO_NR)
1e9c2859 BS	136	return -EINVAL;
1e9c2859 BS	137
f1f70479	138	spin_lock_irqsave(&chip->lock, flags);
1e9c2859 BS	139
	140	gpioiev = readb(chip->base + GPIOIEV);
	141
	142	gpiois = readb(chip->base + GPIOIS);
	143	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
	144	gpiois \|= 1 << offset;
	145	if (trigger & IRQ_TYPE_LEVEL_HIGH)
	146	gpioiev \|= 1 << offset;
	147	else
	148	gpioiev &= ~(1 << offset);
	149	} else
	150	gpiois &= ~(1 << offset);
	151	writeb(gpiois, chip->base + GPIOIS);
	152
	153	gpioibe = readb(chip->base + GPIOIBE);
	154	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
	155	gpioibe \|= 1 << offset;
	156	else {
	157	gpioibe &= ~(1 << offset);
	158	if (trigger & IRQ_TYPE_EDGE_RISING)
	159	gpioiev \|= 1 << offset;
db7e1bc4	160	else if (trigger & IRQ_TYPE_EDGE_FALLING)
1e9c2859 BS	161	gpioiev &= ~(1 << offset);
	162	}
	163	writeb(gpioibe, chip->base + GPIOIBE);
	164
	165	writeb(gpioiev, chip->base + GPIOIEV);
	166
f1f70479	167	spin_unlock_irqrestore(&chip->lock, flags);
1e9c2859 BS	168
	169	return 0;
	170	}
	171
1e9c2859 BS	172	static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
1e9c2859 BS	173	{
2de0dbc5 RH	174	unsigned long pending;
	175	int offset;
	176	struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
dece904d	177	struct irq_chip *irqchip = irq_desc_get_chip(desc);
1e9c2859	178
dece904d	179	chained_irq_enter(irqchip, desc);
1e9c2859	180
2de0dbc5 RH	181	pending = readb(chip->base + GPIOMIS);
	182	writeb(pending, chip->base + GPIOIC);
	183	if (pending) {
984b3f57	184	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
50efacf6	185	generic_handle_irq(pl061_to_irq(&chip->gc, offset));
1e9c2859	186	}
2de0dbc5	187
dece904d	188	chained_irq_exit(irqchip, desc);
1e9c2859 BS	189	}
1e9c2859 BS	190
f1f70479	191	static void pl061_irq_mask(struct irq_data *d)
3ab52475	192	{
f1f70479 HZ	193	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	194	u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
	195	u8 gpioie;
	196
	197	spin_lock(&chip->lock);
	198	gpioie = readb(chip->base + GPIOIE) & ~mask;
	199	writeb(gpioie, chip->base + GPIOIE);
	200	spin_unlock(&chip->lock);
	201	}
3ab52475	202
f1f70479 HZ	203	static void pl061_irq_unmask(struct irq_data *d)
	204	{
	205	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	206	u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
	207	u8 gpioie;
	208
	209	spin_lock(&chip->lock);
	210	gpioie = readb(chip->base + GPIOIE) \| mask;
	211	writeb(gpioie, chip->base + GPIOIE);
	212	spin_unlock(&chip->lock);
	213	}
	214
	215	static struct irq_chip pl061_irqchip = {
	216	.name = "pl061 gpio",
	217	.irq_mask = pl061_irq_mask,
	218	.irq_unmask = pl061_irq_unmask,
	219	.irq_set_type = pl061_irq_type,
	220	};
	221
	222	static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
	223	irq_hw_number_t hw)
	224	{
	225	struct pl061_gpio *chip = d->host_data;
3ab52475	226
f1f70479 HZ	227	irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
	228	"pl061");
	229	irq_set_chip_data(virq, chip);
	230	irq_set_irq_type(virq, IRQ_TYPE_NONE);
3ab52475	231
f1f70479	232	return 0;
1e9c2859 BS	233	}
1e9c2859 BS	234
f1f70479 HZ	235	static const struct irq_domain_ops pl061_domain_ops = {
	236	.map = pl061_irq_map,
	237	.xlate = irq_domain_xlate_twocell,
	238	};
	239
8944df72	240	static int pl061_probe(struct amba_device adev, const struct amba_id id)
1e9c2859	241	{
8944df72 TK	242	struct device *dev = &adev->dev;
8944df72 TK	243	struct pl061_platform_data *pdata = dev->platform_data;
1e9c2859	244	struct pl061_gpio *chip;
f1f70479	245	int ret, irq, i, irq_base;
1e9c2859	246
8944df72	247	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
1e9c2859 BS	248	if (chip == NULL)
	249	return -ENOMEM;
	250
76c05c8a RH	251	if (pdata) {
76c05c8a RH	252	chip->gc.base = pdata->gpio_base;
f1f70479 HZ	253	irq_base = pdata->irq_base;
	254	if (irq_base <= 0)
	255	return -ENODEV;
	256	} else {
76c05c8a	257	chip->gc.base = -1;
f1f70479 HZ	258	irq_base = 0;
f1f70479 HZ	259	}
76c05c8a	260
8944df72	261	if (!devm_request_mem_region(dev, adev->res.start,
f1f70479	262	resource_size(&adev->res), "pl061"))
8944df72	263	return -EBUSY;
1e9c2859	264
8944df72	265	chip->base = devm_ioremap(dev, adev->res.start,
f1f70479 HZ	266	resource_size(&adev->res));
f1f70479 HZ	267	if (!chip->base)
8944df72	268	return -ENOMEM;
1e9c2859	269
f1f70479 HZ	270	chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
	271	irq_base, &pl061_domain_ops, chip);
	272	if (!chip->domain)
	273	return -ENODEV;
	274
1e9c2859	275	spin_lock_init(&chip->lock);
1e9c2859 BS	276
	277	chip->gc.direction_input = pl061_direction_input;
	278	chip->gc.direction_output = pl061_direction_output;
	279	chip->gc.get = pl061_get_value;
	280	chip->gc.set = pl061_set_value;
50efacf6	281	chip->gc.to_irq = pl061_to_irq;
1e9c2859	282	chip->gc.ngpio = PL061_GPIO_NR;
8944df72 TK	283	chip->gc.label = dev_name(dev);
8944df72 TK	284	chip->gc.dev = dev;
1e9c2859 BS	285	chip->gc.owner = THIS_MODULE;
1e9c2859 BS	286
1e9c2859 BS	287	ret = gpiochip_add(&chip->gc);
1e9c2859 BS	288	if (ret)
8944df72	289	return ret;
1e9c2859 BS	290
	291	/*
	292	* irq_chip support
	293	*/
1e9c2859	294	writeb(0, chip->base + GPIOIE); /* disable irqs */
8944df72 TK	295	irq = adev->irq[0];
	296	if (irq < 0)
	297	return -ENODEV;
	298
b51804bc	299	irq_set_chained_handler(irq, pl061_irq_handler);
2de0dbc5	300	irq_set_handler_data(irq, chip);
1e9c2859 BS	301
1e9c2859 BS	302	for (i = 0; i < PL061_GPIO_NR; i++) {
76c05c8a RH	303	if (pdata) {
	304	if (pdata->directions & (1 << i))
	305	pl061_direction_output(&chip->gc, i,
	306	pdata->values & (1 << i));
	307	else
	308	pl061_direction_input(&chip->gc, i);
	309	}
1e9c2859 BS	310	}
1e9c2859 BS	311
8944df72	312	amba_set_drvdata(adev, chip);
e198a8de	313
1e9c2859	314	return 0;
1e9c2859 BS	315	}
1e9c2859 BS	316
e198a8de DS	317	#ifdef CONFIG_PM
	318	static int pl061_suspend(struct device *dev)
	319	{
	320	struct pl061_gpio *chip = dev_get_drvdata(dev);
	321	int offset;
	322
	323	chip->csave_regs.gpio_data = 0;
	324	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
	325	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
	326	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
	327	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
	328	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
	329
	330	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
	331	if (chip->csave_regs.gpio_dir & (1 << offset))
	332	chip->csave_regs.gpio_data \|=
	333	pl061_get_value(&chip->gc, offset) << offset;
	334	}
	335
	336	return 0;
	337	}
	338
	339	static int pl061_resume(struct device *dev)
	340	{
	341	struct pl061_gpio *chip = dev_get_drvdata(dev);
	342	int offset;
	343
	344	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
	345	if (chip->csave_regs.gpio_dir & (1 << offset))
	346	pl061_direction_output(&chip->gc, offset,
	347	chip->csave_regs.gpio_data &
	348	(1 << offset));
	349	else
	350	pl061_direction_input(&chip->gc, offset);
	351	}
	352
	353	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
	354	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
	355	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
	356	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
	357
	358	return 0;
	359	}
	360
6e33aced VK	361	static const struct dev_pm_ops pl061_dev_pm_ops = {
	362	.suspend = pl061_suspend,
	363	.resume = pl061_resume,
	364	.freeze = pl061_suspend,
	365	.restore = pl061_resume,
	366	};
e198a8de DS	367	#endif
e198a8de DS	368
2c39c9e1	369	static struct amba_id pl061_ids[] = {
1e9c2859 BS	370	{
	371	.id = 0x00041061,
	372	.mask = 0x000fffff,
	373	},
	374	{ 0, 0 },
	375	};
	376
955b678c DM	377	MODULE_DEVICE_TABLE(amba, pl061_ids);
955b678c DM	378
1e9c2859 BS	379	static struct amba_driver pl061_gpio_driver = {
	380	.drv = {
	381	.name = "pl061_gpio",
e198a8de DS	382	#ifdef CONFIG_PM
	383	.pm = &pl061_dev_pm_ops,
	384	#endif
1e9c2859 BS	385	},
	386	.id_table = pl061_ids,
	387	.probe = pl061_probe,
	388	};
	389
	390	static int __init pl061_gpio_init(void)
	391	{
	392	return amba_driver_register(&pl061_gpio_driver);
	393	}
5985d76c	394	module_init(pl061_gpio_init);
1e9c2859 BS	395
	396	MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
	397	MODULE_DESCRIPTION("PL061 GPIO driver");
	398	MODULE_LICENSE("GPL");