[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-pmic-eic-sprd.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2018 Spreadtrum Communications Inc.
 * Copyright (C) 2018 Linaro Ltd.
 */

#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

/* EIC registers definition */
#define SPRD_PMIC_EIC_DATA		0x0
#define SPRD_PMIC_EIC_DMSK		0x4
#define SPRD_PMIC_EIC_IEV		0x14
#define SPRD_PMIC_EIC_IE		0x18
#define SPRD_PMIC_EIC_RIS		0x1c
#define SPRD_PMIC_EIC_MIS		0x20
#define SPRD_PMIC_EIC_IC		0x24
#define SPRD_PMIC_EIC_TRIG		0x28
#define SPRD_PMIC_EIC_CTRL0		0x40

/*
 * The PMIC EIC controller only has one bank, and each bank now can contain
 * 16 EICs.
 */
#define SPRD_PMIC_EIC_PER_BANK_NR	16
#define SPRD_PMIC_EIC_NR		SPRD_PMIC_EIC_PER_BANK_NR
#define SPRD_PMIC_EIC_DATA_MASK		GENMASK(15, 0)
#define SPRD_PMIC_EIC_BIT(x)		((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
#define SPRD_PMIC_EIC_DBNC_MASK		GENMASK(11, 0)

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum {
	REG_IEV,
	REG_IE,
	REG_TRIG,
	CACHE_NR_REGS
};

/**
 * struct sprd_pmic_eic - PMIC EIC controller
 * @chip: the gpio_chip structure.
 * @intc: the irq_chip structure.
 * @map:  the regmap from the parent device.
 * @offset: the EIC controller's offset address of the PMIC.
 * @reg: the array to cache the EIC registers.
 * @buslock: for bus lock/sync and unlock.
 * @irq: the interrupt number of the PMIC EIC conteroller.
 */
struct sprd_pmic_eic {
	struct gpio_chip chip;
	struct irq_chip intc;
	struct regmap *map;
	u32 offset;
	u8 reg[CACHE_NR_REGS];
	struct mutex buslock;
	int irq;
};

static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset,
				 u16 reg, unsigned int val)
{
	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
	u32 shift = SPRD_PMIC_EIC_BIT(offset);

	regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,
			   BIT(shift), val << shift);
}

static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset,
			      u16 reg)
{
	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
	u32 value;
	int ret;

	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
	if (ret)
		return ret;

	return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset)));
}

static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset)
{
	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1);
	return 0;
}

static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset)
{
	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0);
}

static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset)
{
	return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA);
}

static int sprd_pmic_eic_direction_input(struct gpio_chip *chip,
					 unsigned int offset)
{
	/* EICs are always input, nothing need to do here. */
	return 0;
}

static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
			      int value)
{
	/* EICs are always input, nothing need to do here. */
}

static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip,
				      unsigned int offset,
				      unsigned int debounce)
{
	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
	u32 reg, value;
	int ret;

	reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4;
	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
	if (ret)
		return ret;

	value &= ~SPRD_PMIC_EIC_DBNC_MASK;
	value |= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK;
	return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);
}

static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset,
				    unsigned long config)
{
	unsigned long param = pinconf_to_config_param(config);
	u32 arg = pinconf_to_config_argument(config);

	if (param == PIN_CONFIG_INPUT_DEBOUNCE)
		return sprd_pmic_eic_set_debounce(chip, offset, arg);

	return -ENOTSUPP;
}

static void sprd_pmic_eic_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);

	pmic_eic->reg[REG_IE] = 0;
	pmic_eic->reg[REG_TRIG] = 0;
}

static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);

	pmic_eic->reg[REG_IE] = 1;
	pmic_eic->reg[REG_TRIG] = 1;
}

static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
				      unsigned int flow_type)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);

	switch (flow_type) {
	case IRQ_TYPE_LEVEL_HIGH:
		pmic_eic->reg[REG_IEV] = 1;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		pmic_eic->reg[REG_IEV] = 0;
		break;
	case IRQ_TYPE_EDGE_RISING:
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_EDGE_BOTH:
		/*
		 * Will set the trigger level according to current EIC level
		 * in irq_bus_sync_unlock() interface, so here nothing to do.
		 */
		break;
	default:
		return -ENOTSUPP;
	}

	return 0;
}

static void sprd_pmic_eic_bus_lock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);

	mutex_lock(&pmic_eic->buslock);
}

static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
	u32 trigger = irqd_get_trigger_type(data);
	u32 offset = irqd_to_hwirq(data);
	int state;

	/* Set irq type */
	if (trigger & IRQ_TYPE_EDGE_BOTH) {
		state = sprd_pmic_eic_get(chip, offset);
		if (state)
			sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
		else
			sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
	} else {
		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
				     pmic_eic->reg[REG_IEV]);
	}

	/* Set irq unmask */
	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
			     pmic_eic->reg[REG_IE]);
	/* Generate trigger start pulse for debounce EIC */
	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
			     pmic_eic->reg[REG_TRIG]);

	mutex_unlock(&pmic_eic->buslock);
}

static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip,
					 unsigned int irq, unsigned int offset)
{
	u32 trigger = irq_get_trigger_type(irq);
	int state, post_state;

	if (!(trigger & IRQ_TYPE_EDGE_BOTH))
		return;

	state = sprd_pmic_eic_get(chip, offset);
retry:
	if (state)
		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
	else
		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);

	post_state = sprd_pmic_eic_get(chip, offset);
	if (state != post_state) {
		dev_warn(chip->parent, "PMIC EIC level was changed.\n");
		state = post_state;
		goto retry;
	}

	/* Set irq unmask */
	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1);
	/* Generate trigger start pulse for debounce EIC */
	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1);
}

static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data)
{
	struct sprd_pmic_eic *pmic_eic = data;
	struct gpio_chip *chip = &pmic_eic->chip;
	unsigned long status;
	u32 n, girq, val;
	int ret;

	ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,
			  &val);
	if (ret)
		return IRQ_RETVAL(ret);

	status = val & SPRD_PMIC_EIC_DATA_MASK;

	for_each_set_bit(n, &status, chip->ngpio) {
		/* Clear the interrupt */
		sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1);

		girq = irq_find_mapping(chip->irq.domain, n);
		handle_nested_irq(girq);

		/*
		 * The PMIC EIC can only support level trigger, so we can
		 * toggle the level trigger to emulate the edge trigger.
		 */
		sprd_pmic_eic_toggle_trigger(chip, girq, n);
	}

	return IRQ_HANDLED;
}

static int sprd_pmic_eic_probe(struct platform_device *pdev)
{
	struct gpio_irq_chip *irq;
	struct sprd_pmic_eic *pmic_eic;
	int ret;

	pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);
	if (!pmic_eic)
		return -ENOMEM;

	mutex_init(&pmic_eic->buslock);

	pmic_eic->irq = platform_get_irq(pdev, 0);
	if (pmic_eic->irq < 0)
		return pmic_eic->irq;

	pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);
	if (!pmic_eic->map)
		return -ENODEV;

	ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);
	if (ret) {
		dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");
		return ret;
	}

	ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,
					sprd_pmic_eic_irq_handler,
					IRQF_ONESHOT | IRQF_NO_SUSPEND,
					dev_name(&pdev->dev), pmic_eic);
	if (ret) {
		dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");
		return ret;
	}

	pmic_eic->chip.label = dev_name(&pdev->dev);
	pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;
	pmic_eic->chip.base = -1;
	pmic_eic->chip.parent = &pdev->dev;
	pmic_eic->chip.of_node = pdev->dev.of_node;
	pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;
	pmic_eic->chip.request = sprd_pmic_eic_request;
	pmic_eic->chip.free = sprd_pmic_eic_free;
	pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
	pmic_eic->chip.set = sprd_pmic_eic_set;
	pmic_eic->chip.get = sprd_pmic_eic_get;

	pmic_eic->intc.name = dev_name(&pdev->dev);
	pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
	pmic_eic->intc.irq_unmask = sprd_pmic_eic_irq_unmask;
	pmic_eic->intc.irq_set_type = sprd_pmic_eic_irq_set_type;
	pmic_eic->intc.irq_bus_lock = sprd_pmic_eic_bus_lock;
	pmic_eic->intc.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock;
	pmic_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;

	irq = &pmic_eic->chip.irq;
	irq->chip = &pmic_eic->intc;
	irq->threaded = true;

	ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);
	if (ret < 0) {
		dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, pmic_eic);
	return 0;
}

static const struct of_device_id sprd_pmic_eic_of_match[] = {
	{ .compatible = "sprd,sc2731-eic", },
	{ /* end of list */ }
};
MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match);

static struct platform_driver sprd_pmic_eic_driver = {
	.probe = sprd_pmic_eic_probe,
	.driver = {
		.name = "sprd-pmic-eic",
		.of_match_table	= sprd_pmic_eic_of_match,
	},
};

module_platform_driver(sprd_pmic_eic_driver);

MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
348f3cde BW	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2018 Spreadtrum Communications Inc.
	4	* Copyright (C) 2018 Linaro Ltd.
	5	*/
	6
	7	#include <linux/gpio/driver.h>
	8	#include <linux/interrupt.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of_device.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/regmap.h>
	14
	15	/* EIC registers definition */
	16	#define SPRD_PMIC_EIC_DATA 0x0
	17	#define SPRD_PMIC_EIC_DMSK 0x4
	18	#define SPRD_PMIC_EIC_IEV 0x14
	19	#define SPRD_PMIC_EIC_IE 0x18
	20	#define SPRD_PMIC_EIC_RIS 0x1c
	21	#define SPRD_PMIC_EIC_MIS 0x20
	22	#define SPRD_PMIC_EIC_IC 0x24
	23	#define SPRD_PMIC_EIC_TRIG 0x28
	24	#define SPRD_PMIC_EIC_CTRL0 0x40
	25
	26	/*
	27	* The PMIC EIC controller only has one bank, and each bank now can contain
	28	* 16 EICs.
	29	*/
	30	#define SPRD_PMIC_EIC_PER_BANK_NR 16
	31	#define SPRD_PMIC_EIC_NR SPRD_PMIC_EIC_PER_BANK_NR
	32	#define SPRD_PMIC_EIC_DATA_MASK GENMASK(15, 0)
	33	#define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
	34	#define SPRD_PMIC_EIC_DBNC_MASK GENMASK(11, 0)
	35
	36	/*
	37	* These registers are modified under the irq bus lock and cached to avoid
	38	* unnecessary writes in bus_sync_unlock.
	39	*/
	40	enum {
	41	REG_IEV,
	42	REG_IE,
	43	REG_TRIG,
	44	CACHE_NR_REGS
	45	};
	46
	47	/**
	48	* struct sprd_pmic_eic - PMIC EIC controller
	49	* @chip: the gpio_chip structure.
	50	* @intc: the irq_chip structure.
3cd7f770	51	* @map: the regmap from the parent device.
348f3cde BW	52	* @offset: the EIC controller's offset address of the PMIC.
	53	* @reg: the array to cache the EIC registers.
	54	* @buslock: for bus lock/sync and unlock.
	55	* @irq: the interrupt number of the PMIC EIC conteroller.
	56	*/
	57	struct sprd_pmic_eic {
	58	struct gpio_chip chip;
	59	struct irq_chip intc;
	60	struct regmap *map;
	61	u32 offset;
	62	u8 reg[CACHE_NR_REGS];
	63	struct mutex buslock;
	64	int irq;
	65	};
	66
	67	static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset,
	68	u16 reg, unsigned int val)
	69	{
	70	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
	71	u32 shift = SPRD_PMIC_EIC_BIT(offset);
	72
	73	regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,
	74	BIT(shift), val << shift);
	75	}
	76
	77	static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset,
	78	u16 reg)
	79	{
	80	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
	81	u32 value;
	82	int ret;
	83
	84	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
	85	if (ret)
	86	return ret;
	87
	88	return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset)));
	89	}
	90
	91	static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset)
	92	{
	93	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1);
	94	return 0;
	95	}
	96
	97	static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset)
	98	{
	99	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0);
	100	}
	101
	102	static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset)
	103	{
	104	return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA);
	105	}
	106
	107	static int sprd_pmic_eic_direction_input(struct gpio_chip *chip,
	108	unsigned int offset)
	109	{
	110	/* EICs are always input, nothing need to do here. */
	111	return 0;
	112	}
	113
	114	static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
	115	int value)
116	{
117	/* EICs are always input, nothing need to do here. */
118	}
119
120	static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip,
121	unsigned int offset,
122	unsigned int debounce)
123	{
124	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
125	u32 reg, value;
126	int ret;
127
128	reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4;
129	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
130	if (ret)
131	return ret;
132
133	value &= ~SPRD_PMIC_EIC_DBNC_MASK;
134	value \|= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK;
135	return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);
136	}
137
138	static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset,
139	unsigned long config)
140	{
141	unsigned long param = pinconf_to_config_param(config);
142	u32 arg = pinconf_to_config_argument(config);
143
144	if (param == PIN_CONFIG_INPUT_DEBOUNCE)
145	return sprd_pmic_eic_set_debounce(chip, offset, arg);
146
147	return -ENOTSUPP;
148	}
149
150	static void sprd_pmic_eic_irq_mask(struct irq_data *data)
151	{
152	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
153	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
154
155	pmic_eic->reg[REG_IE] = 0;
156	pmic_eic->reg[REG_TRIG] = 0;
157	}
158
159	static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
160	{
161	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
162	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
163
164	pmic_eic->reg[REG_IE] = 1;
165	pmic_eic->reg[REG_TRIG] = 1;
166	}
167
168	static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
169	unsigned int flow_type)
170	{
171	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
172	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
173
174	switch (flow_type) {
175	case IRQ_TYPE_LEVEL_HIGH:
176	pmic_eic->reg[REG_IEV] = 1;
177	break;
178	case IRQ_TYPE_LEVEL_LOW:
179	pmic_eic->reg[REG_IEV] = 0;
180	break;
92da8b9d BW	181	case IRQ_TYPE_EDGE_RISING:
	182	case IRQ_TYPE_EDGE_FALLING:
	183	case IRQ_TYPE_EDGE_BOTH:
	184	/*
	185	* Will set the trigger level according to current EIC level
	186	* in irq_bus_sync_unlock() interface, so here nothing to do.
	187	*/
	188	break;
348f3cde BW	189	default:
	190	return -ENOTSUPP;
	191	}
	192
	193	return 0;
	194	}
	195
	196	static void sprd_pmic_eic_bus_lock(struct irq_data *data)
	197	{
	198	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	199	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
	200
	201	mutex_lock(&pmic_eic->buslock);
	202	}
	203
	204	static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
	205	{
	206	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	207	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
92da8b9d	208	u32 trigger = irqd_get_trigger_type(data);
348f3cde	209	u32 offset = irqd_to_hwirq(data);
92da8b9d	210	int state;
348f3cde BW	211
348f3cde BW	212	/* Set irq type */
92da8b9d BW	213	if (trigger & IRQ_TYPE_EDGE_BOTH) {
	214	state = sprd_pmic_eic_get(chip, offset);
	215	if (state)
	216	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
	217	else
	218	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
	219	} else {
	220	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
	221	pmic_eic->reg[REG_IEV]);
	222	}
	223
348f3cde BW	224	/* Set irq unmask */
	225	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
	226	pmic_eic->reg[REG_IE]);
	227	/* Generate trigger start pulse for debounce EIC */
	228	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
	229	pmic_eic->reg[REG_TRIG]);
	230
	231	mutex_unlock(&pmic_eic->buslock);
	232	}
	233
92da8b9d BW	234	static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip,
	235	unsigned int irq, unsigned int offset)
	236	{
	237	u32 trigger = irq_get_trigger_type(irq);
	238	int state, post_state;
	239
	240	if (!(trigger & IRQ_TYPE_EDGE_BOTH))
	241	return;
	242
	243	state = sprd_pmic_eic_get(chip, offset);
	244	retry:
	245	if (state)
	246	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
	247	else
	248	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
	249
	250	post_state = sprd_pmic_eic_get(chip, offset);
	251	if (state != post_state) {
	252	dev_warn(chip->parent, "PMIC EIC level was changed.\n");
	253	state = post_state;
	254	goto retry;
	255	}
	256
	257	/* Set irq unmask */
	258	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1);
	259	/* Generate trigger start pulse for debounce EIC */
	260	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1);
	261	}
	262
348f3cde BW	263	static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data)
	264	{
	265	struct sprd_pmic_eic *pmic_eic = data;
	266	struct gpio_chip *chip = &pmic_eic->chip;
	267	unsigned long status;
	268	u32 n, girq, val;
	269	int ret;
	270
	271	ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,
	272	&val);
	273	if (ret)
	274	return IRQ_RETVAL(ret);
	275
	276	status = val & SPRD_PMIC_EIC_DATA_MASK;
	277
	278	for_each_set_bit(n, &status, chip->ngpio) {
	279	/* Clear the interrupt */
	280	sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1);
	281
	282	girq = irq_find_mapping(chip->irq.domain, n);
	283	handle_nested_irq(girq);
92da8b9d BW	284
	285	/*
	286	* The PMIC EIC can only support level trigger, so we can
	287	* toggle the level trigger to emulate the edge trigger.
	288	*/
	289	sprd_pmic_eic_toggle_trigger(chip, girq, n);
348f3cde BW	290	}
	291
	292	return IRQ_HANDLED;
	293	}
	294
	295	static int sprd_pmic_eic_probe(struct platform_device *pdev)
	296	{
	297	struct gpio_irq_chip *irq;
	298	struct sprd_pmic_eic *pmic_eic;
	299	int ret;
	300
	301	pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);
	302	if (!pmic_eic)
	303	return -ENOMEM;
	304
	305	mutex_init(&pmic_eic->buslock);
	306
	307	pmic_eic->irq = platform_get_irq(pdev, 0);
15bddb7d	308	if (pmic_eic->irq < 0)
348f3cde	309	return pmic_eic->irq;
348f3cde BW	310
	311	pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);
	312	if (!pmic_eic->map)
	313	return -ENODEV;
	314
	315	ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);
	316	if (ret) {
	317	dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");
	318	return ret;
	319	}
	320
	321	ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,
	322	sprd_pmic_eic_irq_handler,
348f3cde BW	323	IRQF_ONESHOT \| IRQF_NO_SUSPEND,
	324	dev_name(&pdev->dev), pmic_eic);
	325	if (ret) {
	326	dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");
	327	return ret;
	328	}
	329
	330	pmic_eic->chip.label = dev_name(&pdev->dev);
	331	pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;
	332	pmic_eic->chip.base = -1;
	333	pmic_eic->chip.parent = &pdev->dev;
	334	pmic_eic->chip.of_node = pdev->dev.of_node;
	335	pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;
	336	pmic_eic->chip.request = sprd_pmic_eic_request;
	337	pmic_eic->chip.free = sprd_pmic_eic_free;
	338	pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
	339	pmic_eic->chip.set = sprd_pmic_eic_set;
	340	pmic_eic->chip.get = sprd_pmic_eic_get;
	341
	342	pmic_eic->intc.name = dev_name(&pdev->dev);
	343	pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
	344	pmic_eic->intc.irq_unmask = sprd_pmic_eic_irq_unmask;
	345	pmic_eic->intc.irq_set_type = sprd_pmic_eic_irq_set_type;
	346	pmic_eic->intc.irq_bus_lock = sprd_pmic_eic_bus_lock;
	347	pmic_eic->intc.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock;
	348	pmic_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
	349
	350	irq = &pmic_eic->chip.irq;
	351	irq->chip = &pmic_eic->intc;
	352	irq->threaded = true;
	353
	354	ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);
	355	if (ret < 0) {
	356	dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
	357	return ret;
	358	}
	359
	360	platform_set_drvdata(pdev, pmic_eic);
	361	return 0;
	362	}
	363
	364	static const struct of_device_id sprd_pmic_eic_of_match[] = {
567cbf07	365	{ .compatible = "sprd,sc2731-eic", },
348f3cde BW	366	{ /* end of list */ }
	367	};
	368	MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match);
	369
	370	static struct platform_driver sprd_pmic_eic_driver = {
	371	.probe = sprd_pmic_eic_probe,
	372	.driver = {
	373	.name = "sprd-pmic-eic",
	374	.of_match_table = sprd_pmic_eic_of_match,
	375	},
	376	};
	377
	378	module_platform_driver(sprd_pmic_eic_driver);
	379
	380	MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver");
	381	MODULE_LICENSE("GPL v2");