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Commit | Line | Data |
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1c44f5f1 | 1 | /* |
38f539a6 | 2 | * linux/arch/arm/plat-pxa/gpio.c |
1c44f5f1 PZ |
3 | * |
4 | * Generic PXA GPIO handling | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
7a4d5079 | 14 | #include <linux/module.h> |
389eda15 HZ |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
2f8163ba | 17 | #include <linux/gpio.h> |
157d2644 | 18 | #include <linux/gpio-pxa.h> |
1c44f5f1 | 19 | #include <linux/init.h> |
e3630db1 | 20 | #include <linux/irq.h> |
7a4d5079 | 21 | #include <linux/irqdomain.h> |
de88cbb7 | 22 | #include <linux/irqchip/chained_irq.h> |
fced80c7 | 23 | #include <linux/io.h> |
7a4d5079 HZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_device.h> | |
157d2644 | 26 | #include <linux/platform_device.h> |
2eaa03b5 | 27 | #include <linux/syscore_ops.h> |
4aa78264 | 28 | #include <linux/slab.h> |
1c44f5f1 | 29 | |
feefe73f RH |
30 | #include <mach/irqs.h> |
31 | ||
157d2644 HZ |
32 | /* |
33 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with | |
34 | * one set of registers. The register offsets are organized below: | |
35 | * | |
36 | * GPLR GPDR GPSR GPCR GRER GFER GEDR | |
37 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 | |
38 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C | |
39 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 | |
40 | * | |
41 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 | |
42 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C | |
43 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 | |
44 | * | |
45 | * NOTE: | |
46 | * BANK 3 is only available on PXA27x and later processors. | |
47 | * BANK 4 and 5 are only available on PXA935 | |
48 | */ | |
49 | ||
50 | #define GPLR_OFFSET 0x00 | |
51 | #define GPDR_OFFSET 0x0C | |
52 | #define GPSR_OFFSET 0x18 | |
53 | #define GPCR_OFFSET 0x24 | |
54 | #define GRER_OFFSET 0x30 | |
55 | #define GFER_OFFSET 0x3C | |
56 | #define GEDR_OFFSET 0x48 | |
57 | #define GAFR_OFFSET 0x54 | |
be24168f | 58 | #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ |
157d2644 HZ |
59 | |
60 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) | |
1c44f5f1 | 61 | |
3b8e285c | 62 | int pxa_last_gpio; |
9450be76 | 63 | static int irq_base; |
3b8e285c | 64 | |
7a4d5079 HZ |
65 | #ifdef CONFIG_OF |
66 | static struct irq_domain *domain; | |
72121572 | 67 | static struct device_node *pxa_gpio_of_node; |
7a4d5079 HZ |
68 | #endif |
69 | ||
1c44f5f1 PZ |
70 | struct pxa_gpio_chip { |
71 | struct gpio_chip chip; | |
0807da59 EM |
72 | void __iomem *regbase; |
73 | char label[10]; | |
74 | ||
75 | unsigned long irq_mask; | |
76 | unsigned long irq_edge_rise; | |
77 | unsigned long irq_edge_fall; | |
b95ace54 | 78 | int (*set_wake)(unsigned int gpio, unsigned int on); |
0807da59 EM |
79 | |
80 | #ifdef CONFIG_PM | |
81 | unsigned long saved_gplr; | |
82 | unsigned long saved_gpdr; | |
83 | unsigned long saved_grer; | |
84 | unsigned long saved_gfer; | |
85 | #endif | |
1c44f5f1 PZ |
86 | }; |
87 | ||
2cab0292 | 88 | enum pxa_gpio_type { |
4929f5a8 HZ |
89 | PXA25X_GPIO = 0, |
90 | PXA26X_GPIO, | |
91 | PXA27X_GPIO, | |
92 | PXA3XX_GPIO, | |
93 | PXA93X_GPIO, | |
94 | MMP_GPIO = 0x10, | |
2cab0292 HZ |
95 | MMP2_GPIO, |
96 | }; | |
97 | ||
98 | struct pxa_gpio_id { | |
99 | enum pxa_gpio_type type; | |
100 | int gpio_nums; | |
4929f5a8 HZ |
101 | }; |
102 | ||
0807da59 EM |
103 | static DEFINE_SPINLOCK(gpio_lock); |
104 | static struct pxa_gpio_chip *pxa_gpio_chips; | |
2cab0292 | 105 | static enum pxa_gpio_type gpio_type; |
157d2644 | 106 | static void __iomem *gpio_reg_base; |
0807da59 | 107 | |
2cab0292 HZ |
108 | static struct pxa_gpio_id pxa25x_id = { |
109 | .type = PXA25X_GPIO, | |
110 | .gpio_nums = 85, | |
111 | }; | |
112 | ||
113 | static struct pxa_gpio_id pxa26x_id = { | |
114 | .type = PXA26X_GPIO, | |
115 | .gpio_nums = 90, | |
116 | }; | |
117 | ||
118 | static struct pxa_gpio_id pxa27x_id = { | |
119 | .type = PXA27X_GPIO, | |
120 | .gpio_nums = 121, | |
121 | }; | |
122 | ||
123 | static struct pxa_gpio_id pxa3xx_id = { | |
124 | .type = PXA3XX_GPIO, | |
125 | .gpio_nums = 128, | |
126 | }; | |
127 | ||
128 | static struct pxa_gpio_id pxa93x_id = { | |
129 | .type = PXA93X_GPIO, | |
130 | .gpio_nums = 192, | |
131 | }; | |
132 | ||
133 | static struct pxa_gpio_id mmp_id = { | |
134 | .type = MMP_GPIO, | |
135 | .gpio_nums = 128, | |
136 | }; | |
137 | ||
138 | static struct pxa_gpio_id mmp2_id = { | |
139 | .type = MMP2_GPIO, | |
140 | .gpio_nums = 192, | |
141 | }; | |
142 | ||
0807da59 EM |
143 | #define for_each_gpio_chip(i, c) \ |
144 | for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) | |
145 | ||
146 | static inline void __iomem *gpio_chip_base(struct gpio_chip *c) | |
147 | { | |
148 | return container_of(c, struct pxa_gpio_chip, chip)->regbase; | |
149 | } | |
150 | ||
a065685d | 151 | static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) |
0807da59 EM |
152 | { |
153 | return &pxa_gpio_chips[gpio_to_bank(gpio)]; | |
154 | } | |
155 | ||
4929f5a8 HZ |
156 | static inline int gpio_is_pxa_type(int type) |
157 | { | |
158 | return (type & MMP_GPIO) == 0; | |
159 | } | |
160 | ||
161 | static inline int gpio_is_mmp_type(int type) | |
162 | { | |
163 | return (type & MMP_GPIO) != 0; | |
164 | } | |
165 | ||
157d2644 HZ |
166 | /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, |
167 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | |
168 | */ | |
169 | static inline int __gpio_is_inverted(int gpio) | |
170 | { | |
171 | if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) | |
172 | return 1; | |
173 | return 0; | |
174 | } | |
175 | ||
176 | /* | |
177 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | |
178 | * function of a GPIO, and GPDRx cannot be altered once configured. It | |
179 | * is attributed as "occupied" here (I know this terminology isn't | |
180 | * accurate, you are welcome to propose a better one :-) | |
181 | */ | |
182 | static inline int __gpio_is_occupied(unsigned gpio) | |
183 | { | |
184 | struct pxa_gpio_chip *pxachip; | |
185 | void __iomem *base; | |
186 | unsigned long gafr = 0, gpdr = 0; | |
187 | int ret, af = 0, dir = 0; | |
188 | ||
189 | pxachip = gpio_to_pxachip(gpio); | |
190 | base = gpio_chip_base(&pxachip->chip); | |
191 | gpdr = readl_relaxed(base + GPDR_OFFSET); | |
192 | ||
193 | switch (gpio_type) { | |
194 | case PXA25X_GPIO: | |
195 | case PXA26X_GPIO: | |
196 | case PXA27X_GPIO: | |
197 | gafr = readl_relaxed(base + GAFR_OFFSET); | |
198 | af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; | |
199 | dir = gpdr & GPIO_bit(gpio); | |
200 | ||
201 | if (__gpio_is_inverted(gpio)) | |
202 | ret = (af != 1) || (dir == 0); | |
203 | else | |
204 | ret = (af != 0) || (dir != 0); | |
205 | break; | |
206 | default: | |
207 | ret = gpdr & GPIO_bit(gpio); | |
208 | break; | |
209 | } | |
210 | return ret; | |
211 | } | |
212 | ||
4929f5a8 HZ |
213 | static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
214 | { | |
9450be76 | 215 | return chip->base + offset + irq_base; |
4929f5a8 HZ |
216 | } |
217 | ||
218 | int pxa_irq_to_gpio(int irq) | |
219 | { | |
9450be76 | 220 | return irq - irq_base; |
4929f5a8 HZ |
221 | } |
222 | ||
1c44f5f1 PZ |
223 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
224 | { | |
0807da59 EM |
225 | void __iomem *base = gpio_chip_base(chip); |
226 | uint32_t value, mask = 1 << offset; | |
227 | unsigned long flags; | |
228 | ||
229 | spin_lock_irqsave(&gpio_lock, flags); | |
230 | ||
df664d20 | 231 | value = readl_relaxed(base + GPDR_OFFSET); |
067455aa EM |
232 | if (__gpio_is_inverted(chip->base + offset)) |
233 | value |= mask; | |
234 | else | |
235 | value &= ~mask; | |
df664d20 | 236 | writel_relaxed(value, base + GPDR_OFFSET); |
1c44f5f1 | 237 | |
0807da59 | 238 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
239 | return 0; |
240 | } | |
241 | ||
242 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | |
0807da59 | 243 | unsigned offset, int value) |
1c44f5f1 | 244 | { |
0807da59 EM |
245 | void __iomem *base = gpio_chip_base(chip); |
246 | uint32_t tmp, mask = 1 << offset; | |
247 | unsigned long flags; | |
248 | ||
df664d20 | 249 | writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
0807da59 EM |
250 | |
251 | spin_lock_irqsave(&gpio_lock, flags); | |
252 | ||
df664d20 | 253 | tmp = readl_relaxed(base + GPDR_OFFSET); |
067455aa EM |
254 | if (__gpio_is_inverted(chip->base + offset)) |
255 | tmp &= ~mask; | |
256 | else | |
257 | tmp |= mask; | |
df664d20 | 258 | writel_relaxed(tmp, base + GPDR_OFFSET); |
1c44f5f1 | 259 | |
0807da59 | 260 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
261 | return 0; |
262 | } | |
263 | ||
1c44f5f1 PZ |
264 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
265 | { | |
df664d20 | 266 | return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); |
1c44f5f1 PZ |
267 | } |
268 | ||
1c44f5f1 PZ |
269 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
270 | { | |
df664d20 | 271 | writel_relaxed(1 << offset, gpio_chip_base(chip) + |
0807da59 | 272 | (value ? GPSR_OFFSET : GPCR_OFFSET)); |
1c44f5f1 PZ |
273 | } |
274 | ||
72121572 DM |
275 | #ifdef CONFIG_OF_GPIO |
276 | static int pxa_gpio_of_xlate(struct gpio_chip *gc, | |
277 | const struct of_phandle_args *gpiospec, | |
278 | u32 *flags) | |
279 | { | |
280 | if (gpiospec->args[0] > pxa_last_gpio) | |
281 | return -EINVAL; | |
282 | ||
283 | if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip) | |
284 | return -EINVAL; | |
285 | ||
286 | if (flags) | |
287 | *flags = gpiospec->args[1]; | |
288 | ||
289 | return gpiospec->args[0] % 32; | |
290 | } | |
291 | #endif | |
292 | ||
3836309d | 293 | static int pxa_init_gpio_chip(int gpio_end, |
b95ace54 | 294 | int (*set_wake)(unsigned int, unsigned int)) |
a58fbcd8 | 295 | { |
0807da59 EM |
296 | int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; |
297 | struct pxa_gpio_chip *chips; | |
a58fbcd8 | 298 | |
4aa78264 | 299 | chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL); |
0807da59 EM |
300 | if (chips == NULL) { |
301 | pr_err("%s: failed to allocate GPIO chips\n", __func__); | |
302 | return -ENOMEM; | |
a58fbcd8 | 303 | } |
a58fbcd8 | 304 | |
0807da59 EM |
305 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { |
306 | struct gpio_chip *c = &chips[i].chip; | |
e3630db1 | 307 | |
0807da59 | 308 | sprintf(chips[i].label, "gpio-%d", i); |
157d2644 | 309 | chips[i].regbase = gpio_reg_base + BANK_OFF(i); |
b95ace54 | 310 | chips[i].set_wake = set_wake; |
0807da59 EM |
311 | |
312 | c->base = gpio; | |
313 | c->label = chips[i].label; | |
314 | ||
315 | c->direction_input = pxa_gpio_direction_input; | |
316 | c->direction_output = pxa_gpio_direction_output; | |
317 | c->get = pxa_gpio_get; | |
318 | c->set = pxa_gpio_set; | |
4929f5a8 | 319 | c->to_irq = pxa_gpio_to_irq; |
72121572 DM |
320 | #ifdef CONFIG_OF_GPIO |
321 | c->of_node = pxa_gpio_of_node; | |
322 | c->of_xlate = pxa_gpio_of_xlate; | |
323 | c->of_gpio_n_cells = 2; | |
324 | #endif | |
0807da59 EM |
325 | |
326 | /* number of GPIOs on last bank may be less than 32 */ | |
327 | c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; | |
328 | gpiochip_add(c); | |
329 | } | |
330 | pxa_gpio_chips = chips; | |
331 | return 0; | |
332 | } | |
e3630db1 | 333 | |
a8f6faeb EM |
334 | /* Update only those GRERx and GFERx edge detection register bits if those |
335 | * bits are set in c->irq_mask | |
336 | */ | |
337 | static inline void update_edge_detect(struct pxa_gpio_chip *c) | |
338 | { | |
339 | uint32_t grer, gfer; | |
340 | ||
df664d20 HZ |
341 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; |
342 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; | |
a8f6faeb EM |
343 | grer |= c->irq_edge_rise & c->irq_mask; |
344 | gfer |= c->irq_edge_fall & c->irq_mask; | |
df664d20 HZ |
345 | writel_relaxed(grer, c->regbase + GRER_OFFSET); |
346 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); | |
a8f6faeb EM |
347 | } |
348 | ||
a3f4c927 | 349 | static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) |
e3630db1 | 350 | { |
0807da59 | 351 | struct pxa_gpio_chip *c; |
4929f5a8 | 352 | int gpio = pxa_irq_to_gpio(d->irq); |
0807da59 | 353 | unsigned long gpdr, mask = GPIO_bit(gpio); |
e3630db1 | 354 | |
a065685d | 355 | c = gpio_to_pxachip(gpio); |
e3630db1 | 356 | |
357 | if (type == IRQ_TYPE_PROBE) { | |
358 | /* Don't mess with enabled GPIOs using preconfigured edges or | |
359 | * GPIOs set to alternate function or to output during probe | |
360 | */ | |
0807da59 | 361 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) |
e3630db1 | 362 | return 0; |
689c04a3 | 363 | |
364 | if (__gpio_is_occupied(gpio)) | |
e3630db1 | 365 | return 0; |
689c04a3 | 366 | |
e3630db1 | 367 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
368 | } | |
369 | ||
df664d20 | 370 | gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
0807da59 | 371 | |
067455aa | 372 | if (__gpio_is_inverted(gpio)) |
df664d20 | 373 | writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); |
067455aa | 374 | else |
df664d20 | 375 | writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); |
e3630db1 | 376 | |
377 | if (type & IRQ_TYPE_EDGE_RISING) | |
0807da59 | 378 | c->irq_edge_rise |= mask; |
e3630db1 | 379 | else |
0807da59 | 380 | c->irq_edge_rise &= ~mask; |
e3630db1 | 381 | |
382 | if (type & IRQ_TYPE_EDGE_FALLING) | |
0807da59 | 383 | c->irq_edge_fall |= mask; |
e3630db1 | 384 | else |
0807da59 | 385 | c->irq_edge_fall &= ~mask; |
e3630db1 | 386 | |
a8f6faeb | 387 | update_edge_detect(c); |
e3630db1 | 388 | |
a3f4c927 | 389 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, |
e3630db1 | 390 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
391 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | |
392 | return 0; | |
393 | } | |
394 | ||
e3630db1 | 395 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) |
396 | { | |
0807da59 EM |
397 | struct pxa_gpio_chip *c; |
398 | int loop, gpio, gpio_base, n; | |
399 | unsigned long gedr; | |
0d2ee5d7 CX |
400 | struct irq_chip *chip = irq_desc_get_chip(desc); |
401 | ||
402 | chained_irq_enter(chip, desc); | |
e3630db1 | 403 | |
404 | do { | |
e3630db1 | 405 | loop = 0; |
0807da59 EM |
406 | for_each_gpio_chip(gpio, c) { |
407 | gpio_base = c->chip.base; | |
408 | ||
df664d20 | 409 | gedr = readl_relaxed(c->regbase + GEDR_OFFSET); |
0807da59 | 410 | gedr = gedr & c->irq_mask; |
df664d20 | 411 | writel_relaxed(gedr, c->regbase + GEDR_OFFSET); |
e3630db1 | 412 | |
d724f1c9 | 413 | for_each_set_bit(n, &gedr, BITS_PER_LONG) { |
0807da59 | 414 | loop = 1; |
e3630db1 | 415 | |
0807da59 | 416 | generic_handle_irq(gpio_to_irq(gpio_base + n)); |
0807da59 | 417 | } |
e3630db1 | 418 | } |
419 | } while (loop); | |
0d2ee5d7 CX |
420 | |
421 | chained_irq_exit(chip, desc); | |
e3630db1 | 422 | } |
423 | ||
a3f4c927 | 424 | static void pxa_ack_muxed_gpio(struct irq_data *d) |
e3630db1 | 425 | { |
4929f5a8 | 426 | int gpio = pxa_irq_to_gpio(d->irq); |
a065685d | 427 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
0807da59 | 428 | |
df664d20 | 429 | writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); |
e3630db1 | 430 | } |
431 | ||
a3f4c927 | 432 | static void pxa_mask_muxed_gpio(struct irq_data *d) |
e3630db1 | 433 | { |
4929f5a8 | 434 | int gpio = pxa_irq_to_gpio(d->irq); |
a065685d | 435 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
0807da59 EM |
436 | uint32_t grer, gfer; |
437 | ||
438 | c->irq_mask &= ~GPIO_bit(gpio); | |
439 | ||
df664d20 HZ |
440 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); |
441 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); | |
442 | writel_relaxed(grer, c->regbase + GRER_OFFSET); | |
443 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); | |
e3630db1 | 444 | } |
445 | ||
b95ace54 RJ |
446 | static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) |
447 | { | |
448 | int gpio = pxa_irq_to_gpio(d->irq); | |
449 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); | |
450 | ||
451 | if (c->set_wake) | |
452 | return c->set_wake(gpio, on); | |
453 | else | |
454 | return 0; | |
455 | } | |
456 | ||
a3f4c927 | 457 | static void pxa_unmask_muxed_gpio(struct irq_data *d) |
e3630db1 | 458 | { |
4929f5a8 | 459 | int gpio = pxa_irq_to_gpio(d->irq); |
a065685d | 460 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
0807da59 EM |
461 | |
462 | c->irq_mask |= GPIO_bit(gpio); | |
a8f6faeb | 463 | update_edge_detect(c); |
e3630db1 | 464 | } |
465 | ||
466 | static struct irq_chip pxa_muxed_gpio_chip = { | |
467 | .name = "GPIO", | |
a3f4c927 LB |
468 | .irq_ack = pxa_ack_muxed_gpio, |
469 | .irq_mask = pxa_mask_muxed_gpio, | |
470 | .irq_unmask = pxa_unmask_muxed_gpio, | |
471 | .irq_set_type = pxa_gpio_irq_type, | |
b95ace54 | 472 | .irq_set_wake = pxa_gpio_set_wake, |
e3630db1 | 473 | }; |
474 | ||
2cab0292 | 475 | static int pxa_gpio_nums(struct platform_device *pdev) |
478e223c | 476 | { |
2cab0292 HZ |
477 | const struct platform_device_id *id = platform_get_device_id(pdev); |
478 | struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; | |
478e223c HZ |
479 | int count = 0; |
480 | ||
2cab0292 HZ |
481 | switch (pxa_id->type) { |
482 | case PXA25X_GPIO: | |
483 | case PXA26X_GPIO: | |
484 | case PXA27X_GPIO: | |
485 | case PXA3XX_GPIO: | |
486 | case PXA93X_GPIO: | |
487 | case MMP_GPIO: | |
488 | case MMP2_GPIO: | |
489 | gpio_type = pxa_id->type; | |
490 | count = pxa_id->gpio_nums - 1; | |
491 | break; | |
492 | default: | |
493 | count = -EINVAL; | |
494 | break; | |
478e223c | 495 | } |
478e223c HZ |
496 | return count; |
497 | } | |
498 | ||
f43e04ec | 499 | #ifdef CONFIG_OF |
7a4d5079 | 500 | static struct of_device_id pxa_gpio_dt_ids[] = { |
f8731174 HZ |
501 | { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, |
502 | { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, | |
503 | { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, | |
504 | { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, | |
505 | { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, | |
506 | { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, | |
507 | { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, | |
7a4d5079 HZ |
508 | {} |
509 | }; | |
510 | ||
511 | static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, | |
512 | irq_hw_number_t hw) | |
513 | { | |
514 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
515 | handle_edge_irq); | |
516 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
517 | return 0; | |
518 | } | |
519 | ||
520 | const struct irq_domain_ops pxa_irq_domain_ops = { | |
521 | .map = pxa_irq_domain_map, | |
72121572 | 522 | .xlate = irq_domain_xlate_twocell, |
7a4d5079 HZ |
523 | }; |
524 | ||
3836309d | 525 | static int pxa_gpio_probe_dt(struct platform_device *pdev) |
7a4d5079 | 526 | { |
5dbb7c63 DM |
527 | int ret = 0, nr_gpios; |
528 | struct device_node *np = pdev->dev.of_node; | |
7a4d5079 HZ |
529 | const struct of_device_id *of_id = |
530 | of_match_device(pxa_gpio_dt_ids, &pdev->dev); | |
f8731174 | 531 | const struct pxa_gpio_id *gpio_id; |
7a4d5079 | 532 | |
f8731174 | 533 | if (!of_id || !of_id->data) { |
7a4d5079 HZ |
534 | dev_err(&pdev->dev, "Failed to find gpio controller\n"); |
535 | return -EFAULT; | |
536 | } | |
f8731174 HZ |
537 | gpio_id = of_id->data; |
538 | gpio_type = gpio_id->type; | |
7a4d5079 | 539 | |
f8731174 | 540 | nr_gpios = gpio_id->gpio_nums; |
7a4d5079 HZ |
541 | pxa_last_gpio = nr_gpios - 1; |
542 | ||
543 | irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); | |
544 | if (irq_base < 0) { | |
545 | dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); | |
5dbb7c63 | 546 | ret = irq_base; |
7a4d5079 HZ |
547 | goto err; |
548 | } | |
549 | domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0, | |
550 | &pxa_irq_domain_ops, NULL); | |
72121572 | 551 | pxa_gpio_of_node = np; |
7a4d5079 HZ |
552 | return 0; |
553 | err: | |
554 | iounmap(gpio_reg_base); | |
555 | return ret; | |
556 | } | |
557 | #else | |
558 | #define pxa_gpio_probe_dt(pdev) (-1) | |
559 | #endif | |
560 | ||
3836309d | 561 | static int pxa_gpio_probe(struct platform_device *pdev) |
e3630db1 | 562 | { |
0807da59 | 563 | struct pxa_gpio_chip *c; |
157d2644 | 564 | struct resource *res; |
389eda15 | 565 | struct clk *clk; |
b95ace54 | 566 | struct pxa_gpio_platform_data *info; |
7a4d5079 | 567 | int gpio, irq, ret, use_of = 0; |
157d2644 | 568 | int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; |
e3630db1 | 569 | |
b8f649f1 HZ |
570 | info = dev_get_platdata(&pdev->dev); |
571 | if (info) { | |
572 | irq_base = info->irq_base; | |
573 | if (irq_base <= 0) | |
574 | return -EINVAL; | |
2cab0292 | 575 | pxa_last_gpio = pxa_gpio_nums(pdev); |
9450be76 | 576 | } else { |
b8f649f1 | 577 | irq_base = 0; |
7a4d5079 | 578 | use_of = 1; |
b8f649f1 HZ |
579 | ret = pxa_gpio_probe_dt(pdev); |
580 | if (ret < 0) | |
581 | return -EINVAL; | |
9450be76 DM |
582 | } |
583 | ||
478e223c | 584 | if (!pxa_last_gpio) |
157d2644 HZ |
585 | return -EINVAL; |
586 | ||
587 | irq0 = platform_get_irq_byname(pdev, "gpio0"); | |
588 | irq1 = platform_get_irq_byname(pdev, "gpio1"); | |
589 | irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); | |
590 | if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) | |
591 | || (irq_mux <= 0)) | |
592 | return -EINVAL; | |
593 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
594 | if (!res) | |
595 | return -EINVAL; | |
596 | gpio_reg_base = ioremap(res->start, resource_size(res)); | |
597 | if (!gpio_reg_base) | |
598 | return -EINVAL; | |
599 | ||
600 | if (irq0 > 0) | |
601 | gpio_offset = 2; | |
e3630db1 | 602 | |
389eda15 HZ |
603 | clk = clk_get(&pdev->dev, NULL); |
604 | if (IS_ERR(clk)) { | |
605 | dev_err(&pdev->dev, "Error %ld to get gpio clock\n", | |
606 | PTR_ERR(clk)); | |
607 | iounmap(gpio_reg_base); | |
608 | return PTR_ERR(clk); | |
609 | } | |
6ab49f42 | 610 | ret = clk_prepare_enable(clk); |
389eda15 HZ |
611 | if (ret) { |
612 | clk_put(clk); | |
613 | iounmap(gpio_reg_base); | |
614 | return ret; | |
615 | } | |
389eda15 | 616 | |
0807da59 | 617 | /* Initialize GPIO chips */ |
b95ace54 | 618 | pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL); |
0807da59 | 619 | |
e3630db1 | 620 | /* clear all GPIO edge detects */ |
0807da59 | 621 | for_each_gpio_chip(gpio, c) { |
df664d20 HZ |
622 | writel_relaxed(0, c->regbase + GFER_OFFSET); |
623 | writel_relaxed(0, c->regbase + GRER_OFFSET); | |
e37f4af7 | 624 | writel_relaxed(~0, c->regbase + GEDR_OFFSET); |
be24168f HZ |
625 | /* unmask GPIO edge detect for AP side */ |
626 | if (gpio_is_mmp_type(gpio_type)) | |
627 | writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); | |
e3630db1 | 628 | } |
629 | ||
7a4d5079 | 630 | if (!use_of) { |
87c49e20 | 631 | #ifdef CONFIG_ARCH_PXA |
7a4d5079 HZ |
632 | irq = gpio_to_irq(0); |
633 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
634 | handle_edge_irq); | |
635 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
636 | irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler); | |
87c49e20 | 637 | |
7a4d5079 | 638 | irq = gpio_to_irq(1); |
f38c02f3 TG |
639 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
640 | handle_edge_irq); | |
e3630db1 | 641 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
7a4d5079 HZ |
642 | irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler); |
643 | #endif | |
644 | ||
645 | for (irq = gpio_to_irq(gpio_offset); | |
646 | irq <= gpio_to_irq(pxa_last_gpio); irq++) { | |
647 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
648 | handle_edge_irq); | |
649 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
650 | } | |
e3630db1 | 651 | } |
652 | ||
157d2644 HZ |
653 | irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler); |
654 | return 0; | |
655 | } | |
656 | ||
2cab0292 HZ |
657 | static const struct platform_device_id gpio_id_table[] = { |
658 | { "pxa25x-gpio", (unsigned long)&pxa25x_id }, | |
659 | { "pxa26x-gpio", (unsigned long)&pxa26x_id }, | |
660 | { "pxa27x-gpio", (unsigned long)&pxa27x_id }, | |
661 | { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, | |
662 | { "pxa93x-gpio", (unsigned long)&pxa93x_id }, | |
663 | { "mmp-gpio", (unsigned long)&mmp_id }, | |
664 | { "mmp2-gpio", (unsigned long)&mmp2_id }, | |
665 | { }, | |
666 | }; | |
667 | ||
157d2644 HZ |
668 | static struct platform_driver pxa_gpio_driver = { |
669 | .probe = pxa_gpio_probe, | |
670 | .driver = { | |
671 | .name = "pxa-gpio", | |
f43e04ec | 672 | .of_match_table = of_match_ptr(pxa_gpio_dt_ids), |
157d2644 | 673 | }, |
2cab0292 | 674 | .id_table = gpio_id_table, |
157d2644 | 675 | }; |
cf3fa17c LW |
676 | |
677 | static int __init pxa_gpio_init(void) | |
678 | { | |
679 | return platform_driver_register(&pxa_gpio_driver); | |
680 | } | |
681 | postcore_initcall(pxa_gpio_init); | |
663707c1 | 682 | |
683 | #ifdef CONFIG_PM | |
2eaa03b5 | 684 | static int pxa_gpio_suspend(void) |
663707c1 | 685 | { |
0807da59 EM |
686 | struct pxa_gpio_chip *c; |
687 | int gpio; | |
663707c1 | 688 | |
0807da59 | 689 | for_each_gpio_chip(gpio, c) { |
df664d20 HZ |
690 | c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); |
691 | c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); | |
692 | c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); | |
693 | c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); | |
663707c1 | 694 | |
695 | /* Clear GPIO transition detect bits */ | |
df664d20 | 696 | writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); |
663707c1 | 697 | } |
698 | return 0; | |
699 | } | |
700 | ||
2eaa03b5 | 701 | static void pxa_gpio_resume(void) |
663707c1 | 702 | { |
0807da59 EM |
703 | struct pxa_gpio_chip *c; |
704 | int gpio; | |
663707c1 | 705 | |
0807da59 | 706 | for_each_gpio_chip(gpio, c) { |
663707c1 | 707 | /* restore level with set/clear */ |
e37f4af7 | 708 | writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); |
df664d20 | 709 | writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); |
663707c1 | 710 | |
df664d20 HZ |
711 | writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); |
712 | writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); | |
713 | writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); | |
663707c1 | 714 | } |
663707c1 | 715 | } |
716 | #else | |
717 | #define pxa_gpio_suspend NULL | |
718 | #define pxa_gpio_resume NULL | |
719 | #endif | |
720 | ||
2eaa03b5 | 721 | struct syscore_ops pxa_gpio_syscore_ops = { |
663707c1 | 722 | .suspend = pxa_gpio_suspend, |
723 | .resume = pxa_gpio_resume, | |
724 | }; | |
157d2644 HZ |
725 | |
726 | static int __init pxa_gpio_sysinit(void) | |
727 | { | |
728 | register_syscore_ops(&pxa_gpio_syscore_ops); | |
729 | return 0; | |
730 | } | |
731 | postcore_initcall(pxa_gpio_sysinit); |