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Commit | Line | Data |
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1c44f5f1 | 1 | /* |
38f539a6 | 2 | * linux/arch/arm/plat-pxa/gpio.c |
1c44f5f1 PZ |
3 | * |
4 | * Generic PXA GPIO handling | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
7a4d5079 | 14 | #include <linux/module.h> |
389eda15 HZ |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
2f8163ba | 17 | #include <linux/gpio.h> |
157d2644 | 18 | #include <linux/gpio-pxa.h> |
1c44f5f1 | 19 | #include <linux/init.h> |
ae4f4cfd | 20 | #include <linux/interrupt.h> |
e3630db1 | 21 | #include <linux/irq.h> |
7a4d5079 | 22 | #include <linux/irqdomain.h> |
de88cbb7 | 23 | #include <linux/irqchip/chained_irq.h> |
fced80c7 | 24 | #include <linux/io.h> |
7a4d5079 HZ |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
a770d946 | 27 | #include <linux/pinctrl/consumer.h> |
157d2644 | 28 | #include <linux/platform_device.h> |
2eaa03b5 | 29 | #include <linux/syscore_ops.h> |
4aa78264 | 30 | #include <linux/slab.h> |
1c44f5f1 | 31 | |
157d2644 HZ |
32 | /* |
33 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with | |
34 | * one set of registers. The register offsets are organized below: | |
35 | * | |
36 | * GPLR GPDR GPSR GPCR GRER GFER GEDR | |
37 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 | |
38 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C | |
39 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 | |
40 | * | |
41 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 | |
42 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C | |
43 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 | |
44 | * | |
684bba2f RH |
45 | * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248 |
46 | * | |
157d2644 HZ |
47 | * NOTE: |
48 | * BANK 3 is only available on PXA27x and later processors. | |
684bba2f RH |
49 | * BANK 4 and 5 are only available on PXA935, PXA1928 |
50 | * BANK 6 is only available on PXA1928 | |
157d2644 HZ |
51 | */ |
52 | ||
53 | #define GPLR_OFFSET 0x00 | |
54 | #define GPDR_OFFSET 0x0C | |
55 | #define GPSR_OFFSET 0x18 | |
56 | #define GPCR_OFFSET 0x24 | |
57 | #define GRER_OFFSET 0x30 | |
58 | #define GFER_OFFSET 0x3C | |
59 | #define GEDR_OFFSET 0x48 | |
60 | #define GAFR_OFFSET 0x54 | |
be24168f | 61 | #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ |
157d2644 | 62 | |
1e970b7d | 63 | #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2) |
1c44f5f1 | 64 | |
3b8e285c | 65 | int pxa_last_gpio; |
9450be76 | 66 | static int irq_base; |
3b8e285c | 67 | |
fc0589ca | 68 | struct pxa_gpio_bank { |
0807da59 | 69 | void __iomem *regbase; |
0807da59 EM |
70 | unsigned long irq_mask; |
71 | unsigned long irq_edge_rise; | |
72 | unsigned long irq_edge_fall; | |
73 | ||
74 | #ifdef CONFIG_PM | |
75 | unsigned long saved_gplr; | |
76 | unsigned long saved_gpdr; | |
77 | unsigned long saved_grer; | |
78 | unsigned long saved_gfer; | |
79 | #endif | |
1c44f5f1 PZ |
80 | }; |
81 | ||
fc0589ca RJ |
82 | struct pxa_gpio_chip { |
83 | struct device *dev; | |
84 | struct gpio_chip chip; | |
85 | struct pxa_gpio_bank *banks; | |
384ca3c6 | 86 | struct irq_domain *irqdomain; |
fc0589ca RJ |
87 | |
88 | int irq0; | |
89 | int irq1; | |
90 | int (*set_wake)(unsigned int gpio, unsigned int on); | |
91 | }; | |
92 | ||
2cab0292 | 93 | enum pxa_gpio_type { |
4929f5a8 HZ |
94 | PXA25X_GPIO = 0, |
95 | PXA26X_GPIO, | |
96 | PXA27X_GPIO, | |
97 | PXA3XX_GPIO, | |
98 | PXA93X_GPIO, | |
99 | MMP_GPIO = 0x10, | |
2cab0292 | 100 | MMP2_GPIO, |
684bba2f | 101 | PXA1928_GPIO, |
2cab0292 HZ |
102 | }; |
103 | ||
104 | struct pxa_gpio_id { | |
105 | enum pxa_gpio_type type; | |
106 | int gpio_nums; | |
4929f5a8 HZ |
107 | }; |
108 | ||
0807da59 | 109 | static DEFINE_SPINLOCK(gpio_lock); |
fc0589ca | 110 | static struct pxa_gpio_chip *pxa_gpio_chip; |
2cab0292 | 111 | static enum pxa_gpio_type gpio_type; |
0807da59 | 112 | |
2cab0292 HZ |
113 | static struct pxa_gpio_id pxa25x_id = { |
114 | .type = PXA25X_GPIO, | |
115 | .gpio_nums = 85, | |
116 | }; | |
117 | ||
118 | static struct pxa_gpio_id pxa26x_id = { | |
119 | .type = PXA26X_GPIO, | |
120 | .gpio_nums = 90, | |
121 | }; | |
122 | ||
123 | static struct pxa_gpio_id pxa27x_id = { | |
124 | .type = PXA27X_GPIO, | |
125 | .gpio_nums = 121, | |
126 | }; | |
127 | ||
128 | static struct pxa_gpio_id pxa3xx_id = { | |
129 | .type = PXA3XX_GPIO, | |
130 | .gpio_nums = 128, | |
131 | }; | |
132 | ||
133 | static struct pxa_gpio_id pxa93x_id = { | |
134 | .type = PXA93X_GPIO, | |
135 | .gpio_nums = 192, | |
136 | }; | |
137 | ||
138 | static struct pxa_gpio_id mmp_id = { | |
139 | .type = MMP_GPIO, | |
140 | .gpio_nums = 128, | |
141 | }; | |
142 | ||
143 | static struct pxa_gpio_id mmp2_id = { | |
144 | .type = MMP2_GPIO, | |
145 | .gpio_nums = 192, | |
146 | }; | |
147 | ||
684bba2f RH |
148 | static struct pxa_gpio_id pxa1928_id = { |
149 | .type = PXA1928_GPIO, | |
150 | .gpio_nums = 224, | |
151 | }; | |
152 | ||
fc0589ca RJ |
153 | #define for_each_gpio_bank(i, b, pc) \ |
154 | for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++) | |
0807da59 | 155 | |
fc0589ca | 156 | static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c) |
0807da59 | 157 | { |
81d0c31d | 158 | struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c); |
fc0589ca RJ |
159 | |
160 | return pxa_chip; | |
0807da59 | 161 | } |
81d0c31d | 162 | |
fc0589ca RJ |
163 | static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio) |
164 | { | |
81d0c31d LW |
165 | struct pxa_gpio_chip *p = gpiochip_get_data(c); |
166 | struct pxa_gpio_bank *bank = p->banks + (gpio / 32); | |
0807da59 | 167 | |
fc0589ca RJ |
168 | return bank->regbase; |
169 | } | |
170 | ||
171 | static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c, | |
172 | unsigned gpio) | |
0807da59 | 173 | { |
fc0589ca | 174 | return chip_to_pxachip(c)->banks + gpio / 32; |
0807da59 EM |
175 | } |
176 | ||
4929f5a8 HZ |
177 | static inline int gpio_is_pxa_type(int type) |
178 | { | |
179 | return (type & MMP_GPIO) == 0; | |
180 | } | |
181 | ||
182 | static inline int gpio_is_mmp_type(int type) | |
183 | { | |
184 | return (type & MMP_GPIO) != 0; | |
185 | } | |
186 | ||
157d2644 HZ |
187 | /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, |
188 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | |
189 | */ | |
190 | static inline int __gpio_is_inverted(int gpio) | |
191 | { | |
192 | if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) | |
193 | return 1; | |
194 | return 0; | |
195 | } | |
196 | ||
197 | /* | |
198 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | |
199 | * function of a GPIO, and GPDRx cannot be altered once configured. It | |
200 | * is attributed as "occupied" here (I know this terminology isn't | |
201 | * accurate, you are welcome to propose a better one :-) | |
202 | */ | |
fc0589ca | 203 | static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio) |
157d2644 | 204 | { |
157d2644 HZ |
205 | void __iomem *base; |
206 | unsigned long gafr = 0, gpdr = 0; | |
207 | int ret, af = 0, dir = 0; | |
208 | ||
fc0589ca | 209 | base = gpio_bank_base(&pchip->chip, gpio); |
157d2644 HZ |
210 | gpdr = readl_relaxed(base + GPDR_OFFSET); |
211 | ||
212 | switch (gpio_type) { | |
213 | case PXA25X_GPIO: | |
214 | case PXA26X_GPIO: | |
215 | case PXA27X_GPIO: | |
216 | gafr = readl_relaxed(base + GAFR_OFFSET); | |
217 | af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; | |
218 | dir = gpdr & GPIO_bit(gpio); | |
219 | ||
220 | if (__gpio_is_inverted(gpio)) | |
221 | ret = (af != 1) || (dir == 0); | |
222 | else | |
223 | ret = (af != 0) || (dir != 0); | |
224 | break; | |
225 | default: | |
226 | ret = gpdr & GPIO_bit(gpio); | |
227 | break; | |
228 | } | |
229 | return ret; | |
230 | } | |
231 | ||
384ca3c6 | 232 | int pxa_irq_to_gpio(int irq) |
4929f5a8 | 233 | { |
384ca3c6 RJ |
234 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
235 | int irq_gpio0; | |
236 | ||
237 | irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0); | |
238 | if (irq_gpio0 > 0) | |
239 | return irq - irq_gpio0; | |
240 | ||
241 | return irq_gpio0; | |
4929f5a8 HZ |
242 | } |
243 | ||
384ca3c6 | 244 | static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
4929f5a8 | 245 | { |
384ca3c6 RJ |
246 | struct pxa_gpio_chip *pchip = chip_to_pxachip(chip); |
247 | ||
248 | return irq_find_mapping(pchip->irqdomain, offset); | |
4929f5a8 HZ |
249 | } |
250 | ||
1c44f5f1 PZ |
251 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
252 | { | |
fc0589ca RJ |
253 | void __iomem *base = gpio_bank_base(chip, offset); |
254 | uint32_t value, mask = GPIO_bit(offset); | |
0807da59 | 255 | unsigned long flags; |
a770d946 RJ |
256 | int ret; |
257 | ||
258 | ret = pinctrl_gpio_direction_input(chip->base + offset); | |
259 | if (!ret) | |
260 | return 0; | |
0807da59 EM |
261 | |
262 | spin_lock_irqsave(&gpio_lock, flags); | |
263 | ||
df664d20 | 264 | value = readl_relaxed(base + GPDR_OFFSET); |
067455aa EM |
265 | if (__gpio_is_inverted(chip->base + offset)) |
266 | value |= mask; | |
267 | else | |
268 | value &= ~mask; | |
df664d20 | 269 | writel_relaxed(value, base + GPDR_OFFSET); |
1c44f5f1 | 270 | |
0807da59 | 271 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
272 | return 0; |
273 | } | |
274 | ||
275 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | |
0807da59 | 276 | unsigned offset, int value) |
1c44f5f1 | 277 | { |
fc0589ca RJ |
278 | void __iomem *base = gpio_bank_base(chip, offset); |
279 | uint32_t tmp, mask = GPIO_bit(offset); | |
0807da59 | 280 | unsigned long flags; |
a770d946 | 281 | int ret; |
0807da59 | 282 | |
df664d20 | 283 | writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
0807da59 | 284 | |
a770d946 | 285 | ret = pinctrl_gpio_direction_output(chip->base + offset); |
c4e5ffb6 RJ |
286 | if (ret) |
287 | return ret; | |
a770d946 | 288 | |
0807da59 EM |
289 | spin_lock_irqsave(&gpio_lock, flags); |
290 | ||
df664d20 | 291 | tmp = readl_relaxed(base + GPDR_OFFSET); |
067455aa EM |
292 | if (__gpio_is_inverted(chip->base + offset)) |
293 | tmp &= ~mask; | |
294 | else | |
295 | tmp |= mask; | |
df664d20 | 296 | writel_relaxed(tmp, base + GPDR_OFFSET); |
1c44f5f1 | 297 | |
0807da59 | 298 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
299 | return 0; |
300 | } | |
301 | ||
1c44f5f1 PZ |
302 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
303 | { | |
fc0589ca RJ |
304 | void __iomem *base = gpio_bank_base(chip, offset); |
305 | u32 gplr = readl_relaxed(base + GPLR_OFFSET); | |
306 | ||
307 | return !!(gplr & GPIO_bit(offset)); | |
1c44f5f1 PZ |
308 | } |
309 | ||
1c44f5f1 PZ |
310 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
311 | { | |
fc0589ca RJ |
312 | void __iomem *base = gpio_bank_base(chip, offset); |
313 | ||
314 | writel_relaxed(GPIO_bit(offset), | |
315 | base + (value ? GPSR_OFFSET : GPCR_OFFSET)); | |
1c44f5f1 PZ |
316 | } |
317 | ||
72121572 DM |
318 | #ifdef CONFIG_OF_GPIO |
319 | static int pxa_gpio_of_xlate(struct gpio_chip *gc, | |
320 | const struct of_phandle_args *gpiospec, | |
321 | u32 *flags) | |
322 | { | |
323 | if (gpiospec->args[0] > pxa_last_gpio) | |
324 | return -EINVAL; | |
325 | ||
72121572 DM |
326 | if (flags) |
327 | *flags = gpiospec->args[1]; | |
328 | ||
fc0589ca | 329 | return gpiospec->args[0]; |
72121572 DM |
330 | } |
331 | #endif | |
332 | ||
a770d946 RJ |
333 | static int pxa_gpio_request(struct gpio_chip *chip, unsigned int offset) |
334 | { | |
335 | return pinctrl_request_gpio(chip->base + offset); | |
336 | } | |
337 | ||
338 | static void pxa_gpio_free(struct gpio_chip *chip, unsigned int offset) | |
339 | { | |
340 | pinctrl_free_gpio(chip->base + offset); | |
341 | } | |
342 | ||
fc0589ca | 343 | static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, |
384ca3c6 | 344 | struct device_node *np, void __iomem *regbase) |
a58fbcd8 | 345 | { |
fc0589ca RJ |
346 | int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32); |
347 | struct pxa_gpio_bank *bank; | |
a58fbcd8 | 348 | |
fc0589ca RJ |
349 | pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks), |
350 | GFP_KERNEL); | |
351 | if (!pchip->banks) | |
0807da59 | 352 | return -ENOMEM; |
a58fbcd8 | 353 | |
fc0589ca RJ |
354 | pchip->chip.label = "gpio-pxa"; |
355 | pchip->chip.direction_input = pxa_gpio_direction_input; | |
356 | pchip->chip.direction_output = pxa_gpio_direction_output; | |
357 | pchip->chip.get = pxa_gpio_get; | |
358 | pchip->chip.set = pxa_gpio_set; | |
359 | pchip->chip.to_irq = pxa_gpio_to_irq; | |
360 | pchip->chip.ngpio = ngpio; | |
a770d946 RJ |
361 | pchip->chip.request = pxa_gpio_request; |
362 | pchip->chip.free = pxa_gpio_free; | |
72121572 | 363 | #ifdef CONFIG_OF_GPIO |
384ca3c6 | 364 | pchip->chip.of_node = np; |
fc0589ca RJ |
365 | pchip->chip.of_xlate = pxa_gpio_of_xlate; |
366 | pchip->chip.of_gpio_n_cells = 2; | |
72121572 | 367 | #endif |
0807da59 | 368 | |
fc0589ca RJ |
369 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { |
370 | bank = pchip->banks + i; | |
371 | bank->regbase = regbase + BANK_OFF(i); | |
0807da59 | 372 | } |
fc0589ca | 373 | |
81d0c31d | 374 | return gpiochip_add_data(&pchip->chip, pchip); |
0807da59 | 375 | } |
e3630db1 | 376 | |
a8f6faeb EM |
377 | /* Update only those GRERx and GFERx edge detection register bits if those |
378 | * bits are set in c->irq_mask | |
379 | */ | |
fc0589ca | 380 | static inline void update_edge_detect(struct pxa_gpio_bank *c) |
a8f6faeb EM |
381 | { |
382 | uint32_t grer, gfer; | |
383 | ||
df664d20 HZ |
384 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; |
385 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; | |
a8f6faeb EM |
386 | grer |= c->irq_edge_rise & c->irq_mask; |
387 | gfer |= c->irq_edge_fall & c->irq_mask; | |
df664d20 HZ |
388 | writel_relaxed(grer, c->regbase + GRER_OFFSET); |
389 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); | |
a8f6faeb EM |
390 | } |
391 | ||
a3f4c927 | 392 | static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) |
e3630db1 | 393 | { |
384ca3c6 RJ |
394 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
395 | unsigned int gpio = irqd_to_hwirq(d); | |
fc0589ca | 396 | struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); |
0807da59 | 397 | unsigned long gpdr, mask = GPIO_bit(gpio); |
e3630db1 | 398 | |
e3630db1 | 399 | if (type == IRQ_TYPE_PROBE) { |
400 | /* Don't mess with enabled GPIOs using preconfigured edges or | |
401 | * GPIOs set to alternate function or to output during probe | |
402 | */ | |
0807da59 | 403 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) |
e3630db1 | 404 | return 0; |
689c04a3 | 405 | |
fc0589ca | 406 | if (__gpio_is_occupied(pchip, gpio)) |
e3630db1 | 407 | return 0; |
689c04a3 | 408 | |
e3630db1 | 409 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
410 | } | |
411 | ||
df664d20 | 412 | gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
0807da59 | 413 | |
067455aa | 414 | if (__gpio_is_inverted(gpio)) |
df664d20 | 415 | writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); |
067455aa | 416 | else |
df664d20 | 417 | writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); |
e3630db1 | 418 | |
419 | if (type & IRQ_TYPE_EDGE_RISING) | |
0807da59 | 420 | c->irq_edge_rise |= mask; |
e3630db1 | 421 | else |
0807da59 | 422 | c->irq_edge_rise &= ~mask; |
e3630db1 | 423 | |
424 | if (type & IRQ_TYPE_EDGE_FALLING) | |
0807da59 | 425 | c->irq_edge_fall |= mask; |
e3630db1 | 426 | else |
0807da59 | 427 | c->irq_edge_fall &= ~mask; |
e3630db1 | 428 | |
a8f6faeb | 429 | update_edge_detect(c); |
e3630db1 | 430 | |
a3f4c927 | 431 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, |
e3630db1 | 432 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
433 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | |
434 | return 0; | |
435 | } | |
436 | ||
384ca3c6 | 437 | static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d) |
e3630db1 | 438 | { |
fc0589ca | 439 | int loop, gpio, n, handled = 0; |
0807da59 | 440 | unsigned long gedr; |
384ca3c6 | 441 | struct pxa_gpio_chip *pchip = d; |
fc0589ca | 442 | struct pxa_gpio_bank *c; |
0d2ee5d7 | 443 | |
e3630db1 | 444 | do { |
e3630db1 | 445 | loop = 0; |
fc0589ca | 446 | for_each_gpio_bank(gpio, c, pchip) { |
df664d20 | 447 | gedr = readl_relaxed(c->regbase + GEDR_OFFSET); |
0807da59 | 448 | gedr = gedr & c->irq_mask; |
df664d20 | 449 | writel_relaxed(gedr, c->regbase + GEDR_OFFSET); |
e3630db1 | 450 | |
d724f1c9 | 451 | for_each_set_bit(n, &gedr, BITS_PER_LONG) { |
0807da59 | 452 | loop = 1; |
e3630db1 | 453 | |
fc0589ca | 454 | generic_handle_irq(gpio_to_irq(gpio + n)); |
0807da59 | 455 | } |
e3630db1 | 456 | } |
384ca3c6 | 457 | handled += loop; |
e3630db1 | 458 | } while (loop); |
0d2ee5d7 | 459 | |
384ca3c6 RJ |
460 | return handled ? IRQ_HANDLED : IRQ_NONE; |
461 | } | |
462 | ||
463 | static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d) | |
464 | { | |
465 | struct pxa_gpio_chip *pchip = d; | |
466 | ||
467 | if (in_irq == pchip->irq0) { | |
468 | generic_handle_irq(gpio_to_irq(0)); | |
469 | } else if (in_irq == pchip->irq1) { | |
470 | generic_handle_irq(gpio_to_irq(1)); | |
471 | } else { | |
472 | pr_err("%s() unknown irq %d\n", __func__, in_irq); | |
473 | return IRQ_NONE; | |
474 | } | |
475 | return IRQ_HANDLED; | |
e3630db1 | 476 | } |
477 | ||
a3f4c927 | 478 | static void pxa_ack_muxed_gpio(struct irq_data *d) |
e3630db1 | 479 | { |
384ca3c6 RJ |
480 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
481 | unsigned int gpio = irqd_to_hwirq(d); | |
fc0589ca | 482 | void __iomem *base = gpio_bank_base(&pchip->chip, gpio); |
0807da59 | 483 | |
fc0589ca | 484 | writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET); |
e3630db1 | 485 | } |
486 | ||
a3f4c927 | 487 | static void pxa_mask_muxed_gpio(struct irq_data *d) |
e3630db1 | 488 | { |
384ca3c6 RJ |
489 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
490 | unsigned int gpio = irqd_to_hwirq(d); | |
fc0589ca RJ |
491 | struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio); |
492 | void __iomem *base = gpio_bank_base(&pchip->chip, gpio); | |
0807da59 EM |
493 | uint32_t grer, gfer; |
494 | ||
fc0589ca | 495 | b->irq_mask &= ~GPIO_bit(gpio); |
0807da59 | 496 | |
fc0589ca RJ |
497 | grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio); |
498 | gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio); | |
499 | writel_relaxed(grer, base + GRER_OFFSET); | |
500 | writel_relaxed(gfer, base + GFER_OFFSET); | |
e3630db1 | 501 | } |
502 | ||
b95ace54 RJ |
503 | static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) |
504 | { | |
384ca3c6 RJ |
505 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
506 | unsigned int gpio = irqd_to_hwirq(d); | |
b95ace54 | 507 | |
fc0589ca RJ |
508 | if (pchip->set_wake) |
509 | return pchip->set_wake(gpio, on); | |
b95ace54 RJ |
510 | else |
511 | return 0; | |
512 | } | |
513 | ||
a3f4c927 | 514 | static void pxa_unmask_muxed_gpio(struct irq_data *d) |
e3630db1 | 515 | { |
384ca3c6 RJ |
516 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
517 | unsigned int gpio = irqd_to_hwirq(d); | |
fc0589ca | 518 | struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); |
0807da59 EM |
519 | |
520 | c->irq_mask |= GPIO_bit(gpio); | |
a8f6faeb | 521 | update_edge_detect(c); |
e3630db1 | 522 | } |
523 | ||
524 | static struct irq_chip pxa_muxed_gpio_chip = { | |
525 | .name = "GPIO", | |
a3f4c927 LB |
526 | .irq_ack = pxa_ack_muxed_gpio, |
527 | .irq_mask = pxa_mask_muxed_gpio, | |
528 | .irq_unmask = pxa_unmask_muxed_gpio, | |
529 | .irq_set_type = pxa_gpio_irq_type, | |
b95ace54 | 530 | .irq_set_wake = pxa_gpio_set_wake, |
e3630db1 | 531 | }; |
532 | ||
2cab0292 | 533 | static int pxa_gpio_nums(struct platform_device *pdev) |
478e223c | 534 | { |
2cab0292 HZ |
535 | const struct platform_device_id *id = platform_get_device_id(pdev); |
536 | struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; | |
478e223c HZ |
537 | int count = 0; |
538 | ||
2cab0292 HZ |
539 | switch (pxa_id->type) { |
540 | case PXA25X_GPIO: | |
541 | case PXA26X_GPIO: | |
542 | case PXA27X_GPIO: | |
543 | case PXA3XX_GPIO: | |
544 | case PXA93X_GPIO: | |
545 | case MMP_GPIO: | |
546 | case MMP2_GPIO: | |
684bba2f | 547 | case PXA1928_GPIO: |
2cab0292 HZ |
548 | gpio_type = pxa_id->type; |
549 | count = pxa_id->gpio_nums - 1; | |
550 | break; | |
551 | default: | |
552 | count = -EINVAL; | |
553 | break; | |
478e223c | 554 | } |
478e223c HZ |
555 | return count; |
556 | } | |
557 | ||
7a4d5079 HZ |
558 | static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, |
559 | irq_hw_number_t hw) | |
560 | { | |
561 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
562 | handle_edge_irq); | |
384ca3c6 | 563 | irq_set_chip_data(irq, d->host_data); |
23393d49 | 564 | irq_set_noprobe(irq); |
7a4d5079 HZ |
565 | return 0; |
566 | } | |
567 | ||
568 | const struct irq_domain_ops pxa_irq_domain_ops = { | |
569 | .map = pxa_irq_domain_map, | |
72121572 | 570 | .xlate = irq_domain_xlate_twocell, |
7a4d5079 HZ |
571 | }; |
572 | ||
0440091b RJ |
573 | #ifdef CONFIG_OF |
574 | static const struct of_device_id pxa_gpio_dt_ids[] = { | |
575 | { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, | |
576 | { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, | |
577 | { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, | |
578 | { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, | |
579 | { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, | |
580 | { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, | |
581 | { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, | |
582 | { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, }, | |
583 | {} | |
584 | }; | |
585 | ||
fc0589ca RJ |
586 | static int pxa_gpio_probe_dt(struct platform_device *pdev, |
587 | struct pxa_gpio_chip *pchip) | |
7a4d5079 | 588 | { |
fc0589ca | 589 | int nr_gpios; |
7a4d5079 HZ |
590 | const struct of_device_id *of_id = |
591 | of_match_device(pxa_gpio_dt_ids, &pdev->dev); | |
f8731174 | 592 | const struct pxa_gpio_id *gpio_id; |
7a4d5079 | 593 | |
f8731174 | 594 | if (!of_id || !of_id->data) { |
7a4d5079 HZ |
595 | dev_err(&pdev->dev, "Failed to find gpio controller\n"); |
596 | return -EFAULT; | |
597 | } | |
f8731174 HZ |
598 | gpio_id = of_id->data; |
599 | gpio_type = gpio_id->type; | |
7a4d5079 | 600 | |
f8731174 | 601 | nr_gpios = gpio_id->gpio_nums; |
7a4d5079 HZ |
602 | pxa_last_gpio = nr_gpios - 1; |
603 | ||
604 | irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); | |
605 | if (irq_base < 0) { | |
606 | dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); | |
fc0589ca | 607 | return irq_base; |
7a4d5079 | 608 | } |
384ca3c6 | 609 | return irq_base; |
7a4d5079 HZ |
610 | } |
611 | #else | |
fc0589ca | 612 | #define pxa_gpio_probe_dt(pdev, pchip) (-1) |
7a4d5079 HZ |
613 | #endif |
614 | ||
3836309d | 615 | static int pxa_gpio_probe(struct platform_device *pdev) |
e3630db1 | 616 | { |
fc0589ca RJ |
617 | struct pxa_gpio_chip *pchip; |
618 | struct pxa_gpio_bank *c; | |
157d2644 | 619 | struct resource *res; |
389eda15 | 620 | struct clk *clk; |
b95ace54 | 621 | struct pxa_gpio_platform_data *info; |
fc0589ca | 622 | void __iomem *gpio_reg_base; |
384ca3c6 | 623 | int gpio, ret; |
157d2644 | 624 | int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; |
e3630db1 | 625 | |
fc0589ca RJ |
626 | pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL); |
627 | if (!pchip) | |
628 | return -ENOMEM; | |
629 | pchip->dev = &pdev->dev; | |
630 | ||
b8f649f1 HZ |
631 | info = dev_get_platdata(&pdev->dev); |
632 | if (info) { | |
633 | irq_base = info->irq_base; | |
634 | if (irq_base <= 0) | |
635 | return -EINVAL; | |
2cab0292 | 636 | pxa_last_gpio = pxa_gpio_nums(pdev); |
fc0589ca | 637 | pchip->set_wake = info->gpio_set_wake; |
9450be76 | 638 | } else { |
384ca3c6 RJ |
639 | irq_base = pxa_gpio_probe_dt(pdev, pchip); |
640 | if (irq_base < 0) | |
b8f649f1 | 641 | return -EINVAL; |
9450be76 DM |
642 | } |
643 | ||
478e223c | 644 | if (!pxa_last_gpio) |
157d2644 HZ |
645 | return -EINVAL; |
646 | ||
384ca3c6 RJ |
647 | pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node, |
648 | pxa_last_gpio + 1, irq_base, | |
649 | 0, &pxa_irq_domain_ops, pchip); | |
41d107ad DC |
650 | if (!pchip->irqdomain) |
651 | return -ENOMEM; | |
384ca3c6 | 652 | |
157d2644 HZ |
653 | irq0 = platform_get_irq_byname(pdev, "gpio0"); |
654 | irq1 = platform_get_irq_byname(pdev, "gpio1"); | |
655 | irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); | |
656 | if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) | |
657 | || (irq_mux <= 0)) | |
658 | return -EINVAL; | |
384ca3c6 RJ |
659 | |
660 | pchip->irq0 = irq0; | |
661 | pchip->irq1 = irq1; | |
157d2644 | 662 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
8852b2f7 RJ |
663 | gpio_reg_base = devm_ioremap(&pdev->dev, res->start, |
664 | resource_size(res)); | |
157d2644 HZ |
665 | if (!gpio_reg_base) |
666 | return -EINVAL; | |
667 | ||
668 | if (irq0 > 0) | |
669 | gpio_offset = 2; | |
e3630db1 | 670 | |
389eda15 HZ |
671 | clk = clk_get(&pdev->dev, NULL); |
672 | if (IS_ERR(clk)) { | |
673 | dev_err(&pdev->dev, "Error %ld to get gpio clock\n", | |
674 | PTR_ERR(clk)); | |
389eda15 HZ |
675 | return PTR_ERR(clk); |
676 | } | |
6ab49f42 | 677 | ret = clk_prepare_enable(clk); |
389eda15 HZ |
678 | if (ret) { |
679 | clk_put(clk); | |
389eda15 HZ |
680 | return ret; |
681 | } | |
389eda15 | 682 | |
0807da59 | 683 | /* Initialize GPIO chips */ |
384ca3c6 RJ |
684 | ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node, |
685 | gpio_reg_base); | |
fc0589ca RJ |
686 | if (ret) { |
687 | clk_put(clk); | |
688 | return ret; | |
689 | } | |
0807da59 | 690 | |
e3630db1 | 691 | /* clear all GPIO edge detects */ |
fc0589ca | 692 | for_each_gpio_bank(gpio, c, pchip) { |
df664d20 HZ |
693 | writel_relaxed(0, c->regbase + GFER_OFFSET); |
694 | writel_relaxed(0, c->regbase + GRER_OFFSET); | |
e37f4af7 | 695 | writel_relaxed(~0, c->regbase + GEDR_OFFSET); |
be24168f HZ |
696 | /* unmask GPIO edge detect for AP side */ |
697 | if (gpio_is_mmp_type(gpio_type)) | |
698 | writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); | |
e3630db1 | 699 | } |
700 | ||
384ca3c6 RJ |
701 | if (irq0 > 0) { |
702 | ret = devm_request_irq(&pdev->dev, | |
703 | irq0, pxa_gpio_direct_handler, 0, | |
704 | "gpio-0", pchip); | |
705 | if (ret) | |
706 | dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n", | |
707 | ret); | |
e3630db1 | 708 | } |
384ca3c6 RJ |
709 | if (irq1 > 0) { |
710 | ret = devm_request_irq(&pdev->dev, | |
711 | irq1, pxa_gpio_direct_handler, 0, | |
712 | "gpio-1", pchip); | |
713 | if (ret) | |
714 | dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n", | |
715 | ret); | |
716 | } | |
717 | ret = devm_request_irq(&pdev->dev, | |
718 | irq_mux, pxa_gpio_demux_handler, 0, | |
719 | "gpio-mux", pchip); | |
720 | if (ret) | |
721 | dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n", | |
722 | ret); | |
e3630db1 | 723 | |
fc0589ca | 724 | pxa_gpio_chip = pchip; |
ae4f4cfd | 725 | |
157d2644 HZ |
726 | return 0; |
727 | } | |
728 | ||
2cab0292 HZ |
729 | static const struct platform_device_id gpio_id_table[] = { |
730 | { "pxa25x-gpio", (unsigned long)&pxa25x_id }, | |
731 | { "pxa26x-gpio", (unsigned long)&pxa26x_id }, | |
732 | { "pxa27x-gpio", (unsigned long)&pxa27x_id }, | |
733 | { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, | |
734 | { "pxa93x-gpio", (unsigned long)&pxa93x_id }, | |
735 | { "mmp-gpio", (unsigned long)&mmp_id }, | |
736 | { "mmp2-gpio", (unsigned long)&mmp2_id }, | |
684bba2f | 737 | { "pxa1928-gpio", (unsigned long)&pxa1928_id }, |
2cab0292 HZ |
738 | { }, |
739 | }; | |
740 | ||
157d2644 HZ |
741 | static struct platform_driver pxa_gpio_driver = { |
742 | .probe = pxa_gpio_probe, | |
743 | .driver = { | |
744 | .name = "pxa-gpio", | |
f43e04ec | 745 | .of_match_table = of_match_ptr(pxa_gpio_dt_ids), |
157d2644 | 746 | }, |
2cab0292 | 747 | .id_table = gpio_id_table, |
157d2644 | 748 | }; |
cf3fa17c | 749 | |
eae122b8 | 750 | static int __init pxa_gpio_legacy_init(void) |
cf3fa17c | 751 | { |
eae122b8 RJ |
752 | if (of_have_populated_dt()) |
753 | return 0; | |
754 | ||
cf3fa17c LW |
755 | return platform_driver_register(&pxa_gpio_driver); |
756 | } | |
eae122b8 RJ |
757 | postcore_initcall(pxa_gpio_legacy_init); |
758 | ||
759 | static int __init pxa_gpio_dt_init(void) | |
760 | { | |
761 | if (of_have_populated_dt()) | |
762 | return platform_driver_register(&pxa_gpio_driver); | |
763 | ||
764 | return 0; | |
765 | } | |
766 | device_initcall(pxa_gpio_dt_init); | |
663707c1 | 767 | |
768 | #ifdef CONFIG_PM | |
2eaa03b5 | 769 | static int pxa_gpio_suspend(void) |
663707c1 | 770 | { |
fc0589ca RJ |
771 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
772 | struct pxa_gpio_bank *c; | |
0807da59 | 773 | int gpio; |
663707c1 | 774 | |
fc0589ca | 775 | for_each_gpio_bank(gpio, c, pchip) { |
df664d20 HZ |
776 | c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); |
777 | c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); | |
778 | c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); | |
779 | c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); | |
663707c1 | 780 | |
781 | /* Clear GPIO transition detect bits */ | |
df664d20 | 782 | writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); |
663707c1 | 783 | } |
784 | return 0; | |
785 | } | |
786 | ||
2eaa03b5 | 787 | static void pxa_gpio_resume(void) |
663707c1 | 788 | { |
fc0589ca RJ |
789 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
790 | struct pxa_gpio_bank *c; | |
0807da59 | 791 | int gpio; |
663707c1 | 792 | |
fc0589ca | 793 | for_each_gpio_bank(gpio, c, pchip) { |
663707c1 | 794 | /* restore level with set/clear */ |
e37f4af7 | 795 | writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); |
df664d20 | 796 | writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); |
663707c1 | 797 | |
df664d20 HZ |
798 | writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); |
799 | writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); | |
800 | writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); | |
663707c1 | 801 | } |
663707c1 | 802 | } |
803 | #else | |
804 | #define pxa_gpio_suspend NULL | |
805 | #define pxa_gpio_resume NULL | |
806 | #endif | |
807 | ||
2eaa03b5 | 808 | struct syscore_ops pxa_gpio_syscore_ops = { |
663707c1 | 809 | .suspend = pxa_gpio_suspend, |
810 | .resume = pxa_gpio_resume, | |
811 | }; | |
157d2644 HZ |
812 | |
813 | static int __init pxa_gpio_sysinit(void) | |
814 | { | |
815 | register_syscore_ops(&pxa_gpio_syscore_ops); | |
816 | return 0; | |
817 | } | |
818 | postcore_initcall(pxa_gpio_sysinit); |