[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-rcar.c

/*
 * Renesas R-Car GPIO Support
 *
 *  Copyright (C) 2014 Renesas Electronics Corporation
 *  Copyright (C) 2013 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/slab.h>

struct gpio_rcar_priv {
	void __iomem *base;
	spinlock_t lock;
	struct platform_device *pdev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	struct clk *clk;
	unsigned int irq_parent;
	bool has_both_edge_trigger;
	bool needs_clk;
};

#define IOINTSEL 0x00	/* General IO/Interrupt Switching Register */
#define INOUTSEL 0x04	/* General Input/Output Switching Register */
#define OUTDT 0x08	/* General Output Register */
#define INDT 0x0c	/* General Input Register */
#define INTDT 0x10	/* Interrupt Display Register */
#define INTCLR 0x14	/* Interrupt Clear Register */
#define INTMSK 0x18	/* Interrupt Mask Register */
#define MSKCLR 0x1c	/* Interrupt Mask Clear Register */
#define POSNEG 0x20	/* Positive/Negative Logic Select Register */
#define EDGLEVEL 0x24	/* Edge/level Select Register */
#define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
#define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */

#define RCAR_MAX_GPIO_PER_BANK		32

static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
{
	return ioread32(p->base + offs);
}

static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
				   u32 value)
{
	iowrite32(value, p->base + offs);
}

static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
				 int bit, bool value)
{
	u32 tmp = gpio_rcar_read(p, offs);

	if (value)
		tmp |= BIT(bit);
	else
		tmp &= ~BIT(bit);

	gpio_rcar_write(p, offs, tmp);
}

static void gpio_rcar_irq_disable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_irq_enable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
						  unsigned int hwirq,
						  bool active_high_rising_edge,
						  bool level_trigger,
						  bool both)
{
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting Edge-Sensitive Interrupt Input Mode" and
	 * "Setting Level-Sensitive Interrupt Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive or negative logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);

	/* Configure edge or level trigger in EDGLEVEL */
	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);

	/* Select one edge or both edges in BOTHEDGE */
	if (p->has_both_edge_trigger)
		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);

	/* Select "Interrupt Input Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);

	/* Write INTCLR in case of edge trigger */
	if (!level_trigger)
		gpio_rcar_write(p, INTCLR, BIT(hwirq));

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	unsigned int hwirq = irqd_to_hwirq(d);

	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
						      false);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
						      false);
		break;
	case IRQ_TYPE_EDGE_RISING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_BOTH:
		if (!p->has_both_edge_trigger)
			return -EINVAL;
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      true);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	int error;

	if (p->irq_parent) {
		error = irq_set_irq_wake(p->irq_parent, on);
		if (error) {
			dev_dbg(&p->pdev->dev,
				"irq %u doesn't support irq_set_wake\n",
				p->irq_parent);
			p->irq_parent = 0;
		}
	}

	if (!p->clk)
		return 0;

	if (on)
		clk_enable(p->clk);
	else
		clk_disable(p->clk);

	return 0;
}

static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
{
	struct gpio_rcar_priv *p = dev_id;
	u32 pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = gpio_rcar_read(p, INTDT) &
			  gpio_rcar_read(p, INTMSK))) {
		offset = __ffs(pending);
		gpio_rcar_write(p, INTCLR, BIT(offset));
		generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
						    offset));
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
						       unsigned int gpio,
						       bool output)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting General Output Mode" and
	 * "Setting General Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, gpio, false);

	/* Select "General Input/Output Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);

	/* Select Input Mode or Output Mode in INOUTSEL */
	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	int error;

	error = pm_runtime_get_sync(&p->pdev->dev);
	if (error < 0)
		return error;

	error = pinctrl_request_gpio(chip->base + offset);
	if (error)
		pm_runtime_put(&p->pdev->dev);

	return error;
}

static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);

	pinctrl_free_gpio(chip->base + offset);

	/*
	 * Set the GPIO as an input to ensure that the next GPIO request won't
	 * drive the GPIO pin as an output.
	 */
	gpio_rcar_config_general_input_output_mode(chip, offset, false);

	pm_runtime_put(&p->pdev->dev);
}

static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
{
	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	return 0;
}

static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
{
	u32 bit = BIT(offset);

	/* testing on r8a7790 shows that INDT does not show correct pin state
	 * when configured as output, so use OUTDT in case of output pins */
	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
		return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
	else
		return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
}

static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&p->lock, flags);
	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	spin_unlock_irqrestore(&p->lock, flags);
}

static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
				   unsigned long *bits)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;
	u32 val, bankmask;

	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
	if (!bankmask)
		return;

	spin_lock_irqsave(&p->lock, flags);
	val = gpio_rcar_read(p, OUTDT);
	val &= ~bankmask;
	val |= (bankmask & bits[0]);
	gpio_rcar_write(p, OUTDT, val);
	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	gpio_rcar_set(chip, offset, value);
	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	return 0;
}

struct gpio_rcar_info {
	bool has_both_edge_trigger;
	bool needs_clk;
};

static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
	.has_both_edge_trigger = false,
	.needs_clk = false,
};

static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
	.has_both_edge_trigger = true,
	.needs_clk = true,
};

static const struct of_device_id gpio_rcar_of_table[] = {
	{
		.compatible = "renesas,gpio-r8a7743",
		/* RZ/G1 GPIO is identical to R-Car Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7790",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7791",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7792",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7793",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7794",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7795",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7796",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-rcar",
		.data = &gpio_rcar_info_gen1,
	}, {
		/* Terminator */
	},
};

MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);

static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
{
	struct device_node *np = p->pdev->dev.of_node;
	const struct of_device_id *match;
	const struct gpio_rcar_info *info;
	struct of_phandle_args args;
	int ret;

	match = of_match_node(gpio_rcar_of_table, np);
	if (!match)
		return -EINVAL;

	info = match->data;

	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
	p->has_both_edge_trigger = info->has_both_edge_trigger;
	p->needs_clk = info->needs_clk;

	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
		dev_warn(&p->pdev->dev,
			 "Invalid number of gpio lines %u, using %u\n", *npins,
			 RCAR_MAX_GPIO_PER_BANK);
		*npins = RCAR_MAX_GPIO_PER_BANK;
	}

	return 0;
}

static int gpio_rcar_probe(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p;
	struct resource *io, *irq;
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	struct device *dev = &pdev->dev;
	const char *name = dev_name(dev);
	unsigned int npins;
	int ret;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p)
		return -ENOMEM;

	p->pdev = pdev;
	spin_lock_init(&p->lock);

	/* Get device configuration from DT node */
	ret = gpio_rcar_parse_dt(p, &npins);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, p);

	p->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(p->clk)) {
		if (p->needs_clk) {
			dev_err(dev, "unable to get clock\n");
			ret = PTR_ERR(p->clk);
			goto err0;
		}
		p->clk = NULL;
	}

	pm_runtime_enable(dev);

	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);

	if (!io || !irq) {
		dev_err(dev, "missing IRQ or IOMEM\n");
		ret = -EINVAL;
		goto err0;
	}

	p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
	if (!p->base) {
		dev_err(dev, "failed to remap I/O memory\n");
		ret = -ENXIO;
		goto err0;
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->request = gpio_rcar_request;
	gpio_chip->free = gpio_rcar_free;
	gpio_chip->direction_input = gpio_rcar_direction_input;
	gpio_chip->get = gpio_rcar_get;
	gpio_chip->direction_output = gpio_rcar_direction_output;
	gpio_chip->set = gpio_rcar_set;
	gpio_chip->set_multiple = gpio_rcar_set_multiple;
	gpio_chip->label = name;
	gpio_chip->parent = dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = -1;
	gpio_chip->ngpio = npins;

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->parent_device = dev;
	irq_chip->irq_mask = gpio_rcar_irq_disable;
	irq_chip->irq_unmask = gpio_rcar_irq_enable;
	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
	irq_chip->flags	= IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;

	ret = gpiochip_add_data(gpio_chip, p);
	if (ret) {
		dev_err(dev, "failed to add GPIO controller\n");
		goto err0;
	}

	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "cannot add irqchip\n");
		goto err1;
	}

	p->irq_parent = irq->start;
	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
			     IRQF_SHARED, name, p)) {
		dev_err(dev, "failed to request IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	dev_info(dev, "driving %d GPIOs\n", npins);

	return 0;

err1:
	gpiochip_remove(gpio_chip);
err0:
	pm_runtime_disable(dev);
	return ret;
}

static int gpio_rcar_remove(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);

	gpiochip_remove(&p->gpio_chip);

	pm_runtime_disable(&pdev->dev);
	return 0;
}

static struct platform_driver gpio_rcar_device_driver = {
	.probe		= gpio_rcar_probe,
	.remove		= gpio_rcar_remove,
	.driver		= {
		.name	= "gpio_rcar",
		.of_match_table = of_match_ptr(gpio_rcar_of_table),
	}
};

module_platform_driver(gpio_rcar_device_driver);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
119f5e44 MD	1	/*
	2	* Renesas R-Car GPIO Support
	3	*
1fd2b49d	4	* Copyright (C) 2014 Renesas Electronics Corporation
119f5e44 MD	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
ab82fa7d	17	#include <linux/clk.h>
119f5e44 MD	18	#include <linux/err.h>
	19	#include <linux/gpio.h>
	20	#include <linux/init.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/io.h>
	23	#include <linux/ioport.h>
	24	#include <linux/irq.h>
119f5e44	25	#include <linux/module.h>
bd0bf468	26	#include <linux/of.h>
dc3465a9	27	#include <linux/pinctrl/consumer.h>
119f5e44	28	#include <linux/platform_device.h>
df0c6c80	29	#include <linux/pm_runtime.h>
119f5e44 MD	30	#include <linux/spinlock.h>
	31	#include <linux/slab.h>
	32
	33	struct gpio_rcar_priv {
	34	void __iomem *base;
	35	spinlock_t lock;
119f5e44 MD	36	struct platform_device *pdev;
	37	struct gpio_chip gpio_chip;
	38	struct irq_chip irq_chip;
ab82fa7d	39	struct clk *clk;
8b092be9 GU	40	unsigned int irq_parent;
8b092be9 GU	41	bool has_both_edge_trigger;
e1fef9e2	42	bool needs_clk;
119f5e44 MD	43	};
119f5e44 MD	44
3dc1e685 GU	45	#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
	46	#define INOUTSEL 0x04 /* General Input/Output Switching Register */
	47	#define OUTDT 0x08 /* General Output Register */
	48	#define INDT 0x0c /* General Input Register */
	49	#define INTDT 0x10 /* Interrupt Display Register */
	50	#define INTCLR 0x14 /* Interrupt Clear Register */
	51	#define INTMSK 0x18 /* Interrupt Mask Register */
	52	#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
	53	#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
	54	#define EDGLEVEL 0x24 /* Edge/level Select Register */
	55	#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
	56	#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
119f5e44	57
159f8a02 LP	58	#define RCAR_MAX_GPIO_PER_BANK 32
159f8a02 LP	59
119f5e44 MD	60	static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
	61	{
	62	return ioread32(p->base + offs);
	63	}
	64
	65	static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
	66	u32 value)
	67	{
	68	iowrite32(value, p->base + offs);
	69	}
	70
	71	static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
	72	int bit, bool value)
	73	{
	74	u32 tmp = gpio_rcar_read(p, offs);
	75
	76	if (value)
	77	tmp \|= BIT(bit);
	78	else
	79	tmp &= ~BIT(bit);
	80
	81	gpio_rcar_write(p, offs, tmp);
	82	}
	83
	84	static void gpio_rcar_irq_disable(struct irq_data *d)
	85	{
c7f3c5d3	86	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	87	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	88
	89	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
	90	}
	91
	92	static void gpio_rcar_irq_enable(struct irq_data *d)
	93	{
c7f3c5d3	94	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	95	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	96
	97	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
	98	}
	99
	100	static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
	101	unsigned int hwirq,
	102	bool active_high_rising_edge,
7e1092b5 SH	103	bool level_trigger,
7e1092b5 SH	104	bool both)
119f5e44 MD	105	{
	106	unsigned long flags;
	107
	108	/* follow steps in the GPIO documentation for
	109	* "Setting Edge-Sensitive Interrupt Input Mode" and
	110	* "Setting Level-Sensitive Interrupt Input Mode"
	111	*/
	112
	113	spin_lock_irqsave(&p->lock, flags);
	114
	115	/* Configure postive or negative logic in POSNEG */
	116	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
	117
	118	/* Configure edge or level trigger in EDGLEVEL */
	119	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
	120
7e1092b5	121	/* Select one edge or both edges in BOTHEDGE */
8b092be9	122	if (p->has_both_edge_trigger)
7e1092b5 SH	123	gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
7e1092b5 SH	124
119f5e44 MD	125	/* Select "Interrupt Input Mode" in IOINTSEL */
	126	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
	127
	128	/* Write INTCLR in case of edge trigger */
	129	if (!level_trigger)
	130	gpio_rcar_write(p, INTCLR, BIT(hwirq));
	131
	132	spin_unlock_irqrestore(&p->lock, flags);
	133	}
	134
	135	static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
	136	{
c7f3c5d3	137	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	138	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	139	unsigned int hwirq = irqd_to_hwirq(d);
	140
	141	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
	142
	143	switch (type & IRQ_TYPE_SENSE_MASK) {
	144	case IRQ_TYPE_LEVEL_HIGH:
7e1092b5 SH	145	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
7e1092b5 SH	146	false);
119f5e44 MD	147	break;
119f5e44 MD	148	case IRQ_TYPE_LEVEL_LOW:
7e1092b5 SH	149	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
7e1092b5 SH	150	false);
119f5e44 MD	151	break;
119f5e44 MD	152	case IRQ_TYPE_EDGE_RISING:
7e1092b5 SH	153	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
7e1092b5 SH	154	false);
119f5e44 MD	155	break;
119f5e44 MD	156	case IRQ_TYPE_EDGE_FALLING:
7e1092b5 SH	157	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
	158	false);
	159	break;
	160	case IRQ_TYPE_EDGE_BOTH:
8b092be9	161	if (!p->has_both_edge_trigger)
7e1092b5 SH	162	return -EINVAL;
	163	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
	164	true);
119f5e44 MD	165	break;
	166	default:
	167	return -EINVAL;
	168	}
	169	return 0;
	170	}
	171
ab82fa7d GU	172	static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
	173	{
	174	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	175	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
501ef0f9 GU	176	int error;
	177
	178	if (p->irq_parent) {
	179	error = irq_set_irq_wake(p->irq_parent, on);
	180	if (error) {
	181	dev_dbg(&p->pdev->dev,
	182	"irq %u doesn't support irq_set_wake\n",
	183	p->irq_parent);
	184	p->irq_parent = 0;
	185	}
	186	}
ab82fa7d GU	187
	188	if (!p->clk)
	189	return 0;
	190
	191	if (on)
	192	clk_enable(p->clk);
	193	else
	194	clk_disable(p->clk);
	195
	196	return 0;
	197	}
	198
119f5e44 MD	199	static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
	200	{
	201	struct gpio_rcar_priv *p = dev_id;
	202	u32 pending;
	203	unsigned int offset, irqs_handled = 0;
	204
8808b64d VB	205	while ((pending = gpio_rcar_read(p, INTDT) &
8808b64d VB	206	gpio_rcar_read(p, INTMSK))) {
119f5e44 MD	207	offset = __ffs(pending);
119f5e44 MD	208	gpio_rcar_write(p, INTCLR, BIT(offset));
c7f3c5d3 GU	209	generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
c7f3c5d3 GU	210	offset));
119f5e44 MD	211	irqs_handled++;
	212	}
	213
	214	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	215	}
	216
119f5e44 MD	217	static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
	218	unsigned int gpio,
	219	bool output)
	220	{
c7b6f457	221	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	222	unsigned long flags;
	223
	224	/* follow steps in the GPIO documentation for
	225	* "Setting General Output Mode" and
	226	* "Setting General Input Mode"
	227	*/
	228
	229	spin_lock_irqsave(&p->lock, flags);
	230
	231	/* Configure postive logic in POSNEG */
	232	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
	233
	234	/* Select "General Input/Output Mode" in IOINTSEL */
	235	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
	236
	237	/* Select Input Mode or Output Mode in INOUTSEL */
	238	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
	239
	240	spin_unlock_irqrestore(&p->lock, flags);
	241	}
	242
dc3465a9 LP	243	static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
dc3465a9 LP	244	{
2d65472b GU	245	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	246	int error;
	247
	248	error = pm_runtime_get_sync(&p->pdev->dev);
	249	if (error < 0)
	250	return error;
	251
	252	error = pinctrl_request_gpio(chip->base + offset);
	253	if (error)
	254	pm_runtime_put(&p->pdev->dev);
	255
	256	return error;
dc3465a9 LP	257	}
	258
	259	static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
	260	{
2d65472b GU	261	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
2d65472b GU	262
dc3465a9 LP	263	pinctrl_free_gpio(chip->base + offset);
dc3465a9 LP	264
ce0e2c60 LW	265	/*
ce0e2c60 LW	266	* Set the GPIO as an input to ensure that the next GPIO request won't
dc3465a9 LP	267	* drive the GPIO pin as an output.
	268	*/
	269	gpio_rcar_config_general_input_output_mode(chip, offset, false);
2d65472b GU	270
2d65472b GU	271	pm_runtime_put(&p->pdev->dev);
dc3465a9 LP	272	}
dc3465a9 LP	273
119f5e44 MD	274	static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
	275	{
	276	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	277	return 0;
	278	}
	279
	280	static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
	281	{
ae9550f6 MD	282	u32 bit = BIT(offset);
	283
	284	/* testing on r8a7790 shows that INDT does not show correct pin state
	285	* when configured as output, so use OUTDT in case of output pins */
c7b6f457 LW	286	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
c7b6f457 LW	287	return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
ae9550f6	288	else
c7b6f457	289	return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
119f5e44 MD	290	}
	291
	292	static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
	293	{
c7b6f457	294	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	295	unsigned long flags;
	296
	297	spin_lock_irqsave(&p->lock, flags);
	298	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	299	spin_unlock_irqrestore(&p->lock, flags);
	300	}
	301
dbb763b8 GU	302	static void gpio_rcar_set_multiple(struct gpio_chip chip, unsigned long mask,
	303	unsigned long *bits)
	304	{
	305	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	306	unsigned long flags;
	307	u32 val, bankmask;
	308
	309	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
	310	if (!bankmask)
	311	return;
	312
	313	spin_lock_irqsave(&p->lock, flags);
	314	val = gpio_rcar_read(p, OUTDT);
	315	val &= ~bankmask;
	316	val \|= (bankmask & bits[0]);
	317	gpio_rcar_write(p, OUTDT, val);
	318	spin_unlock_irqrestore(&p->lock, flags);
	319	}
	320
119f5e44 MD	321	static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
	322	int value)
	323	{
	324	/* write GPIO value to output before selecting output mode of pin */
	325	gpio_rcar_set(chip, offset, value);
	326	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	327	return 0;
	328	}
	329
850dfe17 LP	330	struct gpio_rcar_info {
850dfe17 LP	331	bool has_both_edge_trigger;
e1fef9e2	332	bool needs_clk;
850dfe17 LP	333	};
850dfe17 LP	334
1fd2b49d HN	335	static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
1fd2b49d HN	336	.has_both_edge_trigger = false,
e1fef9e2	337	.needs_clk = false,
1fd2b49d HN	338	};
	339
	340	static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
	341	.has_both_edge_trigger = true,
e1fef9e2	342	.needs_clk = true,
1fd2b49d HN	343	};
1fd2b49d HN	344
850dfe17 LP	345	static const struct of_device_id gpio_rcar_of_table[] = {
850dfe17 LP	346	{
85bb4646 BD	347	.compatible = "renesas,gpio-r8a7743",
	348	/* RZ/G1 GPIO is identical to R-Car Gen2. */
	349	.data = &gpio_rcar_info_gen2,
	350	}, {
850dfe17	351	.compatible = "renesas,gpio-r8a7790",
1fd2b49d	352	.data = &gpio_rcar_info_gen2,
850dfe17 LP	353	}, {
850dfe17 LP	354	.compatible = "renesas,gpio-r8a7791",
1fd2b49d	355	.data = &gpio_rcar_info_gen2,
e79c5830 SS	356	}, {
	357	.compatible = "renesas,gpio-r8a7792",
	358	.data = &gpio_rcar_info_gen2,
1fd2b49d HN	359	}, {
	360	.compatible = "renesas,gpio-r8a7793",
	361	.data = &gpio_rcar_info_gen2,
	362	}, {
	363	.compatible = "renesas,gpio-r8a7794",
	364	.data = &gpio_rcar_info_gen2,
8cd14702 UH	365	}, {
	366	.compatible = "renesas,gpio-r8a7795",
	367	/* Gen3 GPIO is identical to Gen2. */
	368	.data = &gpio_rcar_info_gen2,
5d2f1d6e SH	369	}, {
	370	.compatible = "renesas,gpio-r8a7796",
	371	/* Gen3 GPIO is identical to Gen2. */
	372	.data = &gpio_rcar_info_gen2,
850dfe17 LP	373	}, {
850dfe17 LP	374	.compatible = "renesas,gpio-rcar",
1fd2b49d	375	.data = &gpio_rcar_info_gen1,
850dfe17 LP	376	}, {
	377	/* Terminator */
	378	},
	379	};
	380
	381	MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
	382
8b092be9	383	static int gpio_rcar_parse_dt(struct gpio_rcar_priv p, unsigned int npins)
159f8a02	384	{
159f8a02	385	struct device_node *np = p->pdev->dev.of_node;
8b092be9 GU	386	const struct of_device_id *match;
8b092be9 GU	387	const struct gpio_rcar_info *info;
159f8a02 LP	388	struct of_phandle_args args;
159f8a02 LP	389	int ret;
159f8a02	390
8b092be9 GU	391	match = of_match_node(gpio_rcar_of_table, np);
	392	if (!match)
	393	return -EINVAL;
850dfe17	394
8b092be9	395	info = match->data;
850dfe17	396
8b092be9 GU	397	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
	398	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
	399	p->has_both_edge_trigger = info->has_both_edge_trigger;
e1fef9e2	400	p->needs_clk = info->needs_clk;
850dfe17	401
8b092be9	402	if (npins == 0 \|\| npins > RCAR_MAX_GPIO_PER_BANK) {
159f8a02	403	dev_warn(&p->pdev->dev,
8b092be9 GU	404	"Invalid number of gpio lines %u, using %u\n", *npins,
	405	RCAR_MAX_GPIO_PER_BANK);
	406	*npins = RCAR_MAX_GPIO_PER_BANK;
159f8a02	407	}
850dfe17 LP	408
850dfe17 LP	409	return 0;
159f8a02 LP	410	}
159f8a02 LP	411
119f5e44 MD	412	static int gpio_rcar_probe(struct platform_device *pdev)
119f5e44 MD	413	{
119f5e44 MD	414	struct gpio_rcar_priv *p;
	415	struct resource io, irq;
	416	struct gpio_chip *gpio_chip;
	417	struct irq_chip *irq_chip;
b22978fc GU	418	struct device *dev = &pdev->dev;
b22978fc GU	419	const char *name = dev_name(dev);
8b092be9	420	unsigned int npins;
119f5e44 MD	421	int ret;
119f5e44 MD	422
b22978fc	423	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
7d82bf34 GU	424	if (!p)
7d82bf34 GU	425	return -ENOMEM;
119f5e44	426
119f5e44	427	p->pdev = pdev;
119f5e44 MD	428	spin_lock_init(&p->lock);
119f5e44 MD	429
8b092be9 GU	430	/* Get device configuration from DT node */
8b092be9 GU	431	ret = gpio_rcar_parse_dt(p, &npins);
850dfe17 LP	432	if (ret < 0)
850dfe17 LP	433	return ret;
159f8a02 LP	434
	435	platform_set_drvdata(pdev, p);
	436
ab82fa7d GU	437	p->clk = devm_clk_get(dev, NULL);
ab82fa7d GU	438	if (IS_ERR(p->clk)) {
e1fef9e2 GU	439	if (p->needs_clk) {
	440	dev_err(dev, "unable to get clock\n");
	441	ret = PTR_ERR(p->clk);
	442	goto err0;
	443	}
ab82fa7d GU	444	p->clk = NULL;
	445	}
	446
df0c6c80	447	pm_runtime_enable(dev);
df0c6c80	448
119f5e44 MD	449	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	450	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	451
	452	if (!io \|\| !irq) {
b22978fc	453	dev_err(dev, "missing IRQ or IOMEM\n");
119f5e44 MD	454	ret = -EINVAL;
	455	goto err0;
	456	}
	457
b22978fc	458	p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
119f5e44	459	if (!p->base) {
b22978fc	460	dev_err(dev, "failed to remap I/O memory\n");
119f5e44 MD	461	ret = -ENXIO;
	462	goto err0;
	463	}
	464
	465	gpio_chip = &p->gpio_chip;
dc3465a9 LP	466	gpio_chip->request = gpio_rcar_request;
dc3465a9 LP	467	gpio_chip->free = gpio_rcar_free;
119f5e44 MD	468	gpio_chip->direction_input = gpio_rcar_direction_input;
	469	gpio_chip->get = gpio_rcar_get;
	470	gpio_chip->direction_output = gpio_rcar_direction_output;
	471	gpio_chip->set = gpio_rcar_set;
dbb763b8	472	gpio_chip->set_multiple = gpio_rcar_set_multiple;
119f5e44	473	gpio_chip->label = name;
58383c78	474	gpio_chip->parent = dev;
119f5e44	475	gpio_chip->owner = THIS_MODULE;
8b092be9 GU	476	gpio_chip->base = -1;
8b092be9 GU	477	gpio_chip->ngpio = npins;
119f5e44 MD	478
	479	irq_chip = &p->irq_chip;
	480	irq_chip->name = name;
47bd38a3	481	irq_chip->parent_device = dev;
119f5e44 MD	482	irq_chip->irq_mask = gpio_rcar_irq_disable;
119f5e44 MD	483	irq_chip->irq_unmask = gpio_rcar_irq_enable;
119f5e44	484	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
ab82fa7d GU	485	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
ab82fa7d GU	486	irq_chip->flags = IRQCHIP_SET_TYPE_MASKED \| IRQCHIP_MASK_ON_SUSPEND;
119f5e44	487
c7b6f457	488	ret = gpiochip_add_data(gpio_chip, p);
c7f3c5d3 GU	489	if (ret) {
c7f3c5d3 GU	490	dev_err(dev, "failed to add GPIO controller\n");
0c8aab8e	491	goto err0;
119f5e44 MD	492	}
119f5e44 MD	493
8b092be9 GU	494	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
8b092be9 GU	495	IRQ_TYPE_NONE);
c7f3c5d3 GU	496	if (ret) {
	497	dev_err(dev, "cannot add irqchip\n");
	498	goto err1;
	499	}
	500
ab82fa7d	501	p->irq_parent = irq->start;
b22978fc GU	502	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
	503	IRQF_SHARED, name, p)) {
	504	dev_err(dev, "failed to request IRQ\n");
119f5e44 MD	505	ret = -ENOENT;
	506	goto err1;
	507	}
	508
8b092be9	509	dev_info(dev, "driving %d GPIOs\n", npins);
dc3465a9	510
119f5e44 MD	511	return 0;
	512
	513	err1:
4d84b9e4	514	gpiochip_remove(gpio_chip);
119f5e44	515	err0:
df0c6c80	516	pm_runtime_disable(dev);
119f5e44 MD	517	return ret;
	518	}
	519
	520	static int gpio_rcar_remove(struct platform_device *pdev)
	521	{
	522	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
119f5e44	523
9f5132ae	524	gpiochip_remove(&p->gpio_chip);
119f5e44	525
df0c6c80	526	pm_runtime_disable(&pdev->dev);
119f5e44 MD	527	return 0;
	528	}
	529
	530	static struct platform_driver gpio_rcar_device_driver = {
	531	.probe = gpio_rcar_probe,
	532	.remove = gpio_rcar_remove,
	533	.driver = {
	534	.name = "gpio_rcar",
159f8a02	535	.of_match_table = of_match_ptr(gpio_rcar_of_table),
119f5e44 MD	536	}
	537	};
	538
	539	module_platform_driver(gpio_rcar_device_driver);
	540
	541	MODULE_AUTHOR("Magnus Damm");
	542	MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
	543	MODULE_LICENSE("GPL v2");