[mirror_ubuntu-kernels.git] / drivers / gpio / gpio-rcar.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Renesas R-Car GPIO Support
 *
 *  Copyright (C) 2014 Renesas Electronics Corporation
 *  Copyright (C) 2013 Magnus Damm
 */

#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/slab.h>

struct gpio_rcar_bank_info {
	u32 iointsel;
	u32 inoutsel;
	u32 outdt;
	u32 posneg;
	u32 edglevel;
	u32 bothedge;
	u32 intmsk;
};

struct gpio_rcar_priv {
	void __iomem *base;
	spinlock_t lock;
	struct device *dev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	unsigned int irq_parent;
	atomic_t wakeup_path;
	bool has_outdtsel;
	bool has_both_edge_trigger;
	struct gpio_rcar_bank_info bank_info;
};

#define IOINTSEL 0x00	/* General IO/Interrupt Switching Register */
#define INOUTSEL 0x04	/* General Input/Output Switching Register */
#define OUTDT 0x08	/* General Output Register */
#define INDT 0x0c	/* General Input Register */
#define INTDT 0x10	/* Interrupt Display Register */
#define INTCLR 0x14	/* Interrupt Clear Register */
#define INTMSK 0x18	/* Interrupt Mask Register */
#define MSKCLR 0x1c	/* Interrupt Mask Clear Register */
#define POSNEG 0x20	/* Positive/Negative Logic Select Register */
#define EDGLEVEL 0x24	/* Edge/level Select Register */
#define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
#define OUTDTSEL 0x40	/* Output Data Select Register */
#define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */

#define RCAR_MAX_GPIO_PER_BANK		32

static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
{
	return ioread32(p->base + offs);
}

static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
				   u32 value)
{
	iowrite32(value, p->base + offs);
}

static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
				 int bit, bool value)
{
	u32 tmp = gpio_rcar_read(p, offs);

	if (value)
		tmp |= BIT(bit);
	else
		tmp &= ~BIT(bit);

	gpio_rcar_write(p, offs, tmp);
}

static void gpio_rcar_irq_disable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_irq_enable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
						  unsigned int hwirq,
						  bool active_high_rising_edge,
						  bool level_trigger,
						  bool both)
{
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting Edge-Sensitive Interrupt Input Mode" and
	 * "Setting Level-Sensitive Interrupt Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive or negative logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);

	/* Configure edge or level trigger in EDGLEVEL */
	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);

	/* Select one edge or both edges in BOTHEDGE */
	if (p->has_both_edge_trigger)
		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);

	/* Select "Interrupt Input Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);

	/* Write INTCLR in case of edge trigger */
	if (!level_trigger)
		gpio_rcar_write(p, INTCLR, BIT(hwirq));

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	unsigned int hwirq = irqd_to_hwirq(d);

	dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
						      false);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
						      false);
		break;
	case IRQ_TYPE_EDGE_RISING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_BOTH:
		if (!p->has_both_edge_trigger)
			return -EINVAL;
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      true);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	int error;

	if (p->irq_parent) {
		error = irq_set_irq_wake(p->irq_parent, on);
		if (error) {
			dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
				p->irq_parent);
			p->irq_parent = 0;
		}
	}

	if (on)
		atomic_inc(&p->wakeup_path);
	else
		atomic_dec(&p->wakeup_path);

	return 0;
}

static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
{
	struct gpio_rcar_priv *p = dev_id;
	u32 pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = gpio_rcar_read(p, INTDT) &
			  gpio_rcar_read(p, INTMSK))) {
		offset = __ffs(pending);
		gpio_rcar_write(p, INTCLR, BIT(offset));
		generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
						    offset));
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
						       unsigned int gpio,
						       bool output)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting General Output Mode" and
	 * "Setting General Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, gpio, false);

	/* Select "General Input/Output Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);

	/* Select Input Mode or Output Mode in INOUTSEL */
	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);

	/* Select General Output Register to output data in OUTDTSEL */
	if (p->has_outdtsel && output)
		gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	int error;

	error = pm_runtime_get_sync(p->dev);
	if (error < 0)
		return error;

	error = pinctrl_gpio_request(chip->base + offset);
	if (error)
		pm_runtime_put(p->dev);

	return error;
}

static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);

	pinctrl_gpio_free(chip->base + offset);

	/*
	 * Set the GPIO as an input to ensure that the next GPIO request won't
	 * drive the GPIO pin as an output.
	 */
	gpio_rcar_config_general_input_output_mode(chip, offset, false);

	pm_runtime_put(p->dev);
}

static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);

	return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
}

static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
{
	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	return 0;
}

static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
{
	u32 bit = BIT(offset);

	/* testing on r8a7790 shows that INDT does not show correct pin state
	 * when configured as output, so use OUTDT in case of output pins */
	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
		return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
	else
		return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
}

static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&p->lock, flags);
	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	spin_unlock_irqrestore(&p->lock, flags);
}

static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
				   unsigned long *bits)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;
	u32 val, bankmask;

	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
	if (chip->valid_mask)
		bankmask &= chip->valid_mask[0];

	if (!bankmask)
		return;

	spin_lock_irqsave(&p->lock, flags);
	val = gpio_rcar_read(p, OUTDT);
	val &= ~bankmask;
	val |= (bankmask & bits[0]);
	gpio_rcar_write(p, OUTDT, val);
	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	gpio_rcar_set(chip, offset, value);
	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	return 0;
}

struct gpio_rcar_info {
	bool has_outdtsel;
	bool has_both_edge_trigger;
};

static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
	.has_outdtsel = false,
	.has_both_edge_trigger = false,
};

static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
	.has_outdtsel = true,
	.has_both_edge_trigger = true,
};

static const struct of_device_id gpio_rcar_of_table[] = {
	{
		.compatible = "renesas,gpio-r8a7743",
		/* RZ/G1 GPIO is identical to R-Car Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7790",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7791",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7792",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7793",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7794",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7795",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7796",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,rcar-gen1-gpio",
		.data = &gpio_rcar_info_gen1,
	}, {
		.compatible = "renesas,rcar-gen2-gpio",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,rcar-gen3-gpio",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-rcar",
		.data = &gpio_rcar_info_gen1,
	}, {
		/* Terminator */
	},
};

MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);

static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
{
	struct device_node *np = p->dev->of_node;
	const struct gpio_rcar_info *info;
	struct of_phandle_args args;
	int ret;

	info = of_device_get_match_data(p->dev);
	p->has_outdtsel = info->has_outdtsel;
	p->has_both_edge_trigger = info->has_both_edge_trigger;

	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;

	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
		dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
			 *npins, RCAR_MAX_GPIO_PER_BANK);
		*npins = RCAR_MAX_GPIO_PER_BANK;
	}

	return 0;
}

static int gpio_rcar_probe(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p;
	struct resource *io, *irq;
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	struct device *dev = &pdev->dev;
	const char *name = dev_name(dev);
	unsigned int npins;
	int ret;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p)
		return -ENOMEM;

	p->dev = dev;
	spin_lock_init(&p->lock);

	/* Get device configuration from DT node */
	ret = gpio_rcar_parse_dt(p, &npins);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, p);

	pm_runtime_enable(dev);

	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!irq) {
		dev_err(dev, "missing IRQ\n");
		ret = -EINVAL;
		goto err0;
	}

	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	p->base = devm_ioremap_resource(dev, io);
	if (IS_ERR(p->base)) {
		ret = PTR_ERR(p->base);
		goto err0;
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->request = gpio_rcar_request;
	gpio_chip->free = gpio_rcar_free;
	gpio_chip->get_direction = gpio_rcar_get_direction;
	gpio_chip->direction_input = gpio_rcar_direction_input;
	gpio_chip->get = gpio_rcar_get;
	gpio_chip->direction_output = gpio_rcar_direction_output;
	gpio_chip->set = gpio_rcar_set;
	gpio_chip->set_multiple = gpio_rcar_set_multiple;
	gpio_chip->label = name;
	gpio_chip->parent = dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = -1;
	gpio_chip->ngpio = npins;

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->parent_device = dev;
	irq_chip->irq_mask = gpio_rcar_irq_disable;
	irq_chip->irq_unmask = gpio_rcar_irq_enable;
	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
	irq_chip->flags	= IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;

	ret = gpiochip_add_data(gpio_chip, p);
	if (ret) {
		dev_err(dev, "failed to add GPIO controller\n");
		goto err0;
	}

	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "cannot add irqchip\n");
		goto err1;
	}

	p->irq_parent = irq->start;
	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
			     IRQF_SHARED, name, p)) {
		dev_err(dev, "failed to request IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	dev_info(dev, "driving %d GPIOs\n", npins);

	return 0;

err1:
	gpiochip_remove(gpio_chip);
err0:
	pm_runtime_disable(dev);
	return ret;
}

static int gpio_rcar_remove(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);

	gpiochip_remove(&p->gpio_chip);

	pm_runtime_disable(&pdev->dev);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int gpio_rcar_suspend(struct device *dev)
{
	struct gpio_rcar_priv *p = dev_get_drvdata(dev);

	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
	if (p->has_both_edge_trigger)
		p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);

	if (atomic_read(&p->wakeup_path))
		device_set_wakeup_path(dev);

	return 0;
}

static int gpio_rcar_resume(struct device *dev)
{
	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	unsigned int offset;
	u32 mask;

	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
		if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
			continue;

		mask = BIT(offset);
		/* I/O pin */
		if (!(p->bank_info.iointsel & mask)) {
			if (p->bank_info.inoutsel & mask)
				gpio_rcar_direction_output(
					&p->gpio_chip, offset,
					!!(p->bank_info.outdt & mask));
			else
				gpio_rcar_direction_input(&p->gpio_chip,
							  offset);
		} else {
			/* Interrupt pin */
			gpio_rcar_config_interrupt_input_mode(
				p,
				offset,
				!(p->bank_info.posneg & mask),
				!(p->bank_info.edglevel & mask),
				!!(p->bank_info.bothedge & mask));

			if (p->bank_info.intmsk & mask)
				gpio_rcar_write(p, MSKCLR, mask);
		}
	}

	return 0;
}
#endif /* CONFIG_PM_SLEEP*/

static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);

static struct platform_driver gpio_rcar_device_driver = {
	.probe		= gpio_rcar_probe,
	.remove		= gpio_rcar_remove,
	.driver		= {
		.name	= "gpio_rcar",
		.pm     = &gpio_rcar_pm_ops,
		.of_match_table = of_match_ptr(gpio_rcar_of_table),
	}
};

module_platform_driver(gpio_rcar_device_driver);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
8b37eb74	1	// SPDX-License-Identifier: GPL-2.0
119f5e44 MD	2	/*
	3	* Renesas R-Car GPIO Support
	4	*
1fd2b49d	5	* Copyright (C) 2014 Renesas Electronics Corporation
119f5e44	6	* Copyright (C) 2013 Magnus Damm
119f5e44 MD	7	*/
	8
	9	#include <linux/err.h>
4b1d8007	10	#include <linux/gpio/driver.h>
119f5e44 MD	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/io.h>
	14	#include <linux/ioport.h>
	15	#include <linux/irq.h>
119f5e44	16	#include <linux/module.h>
bd0bf468	17	#include <linux/of.h>
f9f2a6fe	18	#include <linux/of_device.h>
dc3465a9	19	#include <linux/pinctrl/consumer.h>
119f5e44	20	#include <linux/platform_device.h>
df0c6c80	21	#include <linux/pm_runtime.h>
119f5e44 MD	22	#include <linux/spinlock.h>
	23	#include <linux/slab.h>
	24
51750fb1 HD	25	struct gpio_rcar_bank_info {
	26	u32 iointsel;
	27	u32 inoutsel;
	28	u32 outdt;
	29	u32 posneg;
	30	u32 edglevel;
	31	u32 bothedge;
	32	u32 intmsk;
	33	};
	34
119f5e44 MD	35	struct gpio_rcar_priv {
	36	void __iomem *base;
	37	spinlock_t lock;
a53f7953	38	struct device *dev;
119f5e44 MD	39	struct gpio_chip gpio_chip;
119f5e44 MD	40	struct irq_chip irq_chip;
8b092be9	41	unsigned int irq_parent;
9ac79ba9	42	atomic_t wakeup_path;
3ae4f3aa	43	bool has_outdtsel;
8b092be9	44	bool has_both_edge_trigger;
51750fb1	45	struct gpio_rcar_bank_info bank_info;
119f5e44 MD	46	};
119f5e44 MD	47
3dc1e685 GU	48	#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
	49	#define INOUTSEL 0x04 /* General Input/Output Switching Register */
	50	#define OUTDT 0x08 /* General Output Register */
	51	#define INDT 0x0c /* General Input Register */
	52	#define INTDT 0x10 /* Interrupt Display Register */
	53	#define INTCLR 0x14 /* Interrupt Clear Register */
	54	#define INTMSK 0x18 /* Interrupt Mask Register */
	55	#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
	56	#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
	57	#define EDGLEVEL 0x24 /* Edge/level Select Register */
	58	#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
3ae4f3aa	59	#define OUTDTSEL 0x40 /* Output Data Select Register */
3dc1e685	60	#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
119f5e44	61
159f8a02 LP	62	#define RCAR_MAX_GPIO_PER_BANK 32
159f8a02 LP	63
119f5e44 MD	64	static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
	65	{
	66	return ioread32(p->base + offs);
	67	}
	68
	69	static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
	70	u32 value)
	71	{
	72	iowrite32(value, p->base + offs);
	73	}
	74
	75	static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
	76	int bit, bool value)
	77	{
	78	u32 tmp = gpio_rcar_read(p, offs);
	79
	80	if (value)
	81	tmp \|= BIT(bit);
	82	else
	83	tmp &= ~BIT(bit);
	84
	85	gpio_rcar_write(p, offs, tmp);
	86	}
	87
	88	static void gpio_rcar_irq_disable(struct irq_data *d)
	89	{
c7f3c5d3	90	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	91	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	92
	93	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
	94	}
	95
	96	static void gpio_rcar_irq_enable(struct irq_data *d)
	97	{
c7f3c5d3	98	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	99	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	100
	101	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
	102	}
	103
	104	static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
	105	unsigned int hwirq,
	106	bool active_high_rising_edge,
7e1092b5 SH	107	bool level_trigger,
7e1092b5 SH	108	bool both)
119f5e44 MD	109	{
	110	unsigned long flags;
	111
	112	/* follow steps in the GPIO documentation for
	113	* "Setting Edge-Sensitive Interrupt Input Mode" and
	114	* "Setting Level-Sensitive Interrupt Input Mode"
	115	*/
	116
	117	spin_lock_irqsave(&p->lock, flags);
	118
	119	/* Configure postive or negative logic in POSNEG */
	120	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
	121
	122	/* Configure edge or level trigger in EDGLEVEL */
	123	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
	124
7e1092b5	125	/* Select one edge or both edges in BOTHEDGE */
8b092be9	126	if (p->has_both_edge_trigger)
7e1092b5 SH	127	gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
7e1092b5 SH	128
119f5e44 MD	129	/* Select "Interrupt Input Mode" in IOINTSEL */
	130	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
	131
	132	/* Write INTCLR in case of edge trigger */
	133	if (!level_trigger)
	134	gpio_rcar_write(p, INTCLR, BIT(hwirq));
	135
	136	spin_unlock_irqrestore(&p->lock, flags);
	137	}
	138
	139	static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
	140	{
c7f3c5d3	141	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	142	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	143	unsigned int hwirq = irqd_to_hwirq(d);
119f5e44 MD	144
a53f7953	145	dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
119f5e44 MD	146
	147	switch (type & IRQ_TYPE_SENSE_MASK) {
	148	case IRQ_TYPE_LEVEL_HIGH:
7e1092b5 SH	149	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
7e1092b5 SH	150	false);
119f5e44 MD	151	break;
119f5e44 MD	152	case IRQ_TYPE_LEVEL_LOW:
7e1092b5 SH	153	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
7e1092b5 SH	154	false);
119f5e44 MD	155	break;
119f5e44 MD	156	case IRQ_TYPE_EDGE_RISING:
7e1092b5 SH	157	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
7e1092b5 SH	158	false);
119f5e44 MD	159	break;
119f5e44 MD	160	case IRQ_TYPE_EDGE_FALLING:
7e1092b5 SH	161	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
	162	false);
	163	break;
	164	case IRQ_TYPE_EDGE_BOTH:
8b092be9	165	if (!p->has_both_edge_trigger)
7e1092b5 SH	166	return -EINVAL;
	167	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
	168	true);
119f5e44 MD	169	break;
	170	default:
	171	return -EINVAL;
	172	}
	173	return 0;
	174	}
	175
ab82fa7d GU	176	static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
	177	{
	178	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	179	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
501ef0f9 GU	180	int error;
	181
	182	if (p->irq_parent) {
	183	error = irq_set_irq_wake(p->irq_parent, on);
	184	if (error) {
a53f7953	185	dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
501ef0f9 GU	186	p->irq_parent);
	187	p->irq_parent = 0;
	188	}
	189	}
ab82fa7d	190
ab82fa7d	191	if (on)
9ac79ba9	192	atomic_inc(&p->wakeup_path);
ab82fa7d	193	else
9ac79ba9	194	atomic_dec(&p->wakeup_path);
ab82fa7d GU	195
	196	return 0;
	197	}
	198
119f5e44 MD	199	static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
	200	{
	201	struct gpio_rcar_priv *p = dev_id;
	202	u32 pending;
	203	unsigned int offset, irqs_handled = 0;
	204
8808b64d VB	205	while ((pending = gpio_rcar_read(p, INTDT) &
8808b64d VB	206	gpio_rcar_read(p, INTMSK))) {
119f5e44 MD	207	offset = __ffs(pending);
119f5e44 MD	208	gpio_rcar_write(p, INTCLR, BIT(offset));
f0fbe7bc	209	generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
c7f3c5d3	210	offset));
119f5e44 MD	211	irqs_handled++;
	212	}
	213
	214	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	215	}
	216
119f5e44 MD	217	static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
	218	unsigned int gpio,
	219	bool output)
	220	{
c7b6f457	221	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	222	unsigned long flags;
	223
	224	/* follow steps in the GPIO documentation for
	225	* "Setting General Output Mode" and
	226	* "Setting General Input Mode"
	227	*/
	228
	229	spin_lock_irqsave(&p->lock, flags);
	230
	231	/* Configure postive logic in POSNEG */
	232	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
	233
	234	/* Select "General Input/Output Mode" in IOINTSEL */
	235	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
	236
	237	/* Select Input Mode or Output Mode in INOUTSEL */
	238	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
	239
3ae4f3aa VZ	240	/* Select General Output Register to output data in OUTDTSEL */
	241	if (p->has_outdtsel && output)
	242	gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
	243
119f5e44 MD	244	spin_unlock_irqrestore(&p->lock, flags);
	245	}
	246
dc3465a9 LP	247	static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
dc3465a9 LP	248	{
2d65472b GU	249	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	250	int error;
	251
a53f7953	252	error = pm_runtime_get_sync(p->dev);
2d65472b GU	253	if (error < 0)
	254	return error;
	255
a9a1d2a7	256	error = pinctrl_gpio_request(chip->base + offset);
2d65472b	257	if (error)
a53f7953	258	pm_runtime_put(p->dev);
2d65472b GU	259
2d65472b GU	260	return error;
dc3465a9 LP	261	}
	262
	263	static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
	264	{
2d65472b GU	265	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
2d65472b GU	266
a9a1d2a7	267	pinctrl_gpio_free(chip->base + offset);
dc3465a9	268
ce0e2c60 LW	269	/*
ce0e2c60 LW	270	* Set the GPIO as an input to ensure that the next GPIO request won't
dc3465a9 LP	271	* drive the GPIO pin as an output.
	272	*/
	273	gpio_rcar_config_general_input_output_mode(chip, offset, false);
2d65472b	274
a53f7953	275	pm_runtime_put(p->dev);
dc3465a9 LP	276	}
dc3465a9 LP	277
ad817297 GU	278	static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
	279	{
	280	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	281
	282	return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
	283	}
	284
119f5e44 MD	285	static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
	286	{
	287	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	288	return 0;
	289	}
	290
	291	static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
	292	{
ae9550f6 MD	293	u32 bit = BIT(offset);
	294
	295	/* testing on r8a7790 shows that INDT does not show correct pin state
	296	* when configured as output, so use OUTDT in case of output pins */
c7b6f457 LW	297	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
c7b6f457 LW	298	return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
ae9550f6	299	else
c7b6f457	300	return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
119f5e44 MD	301	}
	302
	303	static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
	304	{
c7b6f457	305	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	306	unsigned long flags;
	307
	308	spin_lock_irqsave(&p->lock, flags);
	309	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	310	spin_unlock_irqrestore(&p->lock, flags);
	311	}
	312
dbb763b8 GU	313	static void gpio_rcar_set_multiple(struct gpio_chip chip, unsigned long mask,
	314	unsigned long *bits)
	315	{
	316	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	317	unsigned long flags;
	318	u32 val, bankmask;
	319
	320	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
496069b8 BD	321	if (chip->valid_mask)
	322	bankmask &= chip->valid_mask[0];
	323
dbb763b8 GU	324	if (!bankmask)
	325	return;
	326
	327	spin_lock_irqsave(&p->lock, flags);
	328	val = gpio_rcar_read(p, OUTDT);
	329	val &= ~bankmask;
	330	val \|= (bankmask & bits[0]);
	331	gpio_rcar_write(p, OUTDT, val);
	332	spin_unlock_irqrestore(&p->lock, flags);
	333	}
	334
119f5e44 MD	335	static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
	336	int value)
	337	{
	338	/* write GPIO value to output before selecting output mode of pin */
	339	gpio_rcar_set(chip, offset, value);
	340	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	341	return 0;
	342	}
	343
850dfe17	344	struct gpio_rcar_info {
3ae4f3aa	345	bool has_outdtsel;
850dfe17 LP	346	bool has_both_edge_trigger;
	347	};
	348
1fd2b49d	349	static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
3ae4f3aa	350	.has_outdtsel = false,
1fd2b49d HN	351	.has_both_edge_trigger = false,
	352	};
	353
	354	static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
3ae4f3aa	355	.has_outdtsel = true,
1fd2b49d HN	356	.has_both_edge_trigger = true,
	357	};
	358
850dfe17 LP	359	static const struct of_device_id gpio_rcar_of_table[] = {
850dfe17 LP	360	{
85bb4646 BD	361	.compatible = "renesas,gpio-r8a7743",
	362	/* RZ/G1 GPIO is identical to R-Car Gen2. */
	363	.data = &gpio_rcar_info_gen2,
	364	}, {
850dfe17	365	.compatible = "renesas,gpio-r8a7790",
1fd2b49d	366	.data = &gpio_rcar_info_gen2,
850dfe17 LP	367	}, {
850dfe17 LP	368	.compatible = "renesas,gpio-r8a7791",
1fd2b49d	369	.data = &gpio_rcar_info_gen2,
e79c5830 SS	370	}, {
	371	.compatible = "renesas,gpio-r8a7792",
	372	.data = &gpio_rcar_info_gen2,
1fd2b49d HN	373	}, {
	374	.compatible = "renesas,gpio-r8a7793",
	375	.data = &gpio_rcar_info_gen2,
	376	}, {
	377	.compatible = "renesas,gpio-r8a7794",
	378	.data = &gpio_rcar_info_gen2,
8cd14702 UH	379	}, {
	380	.compatible = "renesas,gpio-r8a7795",
	381	/* Gen3 GPIO is identical to Gen2. */
	382	.data = &gpio_rcar_info_gen2,
5d2f1d6e SH	383	}, {
	384	.compatible = "renesas,gpio-r8a7796",
	385	/* Gen3 GPIO is identical to Gen2. */
	386	.data = &gpio_rcar_info_gen2,
dbd1dad2 SH	387	}, {
	388	.compatible = "renesas,rcar-gen1-gpio",
	389	.data = &gpio_rcar_info_gen1,
	390	}, {
	391	.compatible = "renesas,rcar-gen2-gpio",
	392	.data = &gpio_rcar_info_gen2,
	393	}, {
	394	.compatible = "renesas,rcar-gen3-gpio",
	395	/* Gen3 GPIO is identical to Gen2. */
	396	.data = &gpio_rcar_info_gen2,
850dfe17 LP	397	}, {
850dfe17 LP	398	.compatible = "renesas,gpio-rcar",
1fd2b49d	399	.data = &gpio_rcar_info_gen1,
850dfe17 LP	400	}, {
	401	/* Terminator */
	402	},
	403	};
	404
	405	MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
	406
8b092be9	407	static int gpio_rcar_parse_dt(struct gpio_rcar_priv p, unsigned int npins)
159f8a02	408	{
a53f7953	409	struct device_node *np = p->dev->of_node;
8b092be9	410	const struct gpio_rcar_info *info;
159f8a02 LP	411	struct of_phandle_args args;
159f8a02 LP	412	int ret;
159f8a02	413
a53f7953	414	info = of_device_get_match_data(p->dev);
3ae4f3aa VZ	415	p->has_outdtsel = info->has_outdtsel;
3ae4f3aa VZ	416	p->has_both_edge_trigger = info->has_both_edge_trigger;
850dfe17	417
8b092be9 GU	418	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
8b092be9 GU	419	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
850dfe17	420
8b092be9	421	if (npins == 0 \|\| npins > RCAR_MAX_GPIO_PER_BANK) {
a53f7953 VZ	422	dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
a53f7953 VZ	423	*npins, RCAR_MAX_GPIO_PER_BANK);
8b092be9	424	*npins = RCAR_MAX_GPIO_PER_BANK;
159f8a02	425	}
850dfe17 LP	426
850dfe17 LP	427	return 0;
159f8a02 LP	428	}
159f8a02 LP	429
119f5e44 MD	430	static int gpio_rcar_probe(struct platform_device *pdev)
119f5e44 MD	431	{
119f5e44 MD	432	struct gpio_rcar_priv *p;
	433	struct resource io, irq;
	434	struct gpio_chip *gpio_chip;
	435	struct irq_chip *irq_chip;
b22978fc GU	436	struct device *dev = &pdev->dev;
b22978fc GU	437	const char *name = dev_name(dev);
8b092be9	438	unsigned int npins;
119f5e44 MD	439	int ret;
119f5e44 MD	440
b22978fc	441	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
7d82bf34 GU	442	if (!p)
7d82bf34 GU	443	return -ENOMEM;
119f5e44	444
a53f7953	445	p->dev = dev;
119f5e44 MD	446	spin_lock_init(&p->lock);
119f5e44 MD	447
8b092be9 GU	448	/* Get device configuration from DT node */
8b092be9 GU	449	ret = gpio_rcar_parse_dt(p, &npins);
850dfe17 LP	450	if (ret < 0)
850dfe17 LP	451	return ret;
159f8a02 LP	452
	453	platform_set_drvdata(pdev, p);
	454
df0c6c80	455	pm_runtime_enable(dev);
df0c6c80	456
119f5e44	457	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
5a24d4b6 SS	458	if (!irq) {
5a24d4b6 SS	459	dev_err(dev, "missing IRQ\n");
119f5e44 MD	460	ret = -EINVAL;
	461	goto err0;
	462	}
	463
5a24d4b6 SS	464	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	465	p->base = devm_ioremap_resource(dev, io);
	466	if (IS_ERR(p->base)) {
	467	ret = PTR_ERR(p->base);
119f5e44 MD	468	goto err0;
	469	}
	470
	471	gpio_chip = &p->gpio_chip;
dc3465a9 LP	472	gpio_chip->request = gpio_rcar_request;
dc3465a9 LP	473	gpio_chip->free = gpio_rcar_free;
ad817297	474	gpio_chip->get_direction = gpio_rcar_get_direction;
119f5e44 MD	475	gpio_chip->direction_input = gpio_rcar_direction_input;
	476	gpio_chip->get = gpio_rcar_get;
	477	gpio_chip->direction_output = gpio_rcar_direction_output;
	478	gpio_chip->set = gpio_rcar_set;
dbb763b8	479	gpio_chip->set_multiple = gpio_rcar_set_multiple;
119f5e44	480	gpio_chip->label = name;
58383c78	481	gpio_chip->parent = dev;
119f5e44	482	gpio_chip->owner = THIS_MODULE;
8b092be9 GU	483	gpio_chip->base = -1;
8b092be9 GU	484	gpio_chip->ngpio = npins;
119f5e44 MD	485
	486	irq_chip = &p->irq_chip;
	487	irq_chip->name = name;
47bd38a3	488	irq_chip->parent_device = dev;
119f5e44 MD	489	irq_chip->irq_mask = gpio_rcar_irq_disable;
119f5e44 MD	490	irq_chip->irq_unmask = gpio_rcar_irq_enable;
119f5e44	491	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
ab82fa7d GU	492	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
ab82fa7d GU	493	irq_chip->flags = IRQCHIP_SET_TYPE_MASKED \| IRQCHIP_MASK_ON_SUSPEND;
119f5e44	494
c7b6f457	495	ret = gpiochip_add_data(gpio_chip, p);
c7f3c5d3 GU	496	if (ret) {
c7f3c5d3 GU	497	dev_err(dev, "failed to add GPIO controller\n");
0c8aab8e	498	goto err0;
119f5e44 MD	499	}
119f5e44 MD	500
8b092be9 GU	501	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
8b092be9 GU	502	IRQ_TYPE_NONE);
c7f3c5d3 GU	503	if (ret) {
	504	dev_err(dev, "cannot add irqchip\n");
	505	goto err1;
	506	}
	507
ab82fa7d	508	p->irq_parent = irq->start;
b22978fc GU	509	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
	510	IRQF_SHARED, name, p)) {
	511	dev_err(dev, "failed to request IRQ\n");
119f5e44 MD	512	ret = -ENOENT;
	513	goto err1;
	514	}
	515
8b092be9	516	dev_info(dev, "driving %d GPIOs\n", npins);
dc3465a9	517
119f5e44 MD	518	return 0;
	519
	520	err1:
4d84b9e4	521	gpiochip_remove(gpio_chip);
119f5e44	522	err0:
df0c6c80	523	pm_runtime_disable(dev);
119f5e44 MD	524	return ret;
	525	}
	526
	527	static int gpio_rcar_remove(struct platform_device *pdev)
	528	{
	529	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
119f5e44	530
9f5132ae	531	gpiochip_remove(&p->gpio_chip);
119f5e44	532
df0c6c80	533	pm_runtime_disable(&pdev->dev);
119f5e44 MD	534	return 0;
	535	}
	536
51750fb1 HD	537	#ifdef CONFIG_PM_SLEEP
	538	static int gpio_rcar_suspend(struct device *dev)
	539	{
	540	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	541
	542	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
	543	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
	544	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
	545	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
	546	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
	547	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
	548	if (p->has_both_edge_trigger)
	549	p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
	550
9ac79ba9 GU	551	if (atomic_read(&p->wakeup_path))
	552	device_set_wakeup_path(dev);
	553
51750fb1 HD	554	return 0;
	555	}
	556
	557	static int gpio_rcar_resume(struct device *dev)
	558	{
	559	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	560	unsigned int offset;
	561	u32 mask;
	562
	563	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
496069b8 BD	564	if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
	565	continue;
	566
51750fb1 HD	567	mask = BIT(offset);
	568	/* I/O pin */
	569	if (!(p->bank_info.iointsel & mask)) {
	570	if (p->bank_info.inoutsel & mask)
	571	gpio_rcar_direction_output(
	572	&p->gpio_chip, offset,
	573	!!(p->bank_info.outdt & mask));
	574	else
	575	gpio_rcar_direction_input(&p->gpio_chip,
	576	offset);
	577	} else {
	578	/* Interrupt pin */
	579	gpio_rcar_config_interrupt_input_mode(
	580	p,
	581	offset,
	582	!(p->bank_info.posneg & mask),
	583	!(p->bank_info.edglevel & mask),
	584	!!(p->bank_info.bothedge & mask));
	585
	586	if (p->bank_info.intmsk & mask)
	587	gpio_rcar_write(p, MSKCLR, mask);
	588	}
	589	}
	590
	591	return 0;
	592	}
	593	#endif /* CONFIG_PM_SLEEP*/
	594
	595	static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
	596
119f5e44 MD	597	static struct platform_driver gpio_rcar_device_driver = {
	598	.probe = gpio_rcar_probe,
	599	.remove = gpio_rcar_remove,
	600	.driver = {
	601	.name = "gpio_rcar",
51750fb1	602	.pm = &gpio_rcar_pm_ops,
159f8a02	603	.of_match_table = of_match_ptr(gpio_rcar_of_table),
119f5e44 MD	604	}
	605	};
	606
	607	module_platform_driver(gpio_rcar_device_driver);
	608
	609	MODULE_AUTHOR("Magnus Damm");
	610	MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
	611	MODULE_LICENSE("GPL v2");