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119f5e44
MD
1/*
2 * Renesas R-Car GPIO Support
3 *
1fd2b49d 4 * Copyright (C) 2014 Renesas Electronics Corporation
119f5e44
MD
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
ab82fa7d 17#include <linux/clk.h>
119f5e44
MD
18#include <linux/err.h>
19#include <linux/gpio.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/ioport.h>
24#include <linux/irq.h>
119f5e44 25#include <linux/module.h>
bd0bf468 26#include <linux/of.h>
dc3465a9 27#include <linux/pinctrl/consumer.h>
119f5e44 28#include <linux/platform_device.h>
df0c6c80 29#include <linux/pm_runtime.h>
119f5e44
MD
30#include <linux/spinlock.h>
31#include <linux/slab.h>
32
33struct gpio_rcar_priv {
34 void __iomem *base;
35 spinlock_t lock;
119f5e44
MD
36 struct platform_device *pdev;
37 struct gpio_chip gpio_chip;
38 struct irq_chip irq_chip;
ab82fa7d 39 struct clk *clk;
8b092be9
GU
40 unsigned int irq_parent;
41 bool has_both_edge_trigger;
e1fef9e2 42 bool needs_clk;
119f5e44
MD
43};
44
3dc1e685
GU
45#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
46#define INOUTSEL 0x04 /* General Input/Output Switching Register */
47#define OUTDT 0x08 /* General Output Register */
48#define INDT 0x0c /* General Input Register */
49#define INTDT 0x10 /* Interrupt Display Register */
50#define INTCLR 0x14 /* Interrupt Clear Register */
51#define INTMSK 0x18 /* Interrupt Mask Register */
52#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
53#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
54#define EDGLEVEL 0x24 /* Edge/level Select Register */
55#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
56#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
119f5e44 57
159f8a02
LP
58#define RCAR_MAX_GPIO_PER_BANK 32
59
119f5e44
MD
60static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
61{
62 return ioread32(p->base + offs);
63}
64
65static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
66 u32 value)
67{
68 iowrite32(value, p->base + offs);
69}
70
71static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
72 int bit, bool value)
73{
74 u32 tmp = gpio_rcar_read(p, offs);
75
76 if (value)
77 tmp |= BIT(bit);
78 else
79 tmp &= ~BIT(bit);
80
81 gpio_rcar_write(p, offs, tmp);
82}
83
84static void gpio_rcar_irq_disable(struct irq_data *d)
85{
c7f3c5d3 86 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457 87 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44
MD
88
89 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
90}
91
92static void gpio_rcar_irq_enable(struct irq_data *d)
93{
c7f3c5d3 94 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457 95 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44
MD
96
97 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
98}
99
100static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
101 unsigned int hwirq,
102 bool active_high_rising_edge,
7e1092b5
SH
103 bool level_trigger,
104 bool both)
119f5e44
MD
105{
106 unsigned long flags;
107
108 /* follow steps in the GPIO documentation for
109 * "Setting Edge-Sensitive Interrupt Input Mode" and
110 * "Setting Level-Sensitive Interrupt Input Mode"
111 */
112
113 spin_lock_irqsave(&p->lock, flags);
114
115 /* Configure postive or negative logic in POSNEG */
116 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
117
118 /* Configure edge or level trigger in EDGLEVEL */
119 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
120
7e1092b5 121 /* Select one edge or both edges in BOTHEDGE */
8b092be9 122 if (p->has_both_edge_trigger)
7e1092b5
SH
123 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
124
119f5e44
MD
125 /* Select "Interrupt Input Mode" in IOINTSEL */
126 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
127
128 /* Write INTCLR in case of edge trigger */
129 if (!level_trigger)
130 gpio_rcar_write(p, INTCLR, BIT(hwirq));
131
132 spin_unlock_irqrestore(&p->lock, flags);
133}
134
135static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
136{
c7f3c5d3 137 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457 138 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44
MD
139 unsigned int hwirq = irqd_to_hwirq(d);
140
141 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
142
143 switch (type & IRQ_TYPE_SENSE_MASK) {
144 case IRQ_TYPE_LEVEL_HIGH:
7e1092b5
SH
145 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
146 false);
119f5e44
MD
147 break;
148 case IRQ_TYPE_LEVEL_LOW:
7e1092b5
SH
149 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
150 false);
119f5e44
MD
151 break;
152 case IRQ_TYPE_EDGE_RISING:
7e1092b5
SH
153 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
154 false);
119f5e44
MD
155 break;
156 case IRQ_TYPE_EDGE_FALLING:
7e1092b5
SH
157 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
158 false);
159 break;
160 case IRQ_TYPE_EDGE_BOTH:
8b092be9 161 if (!p->has_both_edge_trigger)
7e1092b5
SH
162 return -EINVAL;
163 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
164 true);
119f5e44
MD
165 break;
166 default:
167 return -EINVAL;
168 }
169 return 0;
170}
171
ab82fa7d
GU
172static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
173{
174 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457 175 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
501ef0f9
GU
176 int error;
177
178 if (p->irq_parent) {
179 error = irq_set_irq_wake(p->irq_parent, on);
180 if (error) {
181 dev_dbg(&p->pdev->dev,
182 "irq %u doesn't support irq_set_wake\n",
183 p->irq_parent);
184 p->irq_parent = 0;
185 }
186 }
ab82fa7d
GU
187
188 if (!p->clk)
189 return 0;
190
191 if (on)
192 clk_enable(p->clk);
193 else
194 clk_disable(p->clk);
195
196 return 0;
197}
198
b26a719b
GU
199static void gpio_rcar_irq_bus_lock(struct irq_data *d)
200{
201 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
202 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
203
204 pm_runtime_get_sync(&p->pdev->dev);
205}
206
207static void gpio_rcar_irq_bus_sync_unlock(struct irq_data *d)
208{
209 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
210 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
211
212 pm_runtime_put(&p->pdev->dev);
213}
214
215
216static int gpio_rcar_irq_request_resources(struct irq_data *d)
217{
218 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
219 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
220 int error;
221
222 error = pm_runtime_get_sync(&p->pdev->dev);
223 if (error < 0)
224 return error;
225
226 return 0;
227}
228
229static void gpio_rcar_irq_release_resources(struct irq_data *d)
230{
231 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
232 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
233
234 pm_runtime_put(&p->pdev->dev);
235}
236
119f5e44
MD
237static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
238{
239 struct gpio_rcar_priv *p = dev_id;
240 u32 pending;
241 unsigned int offset, irqs_handled = 0;
242
8808b64d
VB
243 while ((pending = gpio_rcar_read(p, INTDT) &
244 gpio_rcar_read(p, INTMSK))) {
119f5e44
MD
245 offset = __ffs(pending);
246 gpio_rcar_write(p, INTCLR, BIT(offset));
c7f3c5d3
GU
247 generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
248 offset));
119f5e44
MD
249 irqs_handled++;
250 }
251
252 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
253}
254
119f5e44
MD
255static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
256 unsigned int gpio,
257 bool output)
258{
c7b6f457 259 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44
MD
260 unsigned long flags;
261
262 /* follow steps in the GPIO documentation for
263 * "Setting General Output Mode" and
264 * "Setting General Input Mode"
265 */
266
267 spin_lock_irqsave(&p->lock, flags);
268
269 /* Configure postive logic in POSNEG */
270 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
271
272 /* Select "General Input/Output Mode" in IOINTSEL */
273 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
274
275 /* Select Input Mode or Output Mode in INOUTSEL */
276 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
277
278 spin_unlock_irqrestore(&p->lock, flags);
279}
280
dc3465a9
LP
281static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
282{
c7b6f457 283 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
65194cb1
GU
284 int error;
285
286 error = pm_runtime_get_sync(&p->pdev->dev);
287 if (error < 0)
288 return error;
289
290 error = pinctrl_request_gpio(chip->base + offset);
291 if (error)
292 pm_runtime_put(&p->pdev->dev);
293
294 return error;
dc3465a9
LP
295}
296
297static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
298{
c7b6f457 299 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
65194cb1 300
dc3465a9
LP
301 pinctrl_free_gpio(chip->base + offset);
302
303 /* Set the GPIO as an input to ensure that the next GPIO request won't
304 * drive the GPIO pin as an output.
305 */
306 gpio_rcar_config_general_input_output_mode(chip, offset, false);
65194cb1
GU
307
308 pm_runtime_put(&p->pdev->dev);
dc3465a9
LP
309}
310
119f5e44
MD
311static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
312{
313 gpio_rcar_config_general_input_output_mode(chip, offset, false);
314 return 0;
315}
316
317static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
318{
ae9550f6
MD
319 u32 bit = BIT(offset);
320
321 /* testing on r8a7790 shows that INDT does not show correct pin state
322 * when configured as output, so use OUTDT in case of output pins */
c7b6f457
LW
323 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
324 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
ae9550f6 325 else
c7b6f457 326 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
119f5e44
MD
327}
328
329static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
330{
c7b6f457 331 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44
MD
332 unsigned long flags;
333
334 spin_lock_irqsave(&p->lock, flags);
335 gpio_rcar_modify_bit(p, OUTDT, offset, value);
336 spin_unlock_irqrestore(&p->lock, flags);
337}
338
339static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
340 int value)
341{
342 /* write GPIO value to output before selecting output mode of pin */
343 gpio_rcar_set(chip, offset, value);
344 gpio_rcar_config_general_input_output_mode(chip, offset, true);
345 return 0;
346}
347
850dfe17
LP
348struct gpio_rcar_info {
349 bool has_both_edge_trigger;
e1fef9e2 350 bool needs_clk;
850dfe17
LP
351};
352
1fd2b49d
HN
353static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
354 .has_both_edge_trigger = false,
e1fef9e2 355 .needs_clk = false,
1fd2b49d
HN
356};
357
358static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
359 .has_both_edge_trigger = true,
e1fef9e2 360 .needs_clk = true,
1fd2b49d
HN
361};
362
850dfe17
LP
363static const struct of_device_id gpio_rcar_of_table[] = {
364 {
365 .compatible = "renesas,gpio-r8a7790",
1fd2b49d 366 .data = &gpio_rcar_info_gen2,
850dfe17
LP
367 }, {
368 .compatible = "renesas,gpio-r8a7791",
1fd2b49d
HN
369 .data = &gpio_rcar_info_gen2,
370 }, {
371 .compatible = "renesas,gpio-r8a7793",
372 .data = &gpio_rcar_info_gen2,
373 }, {
374 .compatible = "renesas,gpio-r8a7794",
375 .data = &gpio_rcar_info_gen2,
8cd14702
UH
376 }, {
377 .compatible = "renesas,gpio-r8a7795",
378 /* Gen3 GPIO is identical to Gen2. */
379 .data = &gpio_rcar_info_gen2,
850dfe17
LP
380 }, {
381 .compatible = "renesas,gpio-rcar",
1fd2b49d 382 .data = &gpio_rcar_info_gen1,
850dfe17
LP
383 }, {
384 /* Terminator */
385 },
386};
387
388MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
389
8b092be9 390static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
159f8a02 391{
159f8a02 392 struct device_node *np = p->pdev->dev.of_node;
8b092be9
GU
393 const struct of_device_id *match;
394 const struct gpio_rcar_info *info;
159f8a02
LP
395 struct of_phandle_args args;
396 int ret;
159f8a02 397
8b092be9
GU
398 match = of_match_node(gpio_rcar_of_table, np);
399 if (!match)
400 return -EINVAL;
850dfe17 401
8b092be9 402 info = match->data;
850dfe17 403
8b092be9
GU
404 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
405 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
406 p->has_both_edge_trigger = info->has_both_edge_trigger;
e1fef9e2 407 p->needs_clk = info->needs_clk;
850dfe17 408
8b092be9 409 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
159f8a02 410 dev_warn(&p->pdev->dev,
8b092be9
GU
411 "Invalid number of gpio lines %u, using %u\n", *npins,
412 RCAR_MAX_GPIO_PER_BANK);
413 *npins = RCAR_MAX_GPIO_PER_BANK;
159f8a02 414 }
850dfe17
LP
415
416 return 0;
159f8a02
LP
417}
418
119f5e44
MD
419static int gpio_rcar_probe(struct platform_device *pdev)
420{
119f5e44
MD
421 struct gpio_rcar_priv *p;
422 struct resource *io, *irq;
423 struct gpio_chip *gpio_chip;
424 struct irq_chip *irq_chip;
b22978fc
GU
425 struct device *dev = &pdev->dev;
426 const char *name = dev_name(dev);
8b092be9 427 unsigned int npins;
119f5e44
MD
428 int ret;
429
b22978fc 430 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
7d82bf34
GU
431 if (!p)
432 return -ENOMEM;
119f5e44 433
119f5e44 434 p->pdev = pdev;
119f5e44
MD
435 spin_lock_init(&p->lock);
436
8b092be9
GU
437 /* Get device configuration from DT node */
438 ret = gpio_rcar_parse_dt(p, &npins);
850dfe17
LP
439 if (ret < 0)
440 return ret;
159f8a02
LP
441
442 platform_set_drvdata(pdev, p);
443
ab82fa7d
GU
444 p->clk = devm_clk_get(dev, NULL);
445 if (IS_ERR(p->clk)) {
e1fef9e2
GU
446 if (p->needs_clk) {
447 dev_err(dev, "unable to get clock\n");
448 ret = PTR_ERR(p->clk);
449 goto err0;
450 }
ab82fa7d
GU
451 p->clk = NULL;
452 }
453
df0c6c80 454 pm_runtime_enable(dev);
df0c6c80 455
119f5e44
MD
456 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
458
459 if (!io || !irq) {
b22978fc 460 dev_err(dev, "missing IRQ or IOMEM\n");
119f5e44
MD
461 ret = -EINVAL;
462 goto err0;
463 }
464
b22978fc 465 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
119f5e44 466 if (!p->base) {
b22978fc 467 dev_err(dev, "failed to remap I/O memory\n");
119f5e44
MD
468 ret = -ENXIO;
469 goto err0;
470 }
471
472 gpio_chip = &p->gpio_chip;
dc3465a9
LP
473 gpio_chip->request = gpio_rcar_request;
474 gpio_chip->free = gpio_rcar_free;
119f5e44
MD
475 gpio_chip->direction_input = gpio_rcar_direction_input;
476 gpio_chip->get = gpio_rcar_get;
477 gpio_chip->direction_output = gpio_rcar_direction_output;
478 gpio_chip->set = gpio_rcar_set;
119f5e44 479 gpio_chip->label = name;
58383c78 480 gpio_chip->parent = dev;
119f5e44 481 gpio_chip->owner = THIS_MODULE;
8b092be9
GU
482 gpio_chip->base = -1;
483 gpio_chip->ngpio = npins;
119f5e44
MD
484
485 irq_chip = &p->irq_chip;
486 irq_chip->name = name;
487 irq_chip->irq_mask = gpio_rcar_irq_disable;
488 irq_chip->irq_unmask = gpio_rcar_irq_enable;
119f5e44 489 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
ab82fa7d 490 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
b26a719b
GU
491 irq_chip->irq_bus_lock = gpio_rcar_irq_bus_lock;
492 irq_chip->irq_bus_sync_unlock = gpio_rcar_irq_bus_sync_unlock;
493 irq_chip->irq_request_resources = gpio_rcar_irq_request_resources;
494 irq_chip->irq_release_resources = gpio_rcar_irq_release_resources;
ab82fa7d 495 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
119f5e44 496
c7b6f457 497 ret = gpiochip_add_data(gpio_chip, p);
c7f3c5d3
GU
498 if (ret) {
499 dev_err(dev, "failed to add GPIO controller\n");
0c8aab8e 500 goto err0;
119f5e44
MD
501 }
502
8b092be9
GU
503 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
504 IRQ_TYPE_NONE);
c7f3c5d3
GU
505 if (ret) {
506 dev_err(dev, "cannot add irqchip\n");
507 goto err1;
508 }
509
ab82fa7d 510 p->irq_parent = irq->start;
b22978fc
GU
511 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
512 IRQF_SHARED, name, p)) {
513 dev_err(dev, "failed to request IRQ\n");
119f5e44
MD
514 ret = -ENOENT;
515 goto err1;
516 }
517
8b092be9 518 dev_info(dev, "driving %d GPIOs\n", npins);
dc3465a9 519
119f5e44
MD
520 return 0;
521
522err1:
4d84b9e4 523 gpiochip_remove(gpio_chip);
119f5e44 524err0:
df0c6c80 525 pm_runtime_disable(dev);
119f5e44
MD
526 return ret;
527}
528
529static int gpio_rcar_remove(struct platform_device *pdev)
530{
531 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
119f5e44 532
9f5132ae 533 gpiochip_remove(&p->gpio_chip);
119f5e44 534
df0c6c80 535 pm_runtime_disable(&pdev->dev);
119f5e44
MD
536 return 0;
537}
538
539static struct platform_driver gpio_rcar_device_driver = {
540 .probe = gpio_rcar_probe,
541 .remove = gpio_rcar_remove,
542 .driver = {
543 .name = "gpio_rcar",
159f8a02 544 .of_match_table = of_match_ptr(gpio_rcar_of_table),
119f5e44
MD
545 }
546};
547
548module_platform_driver(gpio_rcar_device_driver);
549
550MODULE_AUTHOR("Magnus Damm");
551MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
552MODULE_LICENSE("GPL v2");