[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-sch.c

/*
 * GPIO interface for Intel Poulsbo SCH
 *
 *  Copyright (c) 2010 CompuLab Ltd
 *  Author: Denis Turischev <denis@compulab.co.il>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License 2 as published
 *  by the Free Software Foundation.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
#include <linux/pci_ids.h>

#include <linux/gpio.h>

#define GEN	0x00
#define GIO	0x04
#define GLV	0x08

struct sch_gpio {
	struct gpio_chip chip;
	spinlock_t lock;
	unsigned short iobase;
	unsigned short core_base;
	unsigned short resume_base;
};

#define to_sch_gpio(c)	container_of(c, struct sch_gpio, chip)

static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
				unsigned reg)
{
	unsigned base = 0;

	if (gpio >= sch->resume_base) {
		gpio -= sch->resume_base;
		base += 0x20;
	}

	return base + reg + gpio / 8;
}

static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
{
	if (gpio >= sch->resume_base)
		gpio -= sch->resume_base;
	return gpio % 8;
}

static void sch_gpio_enable(struct sch_gpio *sch, unsigned gpio)
{
	unsigned short offset, bit;
	u8 enable;

	spin_lock(&sch->lock);

	offset = sch_gpio_offset(sch, gpio, GEN);
	bit = sch_gpio_bit(sch, gpio);

	enable = inb(sch->iobase + offset);
	if (!(enable & (1 << bit)))
		outb(enable | (1 << bit), sch->iobase + offset);

	spin_unlock(&sch->lock);
}

static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned  gpio_num)
{
	struct sch_gpio *sch = to_sch_gpio(gc);
	u8 curr_dirs;
	unsigned short offset, bit;

	spin_lock(&sch->lock);

	offset = sch_gpio_offset(sch, gpio_num, GIO);
	bit = sch_gpio_bit(sch, gpio_num);

	curr_dirs = inb(sch->iobase + offset);

	if (!(curr_dirs & (1 << bit)))
		outb(curr_dirs | (1 << bit), sch->iobase + offset);

	spin_unlock(&sch->lock);
	return 0;
}

static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
{
	struct sch_gpio *sch = to_sch_gpio(gc);
	int res;
	unsigned short offset, bit;

	offset = sch_gpio_offset(sch, gpio_num, GLV);
	bit = sch_gpio_bit(sch, gpio_num);

	res = !!(inb(sch->iobase + offset) & (1 << bit));

	return res;
}

static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
{
	struct sch_gpio *sch = to_sch_gpio(gc);
	u8 curr_vals;
	unsigned short offset, bit;

	spin_lock(&sch->lock);

	offset = sch_gpio_offset(sch, gpio_num, GLV);
	bit = sch_gpio_bit(sch, gpio_num);

	curr_vals = inb(sch->iobase + offset);

	if (val)
		outb(curr_vals | (1 << bit), sch->iobase + offset);
	else
		outb((curr_vals & ~(1 << bit)), sch->iobase + offset);

	spin_unlock(&sch->lock);
}

static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
				  int val)
{
	struct sch_gpio *sch = to_sch_gpio(gc);
	u8 curr_dirs;
	unsigned short offset, bit;

	spin_lock(&sch->lock);

	offset = sch_gpio_offset(sch, gpio_num, GIO);
	bit = sch_gpio_bit(sch, gpio_num);

	curr_dirs = inb(sch->iobase + offset);
	if (curr_dirs & (1 << bit))
		outb(curr_dirs & ~(1 << bit), sch->iobase + offset);

	spin_unlock(&sch->lock);

	/*
	 * according to the datasheet, writing to the level register has no
	 * effect when GPIO is programmed as input.
	 * Actually the the level register is read-only when configured as input.
	 * Thus presetting the output level before switching to output is _NOT_ possible.
	 * Hence we set the level after configuring the GPIO as output.
	 * But we cannot prevent a short low pulse if direction is set to high
	 * and an external pull-up is connected.
	 */
	sch_gpio_set(gc, gpio_num, val);
	return 0;
}

static struct gpio_chip sch_gpio_chip = {
	.label			= "sch_gpio",
	.owner			= THIS_MODULE,
	.direction_input	= sch_gpio_direction_in,
	.get			= sch_gpio_get,
	.direction_output	= sch_gpio_direction_out,
	.set			= sch_gpio_set,
};

static int sch_gpio_probe(struct platform_device *pdev)
{
	struct sch_gpio *sch;
	struct resource *res;

	sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
	if (!sch)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	if (!res)
		return -EBUSY;

	if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
				 pdev->name))
		return -EBUSY;

	spin_lock_init(&sch->lock);
	sch->iobase = res->start;
	sch->chip = sch_gpio_chip;
	sch->chip.label = dev_name(&pdev->dev);
	sch->chip.dev = &pdev->dev;

	switch (pdev->id) {
	case PCI_DEVICE_ID_INTEL_SCH_LPC:
		sch->core_base = 0;
		sch->resume_base = 10;
		sch->chip.ngpio = 14;

		/*
		 * GPIO[6:0] enabled by default
		 * GPIO7 is configured by the CMC as SLPIOVR
		 * Enable GPIO[9:8] core powered gpios explicitly
		 */
		sch_gpio_enable(sch, 8);
		sch_gpio_enable(sch, 9);
		/*
		 * SUS_GPIO[2:0] enabled by default
		 * Enable SUS_GPIO3 resume powered gpio explicitly
		 */
		sch_gpio_enable(sch, 13);
		break;

	case PCI_DEVICE_ID_INTEL_ITC_LPC:
		sch->core_base = 0;
		sch->resume_base = 5;
		sch->chip.ngpio = 14;
		break;

	case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
		sch->core_base = 0;
		sch->resume_base = 21;
		sch->chip.ngpio = 30;
		break;

	case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
		sch->core_base = 0;
		sch->resume_base = 2;
		sch->chip.ngpio = 8;
		break;

	default:
		return -ENODEV;
	}

	platform_set_drvdata(pdev, sch);

	return gpiochip_add(&sch->chip);
}

static int sch_gpio_remove(struct platform_device *pdev)
{
	struct sch_gpio *sch = platform_get_drvdata(pdev);

	gpiochip_remove(&sch->chip);
	return 0;
}

static struct platform_driver sch_gpio_driver = {
	.driver = {
		.name = "sch_gpio",
	},
	.probe		= sch_gpio_probe,
	.remove		= sch_gpio_remove,
};

module_platform_driver(sch_gpio_driver);

MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sch_gpio");
Commit	Line	Data
be9b06b2	1	/*
c103de24	2	* GPIO interface for Intel Poulsbo SCH
be9b06b2 DT	3	*
	4	* Copyright (c) 2010 CompuLab Ltd
	5	* Author: Denis Turischev <denis@compulab.co.il>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License 2 as published
	9	* by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; see the file COPYING. If not, write to
	18	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/io.h>
	25	#include <linux/errno.h>
	26	#include <linux/acpi.h>
	27	#include <linux/platform_device.h>
f04ddfcd	28	#include <linux/pci_ids.h>
be9b06b2 DT	29
	30	#include <linux/gpio.h>
	31
c479ff09 MW	32	#define GEN 0x00
	33	#define GIO 0x04
	34	#define GLV 0x08
	35
	36	struct sch_gpio {
	37	struct gpio_chip chip;
	38	spinlock_t lock;
	39	unsigned short iobase;
	40	unsigned short core_base;
	41	unsigned short resume_base;
	42	};
be9b06b2	43
c479ff09	44	#define to_sch_gpio(c) container_of(c, struct sch_gpio, chip)
be9b06b2	45
c479ff09 MW	46	static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
c479ff09 MW	47	unsigned reg)
be9b06b2	48	{
c479ff09	49	unsigned base = 0;
be9b06b2	50
c479ff09 MW	51	if (gpio >= sch->resume_base) {
	52	gpio -= sch->resume_base;
	53	base += 0x20;
	54	}
be9b06b2	55
c479ff09	56	return base + reg + gpio / 8;
be9b06b2 DT	57	}
be9b06b2 DT	58
c479ff09	59	static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
be9b06b2	60	{
c479ff09 MW	61	if (gpio >= sch->resume_base)
	62	gpio -= sch->resume_base;
	63	return gpio % 8;
be9b06b2 DT	64	}
be9b06b2 DT	65
c479ff09	66	static void sch_gpio_enable(struct sch_gpio *sch, unsigned gpio)
be9b06b2	67	{
be9b06b2	68	unsigned short offset, bit;
c479ff09	69	u8 enable;
be9b06b2	70
c479ff09	71	spin_lock(&sch->lock);
be9b06b2	72
c479ff09 MW	73	offset = sch_gpio_offset(sch, gpio, GEN);
c479ff09 MW	74	bit = sch_gpio_bit(sch, gpio);
be9b06b2	75
c479ff09 MW	76	enable = inb(sch->iobase + offset);
	77	if (!(enable & (1 << bit)))
	78	outb(enable \| (1 << bit), sch->iobase + offset);
1e0d9823	79
c479ff09	80	spin_unlock(&sch->lock);
be9b06b2 DT	81	}
be9b06b2 DT	82
c479ff09	83	static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
be9b06b2	84	{
c479ff09	85	struct sch_gpio *sch = to_sch_gpio(gc);
be9b06b2	86	u8 curr_dirs;
3cbf1822	87	unsigned short offset, bit;
be9b06b2	88
c479ff09	89	spin_lock(&sch->lock);
be9b06b2	90
c479ff09 MW	91	offset = sch_gpio_offset(sch, gpio_num, GIO);
c479ff09 MW	92	bit = sch_gpio_bit(sch, gpio_num);
3cbf1822	93
c479ff09	94	curr_dirs = inb(sch->iobase + offset);
be9b06b2	95
3cbf1822	96	if (!(curr_dirs & (1 << bit)))
c479ff09	97	outb(curr_dirs \| (1 << bit), sch->iobase + offset);
be9b06b2	98
c479ff09	99	spin_unlock(&sch->lock);
be9b06b2 DT	100	return 0;
	101	}
	102
c479ff09	103	static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
be9b06b2	104	{
c479ff09 MW	105	struct sch_gpio *sch = to_sch_gpio(gc);
c479ff09 MW	106	int res;
3cbf1822 DH	107	unsigned short offset, bit;
3cbf1822 DH	108
c479ff09 MW	109	offset = sch_gpio_offset(sch, gpio_num, GLV);
	110	bit = sch_gpio_bit(sch, gpio_num);
	111
	112	res = !!(inb(sch->iobase + offset) & (1 << bit));
3cbf1822	113
c479ff09	114	return res;
be9b06b2 DT	115	}
be9b06b2 DT	116
c479ff09	117	static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
be9b06b2	118	{
c479ff09	119	struct sch_gpio *sch = to_sch_gpio(gc);
be9b06b2	120	u8 curr_vals;
3cbf1822	121	unsigned short offset, bit;
be9b06b2	122
c479ff09	123	spin_lock(&sch->lock);
be9b06b2	124
c479ff09 MW	125	offset = sch_gpio_offset(sch, gpio_num, GLV);
c479ff09 MW	126	bit = sch_gpio_bit(sch, gpio_num);
3cbf1822	127
c479ff09	128	curr_vals = inb(sch->iobase + offset);
be9b06b2 DT	129
be9b06b2 DT	130	if (val)
c479ff09	131	outb(curr_vals \| (1 << bit), sch->iobase + offset);
be9b06b2	132	else
c479ff09	133	outb((curr_vals & ~(1 << bit)), sch->iobase + offset);
be9b06b2	134
c479ff09	135	spin_unlock(&sch->lock);
be9b06b2 DT	136	}
be9b06b2 DT	137
c479ff09 MW	138	static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
c479ff09 MW	139	int val)
be9b06b2	140	{
c479ff09	141	struct sch_gpio *sch = to_sch_gpio(gc);
be9b06b2	142	u8 curr_dirs;
3cbf1822	143	unsigned short offset, bit;
be9b06b2	144
c479ff09	145	spin_lock(&sch->lock);
3cbf1822	146
c479ff09 MW	147	offset = sch_gpio_offset(sch, gpio_num, GIO);
c479ff09 MW	148	bit = sch_gpio_bit(sch, gpio_num);
be9b06b2	149
c479ff09	150	curr_dirs = inb(sch->iobase + offset);
3cbf1822	151	if (curr_dirs & (1 << bit))
c479ff09	152	outb(curr_dirs & ~(1 << bit), sch->iobase + offset);
be9b06b2	153
c479ff09	154	spin_unlock(&sch->lock);
1e0d9823 DK	155
1e0d9823 DK	156	/*
c479ff09 MW	157	* according to the datasheet, writing to the level register has no
	158	* effect when GPIO is programmed as input.
	159	* Actually the the level register is read-only when configured as input.
	160	* Thus presetting the output level before switching to output is _NOT_ possible.
	161	* Hence we set the level after configuring the GPIO as output.
	162	* But we cannot prevent a short low pulse if direction is set to high
	163	* and an external pull-up is connected.
	164	*/
	165	sch_gpio_set(gc, gpio_num, val);
be9b06b2 DT	166	return 0;
	167	}
	168
c479ff09 MW	169	static struct gpio_chip sch_gpio_chip = {
c479ff09 MW	170	.label = "sch_gpio",
be9b06b2	171	.owner = THIS_MODULE,
c479ff09 MW	172	.direction_input = sch_gpio_direction_in,
	173	.get = sch_gpio_get,
	174	.direction_output = sch_gpio_direction_out,
	175	.set = sch_gpio_set,
be9b06b2 DT	176	};
be9b06b2 DT	177
3836309d	178	static int sch_gpio_probe(struct platform_device *pdev)
be9b06b2	179	{
c479ff09	180	struct sch_gpio *sch;
be9b06b2	181	struct resource *res;
f04ddfcd	182
c479ff09 MW	183	sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
	184	if (!sch)
	185	return -ENOMEM;
be9b06b2 DT	186
	187	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	188	if (!res)
	189	return -EBUSY;
	190
c479ff09 MW	191	if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
c479ff09 MW	192	pdev->name))
be9b06b2 DT	193	return -EBUSY;
be9b06b2 DT	194
c479ff09 MW	195	spin_lock_init(&sch->lock);
	196	sch->iobase = res->start;
	197	sch->chip = sch_gpio_chip;
	198	sch->chip.label = dev_name(&pdev->dev);
	199	sch->chip.dev = &pdev->dev;
be9b06b2	200
c479ff09	201	switch (pdev->id) {
be41cf58	202	case PCI_DEVICE_ID_INTEL_SCH_LPC:
c479ff09 MW	203	sch->core_base = 0;
	204	sch->resume_base = 10;
	205	sch->chip.ngpio = 14;
	206
be41cf58 LN	207	/*
	208	* GPIO[6:0] enabled by default
	209	* GPIO7 is configured by the CMC as SLPIOVR
	210	* Enable GPIO[9:8] core powered gpios explicitly
	211	*/
c479ff09 MW	212	sch_gpio_enable(sch, 8);
c479ff09 MW	213	sch_gpio_enable(sch, 9);
be41cf58 LN	214	/*
	215	* SUS_GPIO[2:0] enabled by default
	216	* Enable SUS_GPIO3 resume powered gpio explicitly
	217	*/
c479ff09	218	sch_gpio_enable(sch, 13);
be41cf58 LN	219	break;
	220
	221	case PCI_DEVICE_ID_INTEL_ITC_LPC:
c479ff09 MW	222	sch->core_base = 0;
	223	sch->resume_base = 5;
	224	sch->chip.ngpio = 14;
be41cf58 LN	225	break;
	226
	227	case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
c479ff09 MW	228	sch->core_base = 0;
	229	sch->resume_base = 21;
	230	sch->chip.ngpio = 30;
be41cf58 LN	231	break;
be41cf58 LN	232
92021490 CRSF	233	case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
	234	sch->core_base = 0;
	235	sch->resume_base = 2;
	236	sch->chip.ngpio = 8;
	237	break;
	238
be41cf58	239	default:
c479ff09	240	return -ENODEV;
f04ddfcd	241	}
be9b06b2	242
c479ff09	243	platform_set_drvdata(pdev, sch);
be9b06b2	244
c479ff09	245	return gpiochip_add(&sch->chip);
be9b06b2 DT	246	}
be9b06b2 DT	247
206210ce	248	static int sch_gpio_remove(struct platform_device *pdev)
be9b06b2	249	{
c479ff09	250	struct sch_gpio *sch = platform_get_drvdata(pdev);
be9b06b2	251
c479ff09	252	gpiochip_remove(&sch->chip);
be9b06b2 DT	253	return 0;
	254	}
	255
	256	static struct platform_driver sch_gpio_driver = {
	257	.driver = {
	258	.name = "sch_gpio",
be9b06b2 DT	259	},
be9b06b2 DT	260	.probe = sch_gpio_probe,
8283c4ff	261	.remove = sch_gpio_remove,
be9b06b2 DT	262	};
be9b06b2 DT	263
6f61415e	264	module_platform_driver(sch_gpio_driver);
be9b06b2 DT	265
	266	MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
	267	MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
	268	MODULE_LICENSE("GPL");
	269	MODULE_ALIAS("platform:sch_gpio");