[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-sodaville.c

/*
 *  GPIO interface for Intel Sodaville SoCs.
 *
 *  Copyright (c) 2010, 2011 Intel Corporation
 *
 *  Author: Hans J. Koch <hjk@linutronix.de>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License 2 as published
 *  by the Free Software Foundation.
 *
 */

#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/of_irq.h>
#include <linux/gpio/driver.h>

#define DRV_NAME		"sdv_gpio"
#define SDV_NUM_PUB_GPIOS	12
#define PCI_DEVICE_ID_SDV_GPIO	0x2e67
#define GPIO_BAR		0

#define GPOUTR		0x00
#define GPOER		0x04
#define GPINR		0x08

#define GPSTR		0x0c
#define GPIT1R0		0x10
#define GPIO_INT	0x14
#define GPIT1R1		0x18

#define GPMUXCTL	0x1c

struct sdv_gpio_chip_data {
	int irq_base;
	void __iomem *gpio_pub_base;
	struct irq_domain *id;
	struct irq_chip_generic *gc;
	struct gpio_chip chip;
};

static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct sdv_gpio_chip_data *sd = gc->private;
	void __iomem *type_reg;
	u32 reg;

	if (d->hwirq < 8)
		type_reg = sd->gpio_pub_base + GPIT1R0;
	else
		type_reg = sd->gpio_pub_base + GPIT1R1;

	reg = readl(type_reg);

	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		reg &= ~BIT(4 * (d->hwirq % 8));
		break;

	case IRQ_TYPE_LEVEL_LOW:
		reg |= BIT(4 * (d->hwirq % 8));
		break;

	default:
		return -EINVAL;
	}

	writel(reg, type_reg);
	return 0;
}

static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
{
	struct sdv_gpio_chip_data *sd = data;
	u32 irq_stat = readl(sd->gpio_pub_base + GPSTR);

	irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
	if (!irq_stat)
		return IRQ_NONE;

	while (irq_stat) {
		u32 irq_bit = __fls(irq_stat);

		irq_stat &= ~BIT(irq_bit);
		generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
	}

	return IRQ_HANDLED;
}

static int sdv_xlate(struct irq_domain *h, struct device_node *node,
		const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
		u32 *out_type)
{
	u32 line, type;

	if (node != irq_domain_get_of_node(h))
		return -EINVAL;

	if (intsize < 2)
		return -EINVAL;

	line = *intspec;
	*out_hwirq = line;

	intspec++;
	type = *intspec;

	switch (type) {
	case IRQ_TYPE_LEVEL_LOW:
	case IRQ_TYPE_LEVEL_HIGH:
		*out_type = type;
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static const struct irq_domain_ops irq_domain_sdv_ops = {
	.xlate = sdv_xlate,
};

static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
		struct pci_dev *pdev)
{
	struct irq_chip_type *ct;
	int ret;

	sd->irq_base = irq_alloc_descs(-1, 0, SDV_NUM_PUB_GPIOS, -1);
	if (sd->irq_base < 0)
		return sd->irq_base;

	/* mask + ACK all interrupt sources */
	writel(0, sd->gpio_pub_base + GPIO_INT);
	writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);

	ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
			"sdv_gpio", sd);
	if (ret)
		goto out_free_desc;

	/*
	 * This gpio irq controller latches level irqs. Testing shows that if
	 * we unmask & ACK the IRQ before the source of the interrupt is gone
	 * then the interrupt is active again.
	 */
	sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
			sd->gpio_pub_base, handle_fasteoi_irq);
	if (!sd->gc) {
		ret = -ENOMEM;
		goto out_free_irq;
	}

	sd->gc->private = sd;
	ct = sd->gc->chip_types;
	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
	ct->regs.eoi = GPSTR;
	ct->regs.mask = GPIO_INT;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_eoi = irq_gc_eoi;
	ct->chip.irq_set_type = sdv_gpio_pub_set_type;

	irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
			IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
			IRQ_LEVEL | IRQ_NOPROBE);

	sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
				sd->irq_base, 0, &irq_domain_sdv_ops, sd);
	if (!sd->id) {
		ret = -ENODEV;
		goto out_free_irq;
	}
	return 0;
out_free_irq:
	free_irq(pdev->irq, sd);
out_free_desc:
	irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
	return ret;
}

static int sdv_gpio_probe(struct pci_dev *pdev,
					const struct pci_device_id *pci_id)
{
	struct sdv_gpio_chip_data *sd;
	unsigned long addr;
	const void *prop;
	int len;
	int ret;
	u32 mux_val;

	sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL);
	if (!sd)
		return -ENOMEM;
	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "can't enable device.\n");
		goto done;
	}

	ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
	if (ret) {
		dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
		goto disable_pci;
	}

	addr = pci_resource_start(pdev, GPIO_BAR);
	if (!addr) {
		ret = -ENODEV;
		goto release_reg;
	}
	sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR));

	prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len);
	if (prop && len == 4) {
		mux_val = of_read_number(prop, 1);
		writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
	}

	ret = bgpio_init(&sd->chip, &pdev->dev, 4,
			sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
			NULL, sd->gpio_pub_base + GPOER, NULL, 0);
	if (ret)
		goto unmap;
	sd->chip.ngpio = SDV_NUM_PUB_GPIOS;

	ret = gpiochip_add_data(&sd->chip, sd);
	if (ret < 0) {
		dev_err(&pdev->dev, "gpiochip_add() failed.\n");
		goto unmap;
	}

	ret = sdv_register_irqsupport(sd, pdev);
	if (ret)
		goto unmap;

	pci_set_drvdata(pdev, sd);
	dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
	return 0;

unmap:
	iounmap(sd->gpio_pub_base);
release_reg:
	pci_release_region(pdev, GPIO_BAR);
disable_pci:
	pci_disable_device(pdev);
done:
	kfree(sd);
	return ret;
}

static const struct pci_device_id sdv_gpio_pci_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
	{ 0, },
};

static struct pci_driver sdv_gpio_driver = {
	.driver = {
		.suppress_bind_attrs = true,
	},
	.name = DRV_NAME,
	.id_table = sdv_gpio_pci_ids,
	.probe = sdv_gpio_probe,
};
builtin_pci_driver(sdv_gpio_driver);
Commit	Line	Data
b43ab901 SAS	1	/*
	2	* GPIO interface for Intel Sodaville SoCs.
	3	*
	4	* Copyright (c) 2010, 2011 Intel Corporation
	5	*
6a5ead91 PG	6	* Author: Hans J. Koch <hjk@linutronix.de>
6a5ead91 PG	7	*
b43ab901 SAS	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License 2 as published
	10	* by the Free Software Foundation.
	11	*
	12	*/
	13
	14	#include <linux/errno.h>
b43ab901 SAS	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/irq.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/kernel.h>
b43ab901 SAS	20	#include <linux/pci.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/of_irq.h>
0f4630f3	23	#include <linux/gpio/driver.h>
b43ab901 SAS	24
	25	#define DRV_NAME "sdv_gpio"
	26	#define SDV_NUM_PUB_GPIOS 12
	27	#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
	28	#define GPIO_BAR 0
	29
	30	#define GPOUTR 0x00
	31	#define GPOER 0x04
	32	#define GPINR 0x08
	33
	34	#define GPSTR 0x0c
	35	#define GPIT1R0 0x10
	36	#define GPIO_INT 0x14
	37	#define GPIT1R1 0x18
	38
	39	#define GPMUXCTL 0x1c
	40
	41	struct sdv_gpio_chip_data {
	42	int irq_base;
	43	void __iomem *gpio_pub_base;
3ffc9ceb	44	struct irq_domain *id;
b43ab901	45	struct irq_chip_generic *gc;
0f4630f3	46	struct gpio_chip chip;
b43ab901 SAS	47	};
	48
	49	static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
	50	{
	51	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	52	struct sdv_gpio_chip_data *sd = gc->private;
	53	void __iomem *type_reg;
b43ab901 SAS	54	u32 reg;
b43ab901 SAS	55
3ffc9ceb	56	if (d->hwirq < 8)
b43ab901 SAS	57	type_reg = sd->gpio_pub_base + GPIT1R0;
	58	else
	59	type_reg = sd->gpio_pub_base + GPIT1R1;
	60
	61	reg = readl(type_reg);
	62
	63	switch (type) {
	64	case IRQ_TYPE_LEVEL_HIGH:
3ffc9ceb	65	reg &= ~BIT(4 * (d->hwirq % 8));
b43ab901 SAS	66	break;
	67
	68	case IRQ_TYPE_LEVEL_LOW:
3ffc9ceb	69	reg \|= BIT(4 * (d->hwirq % 8));
b43ab901 SAS	70	break;
	71
	72	default:
	73	return -EINVAL;
	74	}
	75
	76	writel(reg, type_reg);
	77	return 0;
	78	}
	79
	80	static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
	81	{
	82	struct sdv_gpio_chip_data *sd = data;
	83	u32 irq_stat = readl(sd->gpio_pub_base + GPSTR);
	84
	85	irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
	86	if (!irq_stat)
	87	return IRQ_NONE;
	88
	89	while (irq_stat) {
	90	u32 irq_bit = __fls(irq_stat);
	91
	92	irq_stat &= ~BIT(irq_bit);
3ffc9ceb	93	generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
b43ab901 SAS	94	}
	95
	96	return IRQ_HANDLED;
	97	}
	98
	99	static int sdv_xlate(struct irq_domain h, struct device_node node,
	100	const u32 intspec, u32 intsize, irq_hw_number_t out_hwirq,
	101	u32 *out_type)
	102	{
	103	u32 line, type;
	104
5d4c9bc7	105	if (node != irq_domain_get_of_node(h))
b43ab901 SAS	106	return -EINVAL;
	107
	108	if (intsize < 2)
	109	return -EINVAL;
	110
	111	line = *intspec;
	112	*out_hwirq = line;
	113
	114	intspec++;
	115	type = *intspec;
	116
	117	switch (type) {
	118	case IRQ_TYPE_LEVEL_LOW:
	119	case IRQ_TYPE_LEVEL_HIGH:
	120	*out_type = type;
	121	break;
	122	default:
	123	return -EINVAL;
	124	}
	125	return 0;
	126	}
	127
0b354dc4	128	static const struct irq_domain_ops irq_domain_sdv_ops = {
3ffc9ceb	129	.xlate = sdv_xlate,
b43ab901 SAS	130	};
b43ab901 SAS	131
3836309d	132	static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
b43ab901 SAS	133	struct pci_dev *pdev)
	134	{
	135	struct irq_chip_type *ct;
	136	int ret;
	137
	138	sd->irq_base = irq_alloc_descs(-1, 0, SDV_NUM_PUB_GPIOS, -1);
	139	if (sd->irq_base < 0)
	140	return sd->irq_base;
	141
	142	/* mask + ACK all interrupt sources */
	143	writel(0, sd->gpio_pub_base + GPIO_INT);
	144	writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
	145
	146	ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
	147	"sdv_gpio", sd);
	148	if (ret)
	149	goto out_free_desc;
	150
b43ab901 SAS	151	/*
	152	* This gpio irq controller latches level irqs. Testing shows that if
	153	* we unmask & ACK the IRQ before the source of the interrupt is gone
	154	* then the interrupt is active again.
	155	*/
	156	sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
	157	sd->gpio_pub_base, handle_fasteoi_irq);
	158	if (!sd->gc) {
	159	ret = -ENOMEM;
	160	goto out_free_irq;
	161	}
	162
	163	sd->gc->private = sd;
	164	ct = sd->gc->chip_types;
	165	ct->type = IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW;
	166	ct->regs.eoi = GPSTR;
	167	ct->regs.mask = GPIO_INT;
	168	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	169	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	170	ct->chip.irq_eoi = irq_gc_eoi;
	171	ct->chip.irq_set_type = sdv_gpio_pub_set_type;
	172
	173	irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
	174	IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
	175	IRQ_LEVEL \| IRQ_NOPROBE);
	176
3ffc9ceb GL	177	sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
3ffc9ceb GL	178	sd->irq_base, 0, &irq_domain_sdv_ops, sd);
e6ae9195 WY	179	if (!sd->id) {
e6ae9195 WY	180	ret = -ENODEV;
3ffc9ceb	181	goto out_free_irq;
e6ae9195	182	}
b43ab901 SAS	183	return 0;
	184	out_free_irq:
	185	free_irq(pdev->irq, sd);
	186	out_free_desc:
	187	irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
	188	return ret;
	189	}
	190
3836309d	191	static int sdv_gpio_probe(struct pci_dev *pdev,
b43ab901 SAS	192	const struct pci_device_id *pci_id)
	193	{
	194	struct sdv_gpio_chip_data *sd;
	195	unsigned long addr;
	196	const void *prop;
	197	int len;
	198	int ret;
	199	u32 mux_val;
	200
	201	sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL);
	202	if (!sd)
	203	return -ENOMEM;
	204	ret = pci_enable_device(pdev);
	205	if (ret) {
	206	dev_err(&pdev->dev, "can't enable device.\n");
	207	goto done;
	208	}
	209
	210	ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
	211	if (ret) {
	212	dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
	213	goto disable_pci;
	214	}
	215
	216	addr = pci_resource_start(pdev, GPIO_BAR);
e6ae9195 WY	217	if (!addr) {
e6ae9195 WY	218	ret = -ENODEV;
b43ab901	219	goto release_reg;
e6ae9195	220	}
b43ab901 SAS	221	sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR));
	222
	223	prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len);
	224	if (prop && len == 4) {
	225	mux_val = of_read_number(prop, 1);
	226	writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
	227	}
	228
0f4630f3	229	ret = bgpio_init(&sd->chip, &pdev->dev, 4,
b43ab901	230	sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
3e11f7b8	231	NULL, sd->gpio_pub_base + GPOER, NULL, 0);
b43ab901 SAS	232	if (ret)
b43ab901 SAS	233	goto unmap;
0f4630f3	234	sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
b43ab901	235
0f4630f3	236	ret = gpiochip_add_data(&sd->chip, sd);
b43ab901 SAS	237	if (ret < 0) {
	238	dev_err(&pdev->dev, "gpiochip_add() failed.\n");
	239	goto unmap;
	240	}
	241
	242	ret = sdv_register_irqsupport(sd, pdev);
	243	if (ret)
	244	goto unmap;
	245
	246	pci_set_drvdata(pdev, sd);
	247	dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
	248	return 0;
	249
	250	unmap:
	251	iounmap(sd->gpio_pub_base);
	252	release_reg:
	253	pci_release_region(pdev, GPIO_BAR);
	254	disable_pci:
	255	pci_disable_device(pdev);
	256	done:
	257	kfree(sd);
	258	return ret;
	259	}
	260
14f4a883	261	static const struct pci_device_id sdv_gpio_pci_ids[] = {
b43ab901 SAS	262	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
	263	{ 0, },
	264	};
	265
	266	static struct pci_driver sdv_gpio_driver = {
6a5ead91 PG	267	.driver = {
	268	.suppress_bind_attrs = true,
	269	},
b43ab901 SAS	270	.name = DRV_NAME,
	271	.id_table = sdv_gpio_pci_ids,
	272	.probe = sdv_gpio_probe,
b43ab901	273	};
6a5ead91	274	builtin_pci_driver(sdv_gpio_driver);