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Commit | Line | Data |
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03f822f5 RV |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License, version 2 | |
5 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
6 | */ | |
7 | ||
03f822f5 RV |
8 | #include <linux/init.h> |
9 | #include <linux/platform_device.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/gpio.h> | |
03f822f5 | 12 | #include <linux/interrupt.h> |
86605cfe | 13 | #include <linux/of.h> |
03f822f5 | 14 | #include <linux/mfd/stmpe.h> |
27ec8a9c | 15 | #include <linux/seq_file.h> |
03f822f5 RV |
16 | |
17 | /* | |
18 | * These registers are modified under the irq bus lock and cached to avoid | |
19 | * unnecessary writes in bus_sync_unlock. | |
20 | */ | |
21 | enum { REG_RE, REG_FE, REG_IE }; | |
22 | ||
43db289d PC |
23 | enum { LSB, CSB, MSB }; |
24 | ||
03f822f5 | 25 | #define CACHE_NR_REGS 3 |
9e9dc7d9 LW |
26 | /* No variant has more than 24 GPIOs */ |
27 | #define CACHE_NR_BANKS (24 / 8) | |
03f822f5 RV |
28 | |
29 | struct stmpe_gpio { | |
30 | struct gpio_chip chip; | |
31 | struct stmpe *stmpe; | |
32 | struct device *dev; | |
33 | struct mutex irq_lock; | |
1dfb4a0d | 34 | u32 norequest_mask; |
03f822f5 RV |
35 | /* Caches of interrupt control registers for bus_lock */ |
36 | u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
37 | u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
38 | }; | |
39 | ||
03f822f5 RV |
40 | static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) |
41 | { | |
b03c04a0 | 42 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 | 43 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
43db289d | 44 | u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; |
03f822f5 RV |
45 | u8 mask = 1 << (offset % 8); |
46 | int ret; | |
47 | ||
48 | ret = stmpe_reg_read(stmpe, reg); | |
49 | if (ret < 0) | |
50 | return ret; | |
51 | ||
7535b8be | 52 | return !!(ret & mask); |
03f822f5 RV |
53 | } |
54 | ||
55 | static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
56 | { | |
b03c04a0 | 57 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
58 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
59 | int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; | |
43db289d | 60 | u8 reg = stmpe->regs[which + (offset / 8)]; |
03f822f5 RV |
61 | u8 mask = 1 << (offset % 8); |
62 | ||
cccdceb9 VK |
63 | /* |
64 | * Some variants have single register for gpio set/clear functionality. | |
65 | * For them we need to write 0 to clear and 1 to set. | |
66 | */ | |
67 | if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) | |
68 | stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); | |
69 | else | |
70 | stmpe_reg_write(stmpe, reg, mask); | |
03f822f5 RV |
71 | } |
72 | ||
8e293fb0 LW |
73 | static int stmpe_gpio_get_direction(struct gpio_chip *chip, |
74 | unsigned offset) | |
75 | { | |
76 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); | |
77 | struct stmpe *stmpe = stmpe_gpio->stmpe; | |
78 | u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); | |
79 | u8 mask = 1 << (offset % 8); | |
80 | int ret; | |
81 | ||
82 | ret = stmpe_reg_read(stmpe, reg); | |
83 | if (ret < 0) | |
84 | return ret; | |
85 | ||
86 | return !(ret & mask); | |
87 | } | |
88 | ||
03f822f5 RV |
89 | static int stmpe_gpio_direction_output(struct gpio_chip *chip, |
90 | unsigned offset, int val) | |
91 | { | |
b03c04a0 | 92 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 | 93 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
43db289d | 94 | u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; |
03f822f5 RV |
95 | u8 mask = 1 << (offset % 8); |
96 | ||
97 | stmpe_gpio_set(chip, offset, val); | |
98 | ||
99 | return stmpe_set_bits(stmpe, reg, mask, mask); | |
100 | } | |
101 | ||
102 | static int stmpe_gpio_direction_input(struct gpio_chip *chip, | |
103 | unsigned offset) | |
104 | { | |
b03c04a0 | 105 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 | 106 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
43db289d | 107 | u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; |
03f822f5 RV |
108 | u8 mask = 1 << (offset % 8); |
109 | ||
110 | return stmpe_set_bits(stmpe, reg, mask, 0); | |
111 | } | |
112 | ||
03f822f5 RV |
113 | static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) |
114 | { | |
b03c04a0 | 115 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
03f822f5 RV |
116 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
117 | ||
b8e9cf0b WS |
118 | if (stmpe_gpio->norequest_mask & (1 << offset)) |
119 | return -EINVAL; | |
120 | ||
03f822f5 RV |
121 | return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); |
122 | } | |
123 | ||
124 | static struct gpio_chip template_chip = { | |
125 | .label = "stmpe", | |
126 | .owner = THIS_MODULE, | |
8e293fb0 | 127 | .get_direction = stmpe_gpio_get_direction, |
03f822f5 RV |
128 | .direction_input = stmpe_gpio_direction_input, |
129 | .get = stmpe_gpio_get, | |
130 | .direction_output = stmpe_gpio_direction_output, | |
131 | .set = stmpe_gpio_set, | |
03f822f5 | 132 | .request = stmpe_gpio_request, |
9fb1f39e | 133 | .can_sleep = true, |
03f822f5 RV |
134 | }; |
135 | ||
2a866f39 | 136 | static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
03f822f5 | 137 | { |
fe44e70d | 138 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 139 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
fc13d5a5 | 140 | int offset = d->hwirq; |
03f822f5 RV |
141 | int regoffset = offset / 8; |
142 | int mask = 1 << (offset % 8); | |
143 | ||
1fe3bd9e | 144 | if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) |
03f822f5 RV |
145 | return -EINVAL; |
146 | ||
cccdceb9 VK |
147 | /* STMPE801 doesn't have RE and FE registers */ |
148 | if (stmpe_gpio->stmpe->partnum == STMPE801) | |
149 | return 0; | |
150 | ||
1fe3bd9e | 151 | if (type & IRQ_TYPE_EDGE_RISING) |
03f822f5 RV |
152 | stmpe_gpio->regs[REG_RE][regoffset] |= mask; |
153 | else | |
154 | stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; | |
155 | ||
1fe3bd9e | 156 | if (type & IRQ_TYPE_EDGE_FALLING) |
03f822f5 RV |
157 | stmpe_gpio->regs[REG_FE][regoffset] |= mask; |
158 | else | |
159 | stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
2a866f39 | 164 | static void stmpe_gpio_irq_lock(struct irq_data *d) |
03f822f5 | 165 | { |
fe44e70d | 166 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 167 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
03f822f5 RV |
168 | |
169 | mutex_lock(&stmpe_gpio->irq_lock); | |
170 | } | |
171 | ||
2a866f39 | 172 | static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) |
03f822f5 | 173 | { |
fe44e70d | 174 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 175 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
03f822f5 RV |
176 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
177 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); | |
43db289d PC |
178 | static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = { |
179 | [REG_RE][LSB] = STMPE_IDX_GPRER_LSB, | |
180 | [REG_RE][CSB] = STMPE_IDX_GPRER_CSB, | |
181 | [REG_RE][MSB] = STMPE_IDX_GPRER_MSB, | |
182 | [REG_FE][LSB] = STMPE_IDX_GPFER_LSB, | |
183 | [REG_FE][CSB] = STMPE_IDX_GPFER_CSB, | |
184 | [REG_FE][MSB] = STMPE_IDX_GPFER_MSB, | |
185 | [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB, | |
186 | [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB, | |
187 | [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB, | |
03f822f5 RV |
188 | }; |
189 | int i, j; | |
190 | ||
191 | for (i = 0; i < CACHE_NR_REGS; i++) { | |
cccdceb9 VK |
192 | /* STMPE801 doesn't have RE and FE registers */ |
193 | if ((stmpe->partnum == STMPE801) && | |
194 | (i != REG_IE)) | |
195 | continue; | |
196 | ||
03f822f5 RV |
197 | for (j = 0; j < num_banks; j++) { |
198 | u8 old = stmpe_gpio->oldregs[i][j]; | |
199 | u8 new = stmpe_gpio->regs[i][j]; | |
200 | ||
201 | if (new == old) | |
202 | continue; | |
203 | ||
204 | stmpe_gpio->oldregs[i][j] = new; | |
43db289d | 205 | stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new); |
03f822f5 RV |
206 | } |
207 | } | |
208 | ||
209 | mutex_unlock(&stmpe_gpio->irq_lock); | |
210 | } | |
211 | ||
2a866f39 | 212 | static void stmpe_gpio_irq_mask(struct irq_data *d) |
03f822f5 | 213 | { |
fe44e70d | 214 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 215 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
fc13d5a5 | 216 | int offset = d->hwirq; |
03f822f5 RV |
217 | int regoffset = offset / 8; |
218 | int mask = 1 << (offset % 8); | |
219 | ||
220 | stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; | |
221 | } | |
222 | ||
2a866f39 | 223 | static void stmpe_gpio_irq_unmask(struct irq_data *d) |
03f822f5 | 224 | { |
fe44e70d | 225 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b03c04a0 | 226 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
fc13d5a5 | 227 | int offset = d->hwirq; |
03f822f5 RV |
228 | int regoffset = offset / 8; |
229 | int mask = 1 << (offset % 8); | |
230 | ||
231 | stmpe_gpio->regs[REG_IE][regoffset] |= mask; | |
232 | } | |
233 | ||
27ec8a9c LW |
234 | static void stmpe_dbg_show_one(struct seq_file *s, |
235 | struct gpio_chip *gc, | |
236 | unsigned offset, unsigned gpio) | |
237 | { | |
b03c04a0 | 238 | struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
27ec8a9c LW |
239 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
240 | const char *label = gpiochip_is_requested(gc, offset); | |
27ec8a9c | 241 | bool val = !!stmpe_gpio_get(gc, offset); |
43db289d PC |
242 | u8 bank = offset / 8; |
243 | u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank]; | |
27ec8a9c LW |
244 | u8 mask = 1 << (offset % 8); |
245 | int ret; | |
246 | u8 dir; | |
247 | ||
248 | ret = stmpe_reg_read(stmpe, dir_reg); | |
249 | if (ret < 0) | |
250 | return; | |
251 | dir = !!(ret & mask); | |
252 | ||
253 | if (dir) { | |
254 | seq_printf(s, " gpio-%-3d (%-20.20s) out %s", | |
255 | gpio, label ?: "(none)", | |
256 | val ? "hi" : "lo"); | |
257 | } else { | |
287849cb PC |
258 | u8 edge_det_reg; |
259 | u8 rise_reg; | |
260 | u8 fall_reg; | |
261 | u8 irqen_reg; | |
262 | ||
263 | char *edge_det_values[] = {"edge-inactive", | |
264 | "edge-asserted", | |
265 | "not-supported"}; | |
266 | char *rise_values[] = {"no-rising-edge-detection", | |
267 | "rising-edge-detection", | |
268 | "not-supported"}; | |
269 | char *fall_values[] = {"no-falling-edge-detection", | |
270 | "falling-edge-detection", | |
271 | "not-supported"}; | |
272 | #define NOT_SUPPORTED_IDX 2 | |
273 | u8 edge_det = NOT_SUPPORTED_IDX; | |
274 | u8 rise = NOT_SUPPORTED_IDX; | |
275 | u8 fall = NOT_SUPPORTED_IDX; | |
27ec8a9c LW |
276 | bool irqen; |
277 | ||
287849cb PC |
278 | switch (stmpe->partnum) { |
279 | case STMPE610: | |
280 | case STMPE811: | |
281 | case STMPE1601: | |
282 | case STMPE2401: | |
283 | case STMPE2403: | |
43db289d | 284 | edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank]; |
287849cb PC |
285 | ret = stmpe_reg_read(stmpe, edge_det_reg); |
286 | if (ret < 0) | |
287 | return; | |
288 | edge_det = !!(ret & mask); | |
289 | ||
290 | case STMPE1801: | |
43db289d PC |
291 | rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank]; |
292 | fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank]; | |
293 | ||
287849cb PC |
294 | ret = stmpe_reg_read(stmpe, rise_reg); |
295 | if (ret < 0) | |
296 | return; | |
297 | rise = !!(ret & mask); | |
298 | ret = stmpe_reg_read(stmpe, fall_reg); | |
299 | if (ret < 0) | |
300 | return; | |
301 | fall = !!(ret & mask); | |
302 | ||
303 | case STMPE801: | |
43db289d | 304 | irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank]; |
287849cb PC |
305 | break; |
306 | ||
307 | default: | |
27ec8a9c | 308 | return; |
287849cb PC |
309 | } |
310 | ||
27ec8a9c LW |
311 | ret = stmpe_reg_read(stmpe, irqen_reg); |
312 | if (ret < 0) | |
313 | return; | |
314 | irqen = !!(ret & mask); | |
315 | ||
287849cb | 316 | seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", |
27ec8a9c LW |
317 | gpio, label ?: "(none)", |
318 | val ? "hi" : "lo", | |
287849cb PC |
319 | edge_det_values[edge_det], |
320 | irqen ? "IRQ-enabled" : "IRQ-disabled", | |
321 | rise_values[rise], | |
322 | fall_values[fall]); | |
27ec8a9c LW |
323 | } |
324 | } | |
325 | ||
326 | static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) | |
327 | { | |
328 | unsigned i; | |
329 | unsigned gpio = gc->base; | |
330 | ||
331 | for (i = 0; i < gc->ngpio; i++, gpio++) { | |
332 | stmpe_dbg_show_one(s, gc, i, gpio); | |
333 | seq_printf(s, "\n"); | |
334 | } | |
335 | } | |
336 | ||
03f822f5 RV |
337 | static struct irq_chip stmpe_gpio_irq_chip = { |
338 | .name = "stmpe-gpio", | |
2a866f39 LB |
339 | .irq_bus_lock = stmpe_gpio_irq_lock, |
340 | .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, | |
341 | .irq_mask = stmpe_gpio_irq_mask, | |
342 | .irq_unmask = stmpe_gpio_irq_unmask, | |
343 | .irq_set_type = stmpe_gpio_irq_set_type, | |
03f822f5 RV |
344 | }; |
345 | ||
346 | static irqreturn_t stmpe_gpio_irq(int irq, void *dev) | |
347 | { | |
348 | struct stmpe_gpio *stmpe_gpio = dev; | |
349 | struct stmpe *stmpe = stmpe_gpio->stmpe; | |
350 | u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; | |
351 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); | |
352 | u8 status[num_banks]; | |
353 | int ret; | |
354 | int i; | |
355 | ||
356 | ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); | |
357 | if (ret < 0) | |
358 | return IRQ_NONE; | |
359 | ||
360 | for (i = 0; i < num_banks; i++) { | |
361 | int bank = num_banks - i - 1; | |
362 | unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; | |
363 | unsigned int stat = status[i]; | |
364 | ||
365 | stat &= enabled; | |
366 | if (!stat) | |
367 | continue; | |
368 | ||
369 | while (stat) { | |
370 | int bit = __ffs(stat); | |
371 | int line = bank * 8 + bit; | |
fe44e70d | 372 | int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain, |
ed05e204 | 373 | line); |
03f822f5 | 374 | |
ed05e204 | 375 | handle_nested_irq(child_irq); |
03f822f5 RV |
376 | stat &= ~(1 << bit); |
377 | } | |
378 | ||
6936e1f8 PC |
379 | /* |
380 | * interrupt status register write has no effect on | |
381 | * 801 and 1801, bits are cleared when read. | |
382 | * Edge detect register is not present on 801 and 1801 | |
383 | */ | |
384 | if (stmpe->partnum != STMPE801 || stmpe->partnum != STMPE1801) { | |
385 | stmpe_reg_write(stmpe, statmsbreg + i, status[i]); | |
43db289d PC |
386 | stmpe_reg_write(stmpe, |
387 | stmpe->regs[STMPE_IDX_GPEDR_LSB + i], | |
388 | status[i]); | |
6936e1f8 | 389 | } |
03f822f5 RV |
390 | } |
391 | ||
392 | return IRQ_HANDLED; | |
393 | } | |
394 | ||
3836309d | 395 | static int stmpe_gpio_probe(struct platform_device *pdev) |
03f822f5 RV |
396 | { |
397 | struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); | |
86605cfe | 398 | struct device_node *np = pdev->dev.of_node; |
03f822f5 RV |
399 | struct stmpe_gpio *stmpe_gpio; |
400 | int ret; | |
38040c85 | 401 | int irq = 0; |
03f822f5 | 402 | |
03f822f5 | 403 | irq = platform_get_irq(pdev, 0); |
03f822f5 RV |
404 | |
405 | stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL); | |
406 | if (!stmpe_gpio) | |
407 | return -ENOMEM; | |
408 | ||
409 | mutex_init(&stmpe_gpio->irq_lock); | |
410 | ||
411 | stmpe_gpio->dev = &pdev->dev; | |
412 | stmpe_gpio->stmpe = stmpe; | |
03f822f5 RV |
413 | stmpe_gpio->chip = template_chip; |
414 | stmpe_gpio->chip.ngpio = stmpe->num_gpios; | |
58383c78 | 415 | stmpe_gpio->chip.parent = &pdev->dev; |
9afd9b70 | 416 | stmpe_gpio->chip.of_node = np; |
9e9dc7d9 | 417 | stmpe_gpio->chip.base = -1; |
03f822f5 | 418 | |
27ec8a9c LW |
419 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
420 | stmpe_gpio->chip.dbg_show = stmpe_dbg_show; | |
421 | ||
1dfb4a0d LW |
422 | of_property_read_u32(np, "st,norequest-mask", |
423 | &stmpe_gpio->norequest_mask); | |
86605cfe | 424 | |
9e9dc7d9 | 425 | if (irq < 0) |
38040c85 | 426 | dev_info(&pdev->dev, |
fe44e70d | 427 | "device configured in no-irq mode: " |
38040c85 | 428 | "irqs are not available\n"); |
03f822f5 RV |
429 | |
430 | ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); | |
431 | if (ret) | |
02bf0749 | 432 | goto out_free; |
03f822f5 | 433 | |
b03c04a0 | 434 | ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio); |
3f97d5fc LW |
435 | if (ret) { |
436 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); | |
437 | goto out_disable; | |
438 | } | |
439 | ||
fe44e70d LW |
440 | if (irq > 0) { |
441 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
442 | stmpe_gpio_irq, IRQF_ONESHOT, | |
443 | "stmpe-gpio", stmpe_gpio); | |
38040c85 CB |
444 | if (ret) { |
445 | dev_err(&pdev->dev, "unable to get irq: %d\n", ret); | |
fc13d5a5 | 446 | goto out_disable; |
38040c85 | 447 | } |
fe44e70d LW |
448 | ret = gpiochip_irqchip_add(&stmpe_gpio->chip, |
449 | &stmpe_gpio_irq_chip, | |
450 | 0, | |
451 | handle_simple_irq, | |
452 | IRQ_TYPE_NONE); | |
453 | if (ret) { | |
454 | dev_err(&pdev->dev, | |
455 | "could not connect irqchip to gpiochip\n"); | |
3f97d5fc | 456 | goto out_disable; |
fe44e70d | 457 | } |
03f822f5 | 458 | |
3f97d5fc LW |
459 | gpiochip_set_chained_irqchip(&stmpe_gpio->chip, |
460 | &stmpe_gpio_irq_chip, | |
461 | irq, | |
462 | NULL); | |
03f822f5 RV |
463 | } |
464 | ||
03f822f5 RV |
465 | platform_set_drvdata(pdev, stmpe_gpio); |
466 | ||
467 | return 0; | |
468 | ||
02bf0749 VK |
469 | out_disable: |
470 | stmpe_disable(stmpe, STMPE_BLOCK_GPIO); | |
3f97d5fc | 471 | gpiochip_remove(&stmpe_gpio->chip); |
03f822f5 RV |
472 | out_free: |
473 | kfree(stmpe_gpio); | |
474 | return ret; | |
475 | } | |
476 | ||
03f822f5 | 477 | static struct platform_driver stmpe_gpio_driver = { |
3b52bb96 PG |
478 | .driver = { |
479 | .suppress_bind_attrs = true, | |
480 | .name = "stmpe-gpio", | |
3b52bb96 | 481 | }, |
03f822f5 | 482 | .probe = stmpe_gpio_probe, |
03f822f5 RV |
483 | }; |
484 | ||
485 | static int __init stmpe_gpio_init(void) | |
486 | { | |
487 | return platform_driver_register(&stmpe_gpio_driver); | |
488 | } | |
489 | subsys_initcall(stmpe_gpio_init); |