[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-stp-xway.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 *  Copyright (C) 2012 John Crispin <john@phrozen.org>
 *
 */

#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/of_platform.h>
#include <linux/mutex.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/of_gpio.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <lantiq_soc.h>

/*
 * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
 * peripheral controller used to drive external shift register cascades. At most
 * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
 * to drive the 2 LSBs of the cascade automatically.
 */

/* control register 0 */
#define XWAY_STP_CON0		0x00
/* control register 1 */
#define XWAY_STP_CON1		0x04
/* data register 0 */
#define XWAY_STP_CPU0		0x08
/* data register 1 */
#define XWAY_STP_CPU1		0x0C
/* access register */
#define XWAY_STP_AR		0x10

/* software or hardware update select bit */
#define XWAY_STP_CON_SWU	BIT(31)

/* automatic update rates */
#define XWAY_STP_2HZ		0
#define XWAY_STP_4HZ		BIT(23)
#define XWAY_STP_8HZ		BIT(24)
#define XWAY_STP_10HZ		(BIT(24) | BIT(23))
#define XWAY_STP_SPEED_MASK	(0xf << 23)

/* clock source for automatic update */
#define XWAY_STP_UPD_FPI	BIT(31)
#define XWAY_STP_UPD_MASK	(BIT(31) | BIT(30))

/* let the adsl core drive the 2 LSBs */
#define XWAY_STP_ADSL_SHIFT	24
#define XWAY_STP_ADSL_MASK	0x3

/* 2 groups of 3 bits can be driven by the phys */
#define XWAY_STP_PHY_MASK	0x7
#define XWAY_STP_PHY1_SHIFT	27
#define XWAY_STP_PHY2_SHIFT	15

/* STP has 3 groups of 8 bits */
#define XWAY_STP_GROUP0		BIT(0)
#define XWAY_STP_GROUP1		BIT(1)
#define XWAY_STP_GROUP2		BIT(2)
#define XWAY_STP_GROUP_MASK	(0x7)

/* Edge configuration bits */
#define XWAY_STP_FALLING	BIT(26)
#define XWAY_STP_EDGE_MASK	BIT(26)

#define xway_stp_r32(m, reg)		__raw_readl(m + reg)
#define xway_stp_w32(m, val, reg)	__raw_writel(val, m + reg)
#define xway_stp_w32_mask(m, clear, set, reg) \
		ltq_w32((ltq_r32(m + reg) & ~(clear)) | (set), \
		m + reg)

struct xway_stp {
	struct gpio_chip gc;
	void __iomem *virt;
	u32 edge;	/* rising or falling edge triggered shift register */
	u32 shadow;	/* shadow the shift registers state */
	u8 groups;	/* we can drive 1-3 groups of 8bit each */
	u8 dsl;		/* the 2 LSBs can be driven by the dsl core */
	u8 phy1;	/* 3 bits can be driven by phy1 */
	u8 phy2;	/* 3 bits can be driven by phy2 */
	u8 reserved;	/* mask out the hw driven bits in gpio_request */
};

/**
 * xway_stp_set() - gpio_chip->set - set gpios.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * Set the shadow value and call ltq_ebu_apply.
 */
static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
{
	struct xway_stp *chip = gpiochip_get_data(gc);

	if (val)
		chip->shadow |= BIT(gpio);
	else
		chip->shadow &= ~BIT(gpio);
	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
	xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
}

/**
 * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * Same as xway_stp_set, always returns 0.
 */
static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
{
	xway_stp_set(gc, gpio, val);

	return 0;
}

/**
 * xway_stp_request() - gpio_chip->request
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 *
 * We mask out the HW driven pins
 */
static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
{
	struct xway_stp *chip = gpiochip_get_data(gc);

	if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
		dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
		return -ENODEV;
	}

	return 0;
}

/**
 * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
 * @virt: pointer to the remapped register range
 */
static int xway_stp_hw_init(struct xway_stp *chip)
{
	/* sane defaults */
	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
	xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
	xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);

	/* apply edge trigger settings for the shift register */
	xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
				chip->edge, XWAY_STP_CON0);

	/* apply led group settings */
	xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
				chip->groups, XWAY_STP_CON1);

	/* tell the hardware which pins are controlled by the dsl modem */
	xway_stp_w32_mask(chip->virt,
			XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
			chip->dsl << XWAY_STP_ADSL_SHIFT,
			XWAY_STP_CON0);

	/* tell the hardware which pins are controlled by the phys */
	xway_stp_w32_mask(chip->virt,
			XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
			chip->phy1 << XWAY_STP_PHY1_SHIFT,
			XWAY_STP_CON0);
	xway_stp_w32_mask(chip->virt,
			XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
			chip->phy2 << XWAY_STP_PHY2_SHIFT,
			XWAY_STP_CON1);

	/* mask out the hw driven bits in gpio_request */
	chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl;

	/*
	 * if we have pins that are driven by hw, we need to tell the stp what
	 * clock to use as a timer.
	 */
	if (chip->reserved)
		xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
			XWAY_STP_UPD_FPI, XWAY_STP_CON1);

	return 0;
}

static int xway_stp_probe(struct platform_device *pdev)
{
	struct resource *res;
	u32 shadow, groups, dsl, phy;
	struct xway_stp *chip;
	struct clk *clk;
	int ret = 0;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	chip->virt = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(chip->virt))
		return PTR_ERR(chip->virt);

	chip->gc.parent = &pdev->dev;
	chip->gc.label = "stp-xway";
	chip->gc.direction_output = xway_stp_dir_out;
	chip->gc.set = xway_stp_set;
	chip->gc.request = xway_stp_request;
	chip->gc.base = -1;
	chip->gc.owner = THIS_MODULE;

	/* store the shadow value if one was passed by the devicetree */
	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
		chip->shadow = shadow;

	/* find out which gpio groups should be enabled */
	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
		chip->groups = groups & XWAY_STP_GROUP_MASK;
	else
		chip->groups = XWAY_STP_GROUP0;
	chip->gc.ngpio = fls(chip->groups) * 8;

	/* find out which gpios are controlled by the dsl core */
	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
		chip->dsl = dsl & XWAY_STP_ADSL_MASK;

	/* find out which gpios are controlled by the phys */
	if (of_machine_is_compatible("lantiq,ar9") ||
			of_machine_is_compatible("lantiq,gr9") ||
			of_machine_is_compatible("lantiq,vr9")) {
		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
			chip->phy1 = phy & XWAY_STP_PHY_MASK;
		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
			chip->phy2 = phy & XWAY_STP_PHY_MASK;
	}

	/* check which edge trigger we should use, default to a falling edge */
	if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
		chip->edge = XWAY_STP_FALLING;

	clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Failed to get clock\n");
		return PTR_ERR(clk);
	}
	clk_enable(clk);

	ret = xway_stp_hw_init(chip);
	if (!ret)
		ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);

	if (!ret)
		dev_info(&pdev->dev, "Init done\n");

	return ret;
}

static const struct of_device_id xway_stp_match[] = {
	{ .compatible = "lantiq,gpio-stp-xway" },
	{},
};
MODULE_DEVICE_TABLE(of, xway_stp_match);

static struct platform_driver xway_stp_driver = {
	.probe = xway_stp_probe,
	.driver = {
		.name = "gpio-stp-xway",
		.of_match_table = xway_stp_match,
	},
};

static int __init xway_stp_init(void)
{
	return platform_driver_register(&xway_stp_driver);
}

subsys_initcall(xway_stp_init);
Commit	Line	Data
935c500c JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
baddc7ca	6	* Copyright (C) 2012 John Crispin <john@phrozen.org>
935c500c JC	7	*
	8	*/
	9
	10	#include <linux/slab.h>
	11	#include <linux/init.h>
54f30066	12	#include <linux/module.h>
935c500c	13	#include <linux/types.h>
54f30066	14	#include <linux/of_platform.h>
935c500c	15	#include <linux/mutex.h>
935c500c	16	#include <linux/gpio.h>
54f30066 JC	17	#include <linux/io.h>
	18	#include <linux/of_gpio.h>
	19	#include <linux/clk.h>
	20	#include <linux/err.h>
935c500c JC	21
	22	#include <lantiq_soc.h>
	23
54f30066 JC	24	/*
	25	* The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
	26	* peripheral controller used to drive external shift register cascades. At most
	27	* 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
	28	* to drive the 2 LSBs of the cascade automatically.
	29	*/
	30
	31	/* control register 0 */
	32	#define XWAY_STP_CON0 0x00
	33	/* control register 1 */
	34	#define XWAY_STP_CON1 0x04
	35	/* data register 0 */
	36	#define XWAY_STP_CPU0 0x08
	37	/* data register 1 */
	38	#define XWAY_STP_CPU1 0x0C
	39	/* access register */
	40	#define XWAY_STP_AR 0x10
	41
	42	/* software or hardware update select bit */
	43	#define XWAY_STP_CON_SWU BIT(31)
	44
	45	/* automatic update rates */
	46	#define XWAY_STP_2HZ 0
	47	#define XWAY_STP_4HZ BIT(23)
	48	#define XWAY_STP_8HZ BIT(24)
	49	#define XWAY_STP_10HZ (BIT(24) \| BIT(23))
	50	#define XWAY_STP_SPEED_MASK (0xf << 23)
	51
	52	/* clock source for automatic update */
	53	#define XWAY_STP_UPD_FPI BIT(31)
	54	#define XWAY_STP_UPD_MASK (BIT(31) \| BIT(30))
	55
	56	/* let the adsl core drive the 2 LSBs */
	57	#define XWAY_STP_ADSL_SHIFT 24
	58	#define XWAY_STP_ADSL_MASK 0x3
	59
	60	/* 2 groups of 3 bits can be driven by the phys */
08b085a0	61	#define XWAY_STP_PHY_MASK 0x7
54f30066 JC	62	#define XWAY_STP_PHY1_SHIFT 27
	63	#define XWAY_STP_PHY2_SHIFT 15
	64
	65	/* STP has 3 groups of 8 bits */
	66	#define XWAY_STP_GROUP0 BIT(0)
	67	#define XWAY_STP_GROUP1 BIT(1)
	68	#define XWAY_STP_GROUP2 BIT(2)
	69	#define XWAY_STP_GROUP_MASK (0x7)
	70
	71	/* Edge configuration bits */
	72	#define XWAY_STP_FALLING BIT(26)
	73	#define XWAY_STP_EDGE_MASK BIT(26)
	74
	75	#define xway_stp_r32(m, reg) __raw_readl(m + reg)
	76	#define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg)
	77	#define xway_stp_w32_mask(m, clear, set, reg) \
	78	ltq_w32((ltq_r32(m + reg) & ~(clear)) \| (set), \
	79	m + reg)
	80
	81	struct xway_stp {
	82	struct gpio_chip gc;
	83	void __iomem *virt;
	84	u32 edge; /* rising or falling edge triggered shift register */
c9e854cf	85	u32 shadow; /* shadow the shift registers state */
54f30066 JC	86	u8 groups; /* we can drive 1-3 groups of 8bit each */
	87	u8 dsl; /* the 2 LSBs can be driven by the dsl core */
	88	u8 phy1; /* 3 bits can be driven by phy1 */
	89	u8 phy2; /* 3 bits can be driven by phy2 */
	90	u8 reserved; /* mask out the hw driven bits in gpio_request */
	91	};
	92
	93	/**
	94	* xway_stp_set() - gpio_chip->set - set gpios.
	95	* @gc: Pointer to gpio_chip device structure.
	96	* @gpio: GPIO signal number.
	97	* @val: Value to be written to specified signal.
	98	*
	99	* Set the shadow value and call ltq_ebu_apply.
	100	*/
	101	static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
935c500c	102	{
c63b30b0	103	struct xway_stp *chip = gpiochip_get_data(gc);
54f30066 JC	104
	105	if (val)
	106	chip->shadow \|= BIT(gpio);
935c500c	107	else
54f30066 JC	108	chip->shadow &= ~BIT(gpio);
	109	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
	110	xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
935c500c JC	111	}
935c500c JC	112
54f30066 JC	113	/**
	114	* xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
	115	* @gc: Pointer to gpio_chip device structure.
	116	* @gpio: GPIO signal number.
	117	* @val: Value to be written to specified signal.
	118	*
	119	* Same as xway_stp_set, always returns 0.
	120	*/
	121	static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
935c500c	122	{
54f30066	123	xway_stp_set(gc, gpio, val);
935c500c JC	124
	125	return 0;
	126	}
	127
54f30066 JC	128	/**
	129	* xway_stp_request() - gpio_chip->request
	130	* @gc: Pointer to gpio_chip device structure.
	131	* @gpio: GPIO signal number.
	132	*
	133	* We mask out the HW driven pins
	134	*/
	135	static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
	136	{
c63b30b0	137	struct xway_stp *chip = gpiochip_get_data(gc);
54f30066 JC	138
54f30066 JC	139	if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
58383c78	140	dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
54f30066 JC	141	return -ENODEV;
54f30066 JC	142	}
935c500c	143
54f30066 JC	144	return 0;
	145	}
	146
	147	/**
	148	* xway_stp_hw_init() - Configure the STP unit and enable the clock gate
	149	* @virt: pointer to the remapped register range
	150	*/
	151	static int xway_stp_hw_init(struct xway_stp *chip)
935c500c	152	{
935c500c	153	/* sane defaults */
54f30066 JC	154	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
	155	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
	156	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
	157	xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
	158	xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
935c500c	159
54f30066 JC	160	/* apply edge trigger settings for the shift register */
	161	xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
	162	chip->edge, XWAY_STP_CON0);
935c500c	163
54f30066 JC	164	/* apply led group settings */
	165	xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
	166	chip->groups, XWAY_STP_CON1);
935c500c	167
54f30066 JC	168	/* tell the hardware which pins are controlled by the dsl modem */
	169	xway_stp_w32_mask(chip->virt,
	170	XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
	171	chip->dsl << XWAY_STP_ADSL_SHIFT,
	172	XWAY_STP_CON0);
935c500c	173
54f30066 JC	174	/* tell the hardware which pins are controlled by the phys */
	175	xway_stp_w32_mask(chip->virt,
	176	XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
	177	chip->phy1 << XWAY_STP_PHY1_SHIFT,
	178	XWAY_STP_CON0);
	179	xway_stp_w32_mask(chip->virt,
	180	XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
	181	chip->phy2 << XWAY_STP_PHY2_SHIFT,
	182	XWAY_STP_CON1);
935c500c	183
54f30066 JC	184	/* mask out the hw driven bits in gpio_request */
	185	chip->reserved = (chip->phy2 << 5) \| (chip->phy1 << 2) \| chip->dsl;
	186
	187	/*
	188	* if we have pins that are driven by hw, we need to tell the stp what
	189	* clock to use as a timer.
935c500c	190	*/
54f30066 JC	191	if (chip->reserved)
	192	xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
	193	XWAY_STP_UPD_FPI, XWAY_STP_CON1);
935c500c	194
935c500c JC	195	return 0;
	196	}
	197
3836309d	198	static int xway_stp_probe(struct platform_device *pdev)
935c500c	199	{
d9b53c3c	200	struct resource *res;
50f09073	201	u32 shadow, groups, dsl, phy;
54f30066 JC	202	struct xway_stp *chip;
54f30066 JC	203	struct clk *clk;
935c500c JC	204	int ret = 0;
935c500c JC	205
54f30066 JC	206	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	207	if (!chip)
	208	return -ENOMEM;
	209
d9b53c3c	210	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641d0342 TR	211	chip->virt = devm_ioremap_resource(&pdev->dev, res);
	212	if (IS_ERR(chip->virt))
	213	return PTR_ERR(chip->virt);
8ab2a6d2	214
58383c78	215	chip->gc.parent = &pdev->dev;
54f30066 JC	216	chip->gc.label = "stp-xway";
	217	chip->gc.direction_output = xway_stp_dir_out;
	218	chip->gc.set = xway_stp_set;
	219	chip->gc.request = xway_stp_request;
	220	chip->gc.base = -1;
	221	chip->gc.owner = THIS_MODULE;
	222
	223	/* store the shadow value if one was passed by the devicetree */
50f09073 MB	224	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
50f09073 MB	225	chip->shadow = shadow;
54f30066 JC	226
54f30066 JC	227	/* find out which gpio groups should be enabled */
50f09073 MB	228	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
50f09073 MB	229	chip->groups = groups & XWAY_STP_GROUP_MASK;
54f30066 JC	230	else
	231	chip->groups = XWAY_STP_GROUP0;
	232	chip->gc.ngpio = fls(chip->groups) * 8;
	233
	234	/* find out which gpios are controlled by the dsl core */
50f09073 MB	235	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
50f09073 MB	236	chip->dsl = dsl & XWAY_STP_ADSL_MASK;
54f30066 JC	237
	238	/* find out which gpios are controlled by the phys */
	239	if (of_machine_is_compatible("lantiq,ar9") \|\|
	240	of_machine_is_compatible("lantiq,gr9") \|\|
	241	of_machine_is_compatible("lantiq,vr9")) {
50f09073 MB	242	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
	243	chip->phy1 = phy & XWAY_STP_PHY_MASK;
	244	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
	245	chip->phy2 = phy & XWAY_STP_PHY_MASK;
54f30066 JC	246	}
	247
	248	/* check which edge trigger we should use, default to a falling edge */
	249	if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
	250	chip->edge = XWAY_STP_FALLING;
	251
	252	clk = clk_get(&pdev->dev, NULL);
	253	if (IS_ERR(clk)) {
	254	dev_err(&pdev->dev, "Failed to get clock\n");
	255	return PTR_ERR(clk);
	256	}
	257	clk_enable(clk);
	258
	259	ret = xway_stp_hw_init(chip);
935c500c	260	if (!ret)
1a20cb2d	261	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
54f30066 JC	262
	263	if (!ret)
	264	dev_info(&pdev->dev, "Init done\n");
935c500c JC	265
	266	return ret;
	267	}
	268
54f30066 JC	269	static const struct of_device_id xway_stp_match[] = {
	270	{ .compatible = "lantiq,gpio-stp-xway" },
	271	{},
	272	};
	273	MODULE_DEVICE_TABLE(of, xway_stp_match);
	274
	275	static struct platform_driver xway_stp_driver = {
	276	.probe = xway_stp_probe,
935c500c	277	.driver = {
54f30066	278	.name = "gpio-stp-xway",
54f30066	279	.of_match_table = xway_stp_match,
935c500c JC	280	},
	281	};
	282
afdadc06	283	static int __init xway_stp_init(void)
935c500c	284	{
54f30066	285	return platform_driver_register(&xway_stp_driver);
935c500c JC	286	}
935c500c JC	287
54f30066	288	subsys_initcall(xway_stp_init);