[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-syscon.c

/*
 *  SYSCON GPIO driver
 *
 *  Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#define GPIO_SYSCON_FEAT_IN	BIT(0)
#define GPIO_SYSCON_FEAT_OUT	BIT(1)
#define GPIO_SYSCON_FEAT_DIR	BIT(2)

/* SYSCON driver is designed to use 32-bit wide registers */
#define SYSCON_REG_SIZE		(4)
#define SYSCON_REG_BITS		(SYSCON_REG_SIZE * 8)

/**
 * struct syscon_gpio_data - Configuration for the device.
 * compatible:		SYSCON driver compatible string.
 * flags:		Set of GPIO_SYSCON_FEAT_ flags:
 *			GPIO_SYSCON_FEAT_IN:	GPIOs supports input,
 *			GPIO_SYSCON_FEAT_OUT:	GPIOs supports output,
 *			GPIO_SYSCON_FEAT_DIR:	GPIOs supports switch direction.
 * bit_count:		Number of bits used as GPIOs.
 * dat_bit_offset:	Offset (in bits) to the first GPIO bit.
 * dir_bit_offset:	Optional offset (in bits) to the first bit to switch
 *			GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
 * set:		HW specific callback to assigns output value
 *			for signal "offset"
 */

struct syscon_gpio_data {
	const char	*compatible;
	unsigned int	flags;
	unsigned int	bit_count;
	unsigned int	dat_bit_offset;
	unsigned int	dir_bit_offset;
	void		(*set)(struct gpio_chip *chip,
			       unsigned offset, int value);
};

struct syscon_gpio_priv {
	struct gpio_chip		chip;
	struct regmap			*syscon;
	const struct syscon_gpio_data	*data;
	u32				dreg_offset;
	u32				dir_reg_offset;
};

static inline struct syscon_gpio_priv *to_syscon_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct syscon_gpio_priv, chip);
}

static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
	unsigned int val, offs;
	int ret;

	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;

	ret = regmap_read(priv->syscon,
			  (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
	if (ret)
		return ret;

	return !!(val & BIT(offs % SYSCON_REG_BITS));
}

static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
	unsigned int offs;

	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;

	regmap_update_bits(priv->syscon,
			   (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
			   BIT(offs % SYSCON_REG_BITS),
			   val ? BIT(offs % SYSCON_REG_BITS) : 0);
}

static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
{
	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);

	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
		unsigned int offs;

		offs = priv->dir_reg_offset +
		       priv->data->dir_bit_offset + offset;

		regmap_update_bits(priv->syscon,
				   (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
				   BIT(offs % SYSCON_REG_BITS), 0);
	}

	return 0;
}

static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
{
	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);

	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
		unsigned int offs;

		offs = priv->dir_reg_offset +
		       priv->data->dir_bit_offset + offset;

		regmap_update_bits(priv->syscon,
				   (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
				   BIT(offs % SYSCON_REG_BITS),
				   BIT(offs % SYSCON_REG_BITS));
	}

	priv->data->set(chip, offset, val);

	return 0;
}

static const struct syscon_gpio_data clps711x_mctrl_gpio = {
	/* ARM CLPS711X SYSFLG1 Bits 8-10 */
	.compatible	= "cirrus,clps711x-syscon1",
	.flags		= GPIO_SYSCON_FEAT_IN,
	.bit_count	= 3,
	.dat_bit_offset	= 0x40 * 8 + 8,
};

#define KEYSTONE_LOCK_BIT BIT(0)

static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
	unsigned int offs;
	int ret;

	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;

	if (!val)
		return;

	ret = regmap_update_bits(
			priv->syscon,
			(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
			BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT,
			BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT);
	if (ret < 0)
		dev_err(chip->dev, "gpio write failed ret(%d)\n", ret);
}

static const struct syscon_gpio_data keystone_dsp_gpio = {
	/* ARM Keystone 2 */
	.compatible	= NULL,
	.flags		= GPIO_SYSCON_FEAT_OUT,
	.bit_count	= 28,
	.dat_bit_offset	= 4,
	.set		= keystone_gpio_set,
};

static const struct of_device_id syscon_gpio_ids[] = {
	{
		.compatible	= "cirrus,clps711x-mctrl-gpio",
		.data		= &clps711x_mctrl_gpio,
	},
	{
		.compatible	= "ti,keystone-dsp-gpio",
		.data		= &keystone_dsp_gpio,
	},
	{ }
};
MODULE_DEVICE_TABLE(of, syscon_gpio_ids);

static int syscon_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *of_id;
	struct syscon_gpio_priv *priv;
	struct device_node *np = dev->of_node;
	int ret;

	of_id = of_match_device(syscon_gpio_ids, dev);
	if (!of_id)
		return -ENODEV;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->data = of_id->data;

	if (priv->data->compatible) {
		priv->syscon = syscon_regmap_lookup_by_compatible(
					priv->data->compatible);
		if (IS_ERR(priv->syscon))
			return PTR_ERR(priv->syscon);
	} else {
		priv->syscon =
			syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
		if (IS_ERR(priv->syscon))
			return PTR_ERR(priv->syscon);

		ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,
						 &priv->dreg_offset);
		if (ret)
			dev_err(dev, "can't read the data register offset!\n");

		priv->dreg_offset <<= 3;

		ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,
						 &priv->dir_reg_offset);
		if (ret)
			dev_dbg(dev, "can't read the dir register offset!\n");

		priv->dir_reg_offset <<= 3;
	}

	priv->chip.dev = dev;
	priv->chip.owner = THIS_MODULE;
	priv->chip.label = dev_name(dev);
	priv->chip.base = -1;
	priv->chip.ngpio = priv->data->bit_count;
	priv->chip.get = syscon_gpio_get;
	if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
		priv->chip.direction_input = syscon_gpio_dir_in;
	if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
		priv->chip.set = priv->data->set ? : syscon_gpio_set;
		priv->chip.direction_output = syscon_gpio_dir_out;
	}

	platform_set_drvdata(pdev, priv);

	return gpiochip_add(&priv->chip);
}

static int syscon_gpio_remove(struct platform_device *pdev)
{
	struct syscon_gpio_priv *priv = platform_get_drvdata(pdev);

	gpiochip_remove(&priv->chip);
	return 0;
}

static struct platform_driver syscon_gpio_driver = {
	.driver	= {
		.name		= "gpio-syscon",
		.of_match_table	= syscon_gpio_ids,
	},
	.probe	= syscon_gpio_probe,
	.remove	= syscon_gpio_remove,
};
module_platform_driver(syscon_gpio_driver);

MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
MODULE_DESCRIPTION("SYSCON GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
6a8a0c1d AS	1	/*
	2	* SYSCON GPIO driver
	3	*
	4	* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/err.h>
	13	#include <linux/gpio.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/of_device.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/regmap.h>
	19	#include <linux/mfd/syscon.h>
	20
	21	#define GPIO_SYSCON_FEAT_IN BIT(0)
	22	#define GPIO_SYSCON_FEAT_OUT BIT(1)
	23	#define GPIO_SYSCON_FEAT_DIR BIT(2)
	24
	25	/* SYSCON driver is designed to use 32-bit wide registers */
	26	#define SYSCON_REG_SIZE (4)
	27	#define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8)
	28
	29	/**
	30	* struct syscon_gpio_data - Configuration for the device.
	31	* compatible: SYSCON driver compatible string.
	32	* flags: Set of GPIO_SYSCON_FEAT_ flags:
	33	* GPIO_SYSCON_FEAT_IN: GPIOs supports input,
	34	* GPIO_SYSCON_FEAT_OUT: GPIOs supports output,
	35	* GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction.
	36	* bit_count: Number of bits used as GPIOs.
	37	* dat_bit_offset: Offset (in bits) to the first GPIO bit.
	38	* dir_bit_offset: Optional offset (in bits) to the first bit to switch
	39	* GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
2c341d62 GS	40	* set: HW specific callback to assigns output value
2c341d62 GS	41	* for signal "offset"
6a8a0c1d AS	42	*/
	43
	44	struct syscon_gpio_data {
	45	const char *compatible;
	46	unsigned int flags;
	47	unsigned int bit_count;
	48	unsigned int dat_bit_offset;
	49	unsigned int dir_bit_offset;
2c341d62 GS	50	void (set)(struct gpio_chip chip,
2c341d62 GS	51	unsigned offset, int value);
6a8a0c1d AS	52	};
	53
	54	struct syscon_gpio_priv {
	55	struct gpio_chip chip;
	56	struct regmap *syscon;
	57	const struct syscon_gpio_data *data;
5a3e3f88 GS	58	u32 dreg_offset;
5a3e3f88 GS	59	u32 dir_reg_offset;
6a8a0c1d AS	60	};
	61
	62	static inline struct syscon_gpio_priv to_syscon_gpio(struct gpio_chip chip)
	63	{
	64	return container_of(chip, struct syscon_gpio_priv, chip);
	65	}
	66
	67	static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
	68	{
	69	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
5a3e3f88	70	unsigned int val, offs;
6a8a0c1d AS	71	int ret;
6a8a0c1d AS	72
5a3e3f88 GS	73	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
5a3e3f88 GS	74
6a8a0c1d AS	75	ret = regmap_read(priv->syscon,
	76	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
	77	if (ret)
	78	return ret;
	79
	80	return !!(val & BIT(offs % SYSCON_REG_BITS));
	81	}
	82
	83	static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	84	{
	85	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
5a3e3f88 GS	86	unsigned int offs;
	87
	88	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
6a8a0c1d AS	89
	90	regmap_update_bits(priv->syscon,
	91	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
	92	BIT(offs % SYSCON_REG_BITS),
	93	val ? BIT(offs % SYSCON_REG_BITS) : 0);
	94	}
	95
	96	static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
	97	{
	98	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
	99
	100	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
5a3e3f88 GS	101	unsigned int offs;
	102
	103	offs = priv->dir_reg_offset +
	104	priv->data->dir_bit_offset + offset;
6a8a0c1d AS	105
	106	regmap_update_bits(priv->syscon,
	107	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
	108	BIT(offs % SYSCON_REG_BITS), 0);
	109	}
	110
	111	return 0;
	112	}
	113
	114	static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
	115	{
	116	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
	117
	118	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
5a3e3f88 GS	119	unsigned int offs;
	120
	121	offs = priv->dir_reg_offset +
	122	priv->data->dir_bit_offset + offset;
6a8a0c1d AS	123
	124	regmap_update_bits(priv->syscon,
	125	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
	126	BIT(offs % SYSCON_REG_BITS),
	127	BIT(offs % SYSCON_REG_BITS));
	128	}
	129
2c341d62	130	priv->data->set(chip, offset, val);
6a8a0c1d AS	131
	132	return 0;
	133	}
	134
	135	static const struct syscon_gpio_data clps711x_mctrl_gpio = {
	136	/* ARM CLPS711X SYSFLG1 Bits 8-10 */
	137	.compatible = "cirrus,clps711x-syscon1",
	138	.flags = GPIO_SYSCON_FEAT_IN,
	139	.bit_count = 3,
	140	.dat_bit_offset = 0x40 * 8 + 8,
	141	};
	142
2134cb99 GS	143	#define KEYSTONE_LOCK_BIT BIT(0)
	144
	145	static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	146	{
	147	struct syscon_gpio_priv *priv = to_syscon_gpio(chip);
	148	unsigned int offs;
	149	int ret;
	150
	151	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
	152
	153	if (!val)
	154	return;
	155
	156	ret = regmap_update_bits(
	157	priv->syscon,
	158	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
	159	BIT(offs % SYSCON_REG_BITS) \| KEYSTONE_LOCK_BIT,
	160	BIT(offs % SYSCON_REG_BITS) \| KEYSTONE_LOCK_BIT);
	161	if (ret < 0)
	162	dev_err(chip->dev, "gpio write failed ret(%d)\n", ret);
	163	}
	164
	165	static const struct syscon_gpio_data keystone_dsp_gpio = {
	166	/* ARM Keystone 2 */
	167	.compatible = NULL,
	168	.flags = GPIO_SYSCON_FEAT_OUT,
	169	.bit_count = 28,
	170	.dat_bit_offset = 4,
	171	.set = keystone_gpio_set,
	172	};
	173
6a8a0c1d AS	174	static const struct of_device_id syscon_gpio_ids[] = {
	175	{
	176	.compatible = "cirrus,clps711x-mctrl-gpio",
	177	.data = &clps711x_mctrl_gpio,
	178	},
2134cb99 GS	179	{
	180	.compatible = "ti,keystone-dsp-gpio",
	181	.data = &keystone_dsp_gpio,
	182	},
6a8a0c1d AS	183	{ }
	184	};
	185	MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
	186
	187	static int syscon_gpio_probe(struct platform_device *pdev)
	188	{
	189	struct device *dev = &pdev->dev;
853f0cb8	190	const struct of_device_id *of_id;
6a8a0c1d	191	struct syscon_gpio_priv *priv;
5a3e3f88 GS	192	struct device_node *np = dev->of_node;
5a3e3f88 GS	193	int ret;
6a8a0c1d	194
853f0cb8 LC	195	of_id = of_match_device(syscon_gpio_ids, dev);
	196	if (!of_id)
	197	return -ENODEV;
	198
6a8a0c1d AS	199	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	200	if (!priv)
	201	return -ENOMEM;
	202
	203	priv->data = of_id->data;
	204
5a3e3f88 GS	205	if (priv->data->compatible) {
	206	priv->syscon = syscon_regmap_lookup_by_compatible(
	207	priv->data->compatible);
	208	if (IS_ERR(priv->syscon))
	209	return PTR_ERR(priv->syscon);
	210	} else {
	211	priv->syscon =
	212	syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
	213	if (IS_ERR(priv->syscon))
	214	return PTR_ERR(priv->syscon);
	215
	216	ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,
	217	&priv->dreg_offset);
	218	if (ret)
	219	dev_err(dev, "can't read the data register offset!\n");
	220
	221	priv->dreg_offset <<= 3;
	222
	223	ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,
	224	&priv->dir_reg_offset);
	225	if (ret)
c6ac19da	226	dev_dbg(dev, "can't read the dir register offset!\n");
5a3e3f88 GS	227
	228	priv->dir_reg_offset <<= 3;
	229	}
6a8a0c1d AS	230
	231	priv->chip.dev = dev;
	232	priv->chip.owner = THIS_MODULE;
	233	priv->chip.label = dev_name(dev);
	234	priv->chip.base = -1;
	235	priv->chip.ngpio = priv->data->bit_count;
	236	priv->chip.get = syscon_gpio_get;
	237	if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
	238	priv->chip.direction_input = syscon_gpio_dir_in;
	239	if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
2c341d62	240	priv->chip.set = priv->data->set ? : syscon_gpio_set;
6a8a0c1d AS	241	priv->chip.direction_output = syscon_gpio_dir_out;
	242	}
	243
	244	platform_set_drvdata(pdev, priv);
	245
	246	return gpiochip_add(&priv->chip);
	247	}
	248
	249	static int syscon_gpio_remove(struct platform_device *pdev)
	250	{
	251	struct syscon_gpio_priv *priv = platform_get_drvdata(pdev);
	252
9f5132ae	253	gpiochip_remove(&priv->chip);
9f5132ae	254	return 0;
6a8a0c1d AS	255	}
	256
	257	static struct platform_driver syscon_gpio_driver = {
	258	.driver = {
	259	.name = "gpio-syscon",
6a8a0c1d AS	260	.of_match_table = syscon_gpio_ids,
	261	},
	262	.probe = syscon_gpio_probe,
	263	.remove = syscon_gpio_remove,
	264	};
	265	module_platform_driver(syscon_gpio_driver);
	266
	267	MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
	268	MODULE_DESCRIPTION("SYSCON GPIO driver");
	269	MODULE_LICENSE("GPL");