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d88b25be RV |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License, version 2 | |
5 | * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson | |
6 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
7 | */ | |
8 | ||
d88b25be RV |
9 | #include <linux/init.h> |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/slab.h> | |
cee1b40d | 12 | #include <linux/gpio/driver.h> |
3113e679 | 13 | #include <linux/of.h> |
d88b25be | 14 | #include <linux/interrupt.h> |
c6eda6c5 | 15 | #include <linux/mfd/tc3589x.h> |
cee1b40d | 16 | #include <linux/bitops.h> |
d88b25be RV |
17 | |
18 | /* | |
19 | * These registers are modified under the irq bus lock and cached to avoid | |
20 | * unnecessary writes in bus_sync_unlock. | |
21 | */ | |
22 | enum { REG_IBE, REG_IEV, REG_IS, REG_IE }; | |
23 | ||
24 | #define CACHE_NR_REGS 4 | |
25 | #define CACHE_NR_BANKS 3 | |
26 | ||
20406ebf | 27 | struct tc3589x_gpio { |
d88b25be | 28 | struct gpio_chip chip; |
20406ebf | 29 | struct tc3589x *tc3589x; |
d88b25be RV |
30 | struct device *dev; |
31 | struct mutex irq_lock; | |
d88b25be RV |
32 | /* Caches of interrupt control registers for bus_lock */ |
33 | u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
34 | u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
35 | }; | |
36 | ||
0e4011eb | 37 | static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset) |
d88b25be | 38 | { |
b0d38473 | 39 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
40 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
41 | u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; | |
cee1b40d | 42 | u8 mask = BIT(offset % 8); |
d88b25be RV |
43 | int ret; |
44 | ||
20406ebf | 45 | ret = tc3589x_reg_read(tc3589x, reg); |
d88b25be RV |
46 | if (ret < 0) |
47 | return ret; | |
48 | ||
27ca2267 | 49 | return !!(ret & mask); |
d88b25be RV |
50 | } |
51 | ||
0e4011eb | 52 | static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) |
d88b25be | 53 | { |
b0d38473 | 54 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
55 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
56 | u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; | |
0e4011eb | 57 | unsigned int pos = offset % 8; |
cee1b40d | 58 | u8 data[] = {val ? BIT(pos) : 0, BIT(pos)}; |
d88b25be | 59 | |
20406ebf | 60 | tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data); |
d88b25be RV |
61 | } |
62 | ||
20406ebf | 63 | static int tc3589x_gpio_direction_output(struct gpio_chip *chip, |
0e4011eb | 64 | unsigned int offset, int val) |
d88b25be | 65 | { |
b0d38473 | 66 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
67 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
68 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
0e4011eb | 69 | unsigned int pos = offset % 8; |
d88b25be | 70 | |
20406ebf | 71 | tc3589x_gpio_set(chip, offset, val); |
d88b25be | 72 | |
cee1b40d | 73 | return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos)); |
d88b25be RV |
74 | } |
75 | ||
20406ebf | 76 | static int tc3589x_gpio_direction_input(struct gpio_chip *chip, |
0e4011eb | 77 | unsigned int offset) |
d88b25be | 78 | { |
b0d38473 | 79 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
80 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
81 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
0e4011eb | 82 | unsigned int pos = offset % 8; |
d88b25be | 83 | |
cee1b40d | 84 | return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0); |
d88b25be RV |
85 | } |
86 | ||
14063d71 | 87 | static int tc3589x_gpio_get_direction(struct gpio_chip *chip, |
0e4011eb | 88 | unsigned int offset) |
14063d71 LW |
89 | { |
90 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); | |
91 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
92 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
0e4011eb | 93 | unsigned int pos = offset % 8; |
14063d71 LW |
94 | int ret; |
95 | ||
96 | ret = tc3589x_reg_read(tc3589x, reg); | |
97 | if (ret < 0) | |
98 | return ret; | |
99 | ||
100 | return !!(ret & BIT(pos)); | |
101 | } | |
102 | ||
103 | static int tc3589x_gpio_set_single_ended(struct gpio_chip *chip, | |
0e4011eb | 104 | unsigned int offset, |
14063d71 | 105 | enum single_ended_mode mode) |
8b866b06 LW |
106 | { |
107 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); | |
108 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
109 | /* | |
110 | * These registers are alterated at each second address | |
111 | * ODM bit 0 = drive to GND or Hi-Z (open drain) | |
112 | * ODM bit 1 = drive to VDD or Hi-Z (open source) | |
113 | */ | |
114 | u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2; | |
115 | u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2; | |
0e4011eb | 116 | unsigned int pos = offset % 8; |
8b866b06 LW |
117 | int ret; |
118 | ||
119 | switch(mode) { | |
120 | case LINE_MODE_OPEN_DRAIN: | |
121 | /* Set open drain mode */ | |
122 | ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0); | |
123 | if (ret) | |
124 | return ret; | |
125 | /* Enable open drain/source mode */ | |
126 | return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos)); | |
127 | case LINE_MODE_OPEN_SOURCE: | |
128 | /* Set open source mode */ | |
129 | ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos)); | |
130 | if (ret) | |
131 | return ret; | |
132 | /* Enable open drain/source mode */ | |
133 | return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos)); | |
134 | case LINE_MODE_PUSH_PULL: | |
135 | /* Disable open drain/source mode */ | |
136 | return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0); | |
137 | default: | |
138 | break; | |
139 | } | |
140 | return -ENOTSUPP; | |
141 | } | |
142 | ||
e35b5ab0 | 143 | static const struct gpio_chip template_chip = { |
20406ebf | 144 | .label = "tc3589x", |
d88b25be | 145 | .owner = THIS_MODULE, |
20406ebf | 146 | .get = tc3589x_gpio_get, |
20406ebf | 147 | .set = tc3589x_gpio_set, |
14063d71 LW |
148 | .direction_output = tc3589x_gpio_direction_output, |
149 | .direction_input = tc3589x_gpio_direction_input, | |
150 | .get_direction = tc3589x_gpio_get_direction, | |
151 | .set_single_ended = tc3589x_gpio_set_single_ended, | |
9fb1f39e | 152 | .can_sleep = true, |
d88b25be RV |
153 | }; |
154 | ||
33fcc1b8 | 155 | static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
d88b25be | 156 | { |
cf42f1cf | 157 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 158 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
efe4c949 | 159 | int offset = d->hwirq; |
d88b25be | 160 | int regoffset = offset / 8; |
cee1b40d | 161 | int mask = BIT(offset % 8); |
d88b25be RV |
162 | |
163 | if (type == IRQ_TYPE_EDGE_BOTH) { | |
20406ebf | 164 | tc3589x_gpio->regs[REG_IBE][regoffset] |= mask; |
d88b25be RV |
165 | return 0; |
166 | } | |
167 | ||
20406ebf | 168 | tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask; |
d88b25be RV |
169 | |
170 | if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) | |
20406ebf | 171 | tc3589x_gpio->regs[REG_IS][regoffset] |= mask; |
d88b25be | 172 | else |
20406ebf | 173 | tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask; |
d88b25be RV |
174 | |
175 | if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) | |
20406ebf | 176 | tc3589x_gpio->regs[REG_IEV][regoffset] |= mask; |
d88b25be | 177 | else |
20406ebf | 178 | tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask; |
d88b25be RV |
179 | |
180 | return 0; | |
181 | } | |
182 | ||
33fcc1b8 | 183 | static void tc3589x_gpio_irq_lock(struct irq_data *d) |
d88b25be | 184 | { |
cf42f1cf | 185 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 186 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
d88b25be | 187 | |
20406ebf | 188 | mutex_lock(&tc3589x_gpio->irq_lock); |
d88b25be RV |
189 | } |
190 | ||
33fcc1b8 | 191 | static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d) |
d88b25be | 192 | { |
cf42f1cf | 193 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 194 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
20406ebf | 195 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
d88b25be | 196 | static const u8 regmap[] = { |
20406ebf SI |
197 | [REG_IBE] = TC3589x_GPIOIBE0, |
198 | [REG_IEV] = TC3589x_GPIOIEV0, | |
199 | [REG_IS] = TC3589x_GPIOIS0, | |
200 | [REG_IE] = TC3589x_GPIOIE0, | |
d88b25be RV |
201 | }; |
202 | int i, j; | |
203 | ||
204 | for (i = 0; i < CACHE_NR_REGS; i++) { | |
205 | for (j = 0; j < CACHE_NR_BANKS; j++) { | |
20406ebf SI |
206 | u8 old = tc3589x_gpio->oldregs[i][j]; |
207 | u8 new = tc3589x_gpio->regs[i][j]; | |
d88b25be RV |
208 | |
209 | if (new == old) | |
210 | continue; | |
211 | ||
20406ebf SI |
212 | tc3589x_gpio->oldregs[i][j] = new; |
213 | tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new); | |
d88b25be RV |
214 | } |
215 | } | |
216 | ||
20406ebf | 217 | mutex_unlock(&tc3589x_gpio->irq_lock); |
d88b25be RV |
218 | } |
219 | ||
33fcc1b8 | 220 | static void tc3589x_gpio_irq_mask(struct irq_data *d) |
d88b25be | 221 | { |
cf42f1cf | 222 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 223 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
efe4c949 | 224 | int offset = d->hwirq; |
d88b25be | 225 | int regoffset = offset / 8; |
cee1b40d | 226 | int mask = BIT(offset % 8); |
d88b25be | 227 | |
20406ebf | 228 | tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask; |
d88b25be RV |
229 | } |
230 | ||
33fcc1b8 | 231 | static void tc3589x_gpio_irq_unmask(struct irq_data *d) |
d88b25be | 232 | { |
cf42f1cf | 233 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 234 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
efe4c949 | 235 | int offset = d->hwirq; |
d88b25be | 236 | int regoffset = offset / 8; |
cee1b40d | 237 | int mask = BIT(offset % 8); |
d88b25be | 238 | |
20406ebf | 239 | tc3589x_gpio->regs[REG_IE][regoffset] |= mask; |
d88b25be RV |
240 | } |
241 | ||
20406ebf SI |
242 | static struct irq_chip tc3589x_gpio_irq_chip = { |
243 | .name = "tc3589x-gpio", | |
33fcc1b8 LB |
244 | .irq_bus_lock = tc3589x_gpio_irq_lock, |
245 | .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock, | |
246 | .irq_mask = tc3589x_gpio_irq_mask, | |
247 | .irq_unmask = tc3589x_gpio_irq_unmask, | |
248 | .irq_set_type = tc3589x_gpio_irq_set_type, | |
d88b25be RV |
249 | }; |
250 | ||
20406ebf | 251 | static irqreturn_t tc3589x_gpio_irq(int irq, void *dev) |
d88b25be | 252 | { |
20406ebf SI |
253 | struct tc3589x_gpio *tc3589x_gpio = dev; |
254 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
d88b25be RV |
255 | u8 status[CACHE_NR_BANKS]; |
256 | int ret; | |
257 | int i; | |
258 | ||
20406ebf | 259 | ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0, |
d88b25be RV |
260 | ARRAY_SIZE(status), status); |
261 | if (ret < 0) | |
262 | return IRQ_NONE; | |
263 | ||
264 | for (i = 0; i < ARRAY_SIZE(status); i++) { | |
265 | unsigned int stat = status[i]; | |
266 | if (!stat) | |
267 | continue; | |
268 | ||
269 | while (stat) { | |
270 | int bit = __ffs(stat); | |
271 | int line = i * 8 + bit; | |
cf42f1cf LW |
272 | int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain, |
273 | line); | |
d88b25be | 274 | |
e300376d | 275 | handle_nested_irq(irq); |
d88b25be RV |
276 | stat &= ~(1 << bit); |
277 | } | |
278 | ||
20406ebf | 279 | tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]); |
d88b25be RV |
280 | } |
281 | ||
282 | return IRQ_HANDLED; | |
283 | } | |
284 | ||
3836309d | 285 | static int tc3589x_gpio_probe(struct platform_device *pdev) |
d88b25be | 286 | { |
20406ebf | 287 | struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent); |
3113e679 | 288 | struct device_node *np = pdev->dev.of_node; |
20406ebf | 289 | struct tc3589x_gpio *tc3589x_gpio; |
d88b25be RV |
290 | int ret; |
291 | int irq; | |
292 | ||
53e41f55 LW |
293 | if (!np) { |
294 | dev_err(&pdev->dev, "No Device Tree node found\n"); | |
3113e679 LJ |
295 | return -EINVAL; |
296 | } | |
d88b25be RV |
297 | |
298 | irq = platform_get_irq(pdev, 0); | |
299 | if (irq < 0) | |
300 | return irq; | |
301 | ||
033f2752 LW |
302 | tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio), |
303 | GFP_KERNEL); | |
20406ebf | 304 | if (!tc3589x_gpio) |
d88b25be RV |
305 | return -ENOMEM; |
306 | ||
20406ebf | 307 | mutex_init(&tc3589x_gpio->irq_lock); |
d88b25be | 308 | |
20406ebf SI |
309 | tc3589x_gpio->dev = &pdev->dev; |
310 | tc3589x_gpio->tc3589x = tc3589x; | |
d88b25be | 311 | |
20406ebf SI |
312 | tc3589x_gpio->chip = template_chip; |
313 | tc3589x_gpio->chip.ngpio = tc3589x->num_gpio; | |
58383c78 | 314 | tc3589x_gpio->chip.parent = &pdev->dev; |
90f2d0f7 | 315 | tc3589x_gpio->chip.base = -1; |
e90c636b | 316 | tc3589x_gpio->chip.of_node = np; |
d88b25be RV |
317 | |
318 | /* Bring the GPIO module out of reset */ | |
20406ebf SI |
319 | ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL, |
320 | TC3589x_RSTCTRL_GPIRST, 0); | |
d88b25be | 321 | if (ret < 0) |
033f2752 | 322 | return ret; |
d88b25be | 323 | |
033f2752 LW |
324 | ret = devm_request_threaded_irq(&pdev->dev, |
325 | irq, NULL, tc3589x_gpio_irq, | |
326 | IRQF_ONESHOT, "tc3589x-gpio", | |
327 | tc3589x_gpio); | |
d88b25be RV |
328 | if (ret) { |
329 | dev_err(&pdev->dev, "unable to get irq: %d\n", ret); | |
033f2752 | 330 | return ret; |
d88b25be RV |
331 | } |
332 | ||
f3378b6a LD |
333 | ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip, |
334 | tc3589x_gpio); | |
d88b25be RV |
335 | if (ret) { |
336 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); | |
033f2752 | 337 | return ret; |
d88b25be RV |
338 | } |
339 | ||
cf42f1cf LW |
340 | ret = gpiochip_irqchip_add(&tc3589x_gpio->chip, |
341 | &tc3589x_gpio_irq_chip, | |
342 | 0, | |
343 | handle_simple_irq, | |
344 | IRQ_TYPE_NONE); | |
345 | if (ret) { | |
346 | dev_err(&pdev->dev, | |
347 | "could not connect irqchip to gpiochip\n"); | |
348 | return ret; | |
349 | } | |
350 | ||
3f97d5fc LW |
351 | gpiochip_set_chained_irqchip(&tc3589x_gpio->chip, |
352 | &tc3589x_gpio_irq_chip, | |
353 | irq, | |
354 | NULL); | |
355 | ||
20406ebf | 356 | platform_set_drvdata(pdev, tc3589x_gpio); |
d88b25be RV |
357 | |
358 | return 0; | |
d88b25be RV |
359 | } |
360 | ||
20406ebf SI |
361 | static struct platform_driver tc3589x_gpio_driver = { |
362 | .driver.name = "tc3589x-gpio", | |
20406ebf | 363 | .probe = tc3589x_gpio_probe, |
d88b25be RV |
364 | }; |
365 | ||
20406ebf | 366 | static int __init tc3589x_gpio_init(void) |
d88b25be | 367 | { |
20406ebf | 368 | return platform_driver_register(&tc3589x_gpio_driver); |
d88b25be | 369 | } |
20406ebf | 370 | subsys_initcall(tc3589x_gpio_init); |