[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-tc3589x.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>
#include <linux/bitops.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_IBE, REG_IEV, REG_IS, REG_IE };

#define CACHE_NR_REGS	4
#define CACHE_NR_BANKS	3

struct tc3589x_gpio {
	struct gpio_chip chip;
	struct tc3589x *tc3589x;
	struct device *dev;
	struct mutex irq_lock;
	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	u8 mask = BIT(offset % 8);
	int ret;

	ret = tc3589x_reg_read(tc3589x, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	unsigned int pos = offset % 8;
	u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};

	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
}

static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
					 unsigned int offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned int pos = offset % 8;

	tc3589x_gpio_set(chip, offset, val);

	return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
}

static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
					unsigned int offset)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned int pos = offset % 8;

	return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
}

static int tc3589x_gpio_get_direction(struct gpio_chip *chip,
				      unsigned int offset)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned int pos = offset % 8;
	int ret;

	ret = tc3589x_reg_read(tc3589x, reg);
	if (ret < 0)
		return ret;

	return !(ret & BIT(pos));
}

static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
				   unsigned long config)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	/*
	 * These registers are alterated at each second address
	 * ODM bit 0 = drive to GND or Hi-Z (open drain)
	 * ODM bit 1 = drive to VDD or Hi-Z (open source)
	 */
	u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
	u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
	unsigned int pos = offset % 8;
	int ret;

	switch (pinconf_to_config_param(config)) {
	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
		/* Set open drain mode */
		ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
		if (ret)
			return ret;
		/* Enable open drain/source mode */
		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
		/* Set open source mode */
		ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
		if (ret)
			return ret;
		/* Enable open drain/source mode */
		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
	case PIN_CONFIG_DRIVE_PUSH_PULL:
		/* Disable open drain/source mode */
		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
	default:
		break;
	}
	return -ENOTSUPP;
}

static const struct gpio_chip template_chip = {
	.label			= "tc3589x",
	.owner			= THIS_MODULE,
	.get			= tc3589x_gpio_get,
	.set			= tc3589x_gpio_set,
	.direction_output	= tc3589x_gpio_direction_output,
	.direction_input	= tc3589x_gpio_direction_input,
	.get_direction		= tc3589x_gpio_get_direction,
	.set_config		= tc3589x_gpio_set_config,
	.can_sleep		= true,
};

static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	if (type == IRQ_TYPE_EDGE_BOTH) {
		tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
		return 0;
	}

	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;

	return 0;
}

static void tc3589x_gpio_irq_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);

	mutex_lock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	static const u8 regmap[] = {
		[REG_IBE]	= TC3589x_GPIOIBE0,
		[REG_IEV]	= TC3589x_GPIOIEV0,
		[REG_IS]	= TC3589x_GPIOIS0,
		[REG_IE]	= TC3589x_GPIOIE0,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		for (j = 0; j < CACHE_NR_BANKS; j++) {
			u8 old = tc3589x_gpio->oldregs[i][j];
			u8 new = tc3589x_gpio->regs[i][j];

			if (new == old)
				continue;

			tc3589x_gpio->oldregs[i][j] = new;
			tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
		}
	}

	mutex_unlock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void tc3589x_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip tc3589x_gpio_irq_chip = {
	.name			= "tc3589x-gpio",
	.irq_bus_lock		= tc3589x_gpio_irq_lock,
	.irq_bus_sync_unlock	= tc3589x_gpio_irq_sync_unlock,
	.irq_mask		= tc3589x_gpio_irq_mask,
	.irq_unmask		= tc3589x_gpio_irq_unmask,
	.irq_set_type		= tc3589x_gpio_irq_set_type,
};

static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
{
	struct tc3589x_gpio *tc3589x_gpio = dev;
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 status[CACHE_NR_BANKS];
	int ret;
	int i;

	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
				 ARRAY_SIZE(status), status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < ARRAY_SIZE(status); i++) {
		unsigned int stat = status[i];
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = i * 8 + bit;
			int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
						   line);

			handle_nested_irq(irq);
			stat &= ~(1 << bit);
		}

		tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
	}

	return IRQ_HANDLED;
}

static int tc3589x_gpio_probe(struct platform_device *pdev)
{
	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct tc3589x_gpio *tc3589x_gpio;
	int ret;
	int irq;

	if (!np) {
		dev_err(&pdev->dev, "No Device Tree node found\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
				    GFP_KERNEL);
	if (!tc3589x_gpio)
		return -ENOMEM;

	mutex_init(&tc3589x_gpio->irq_lock);

	tc3589x_gpio->dev = &pdev->dev;
	tc3589x_gpio->tc3589x = tc3589x;

	tc3589x_gpio->chip = template_chip;
	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
	tc3589x_gpio->chip.parent = &pdev->dev;
	tc3589x_gpio->chip.base = -1;
	tc3589x_gpio->chip.of_node = np;

	/* Bring the GPIO module out of reset */
	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
			       TC3589x_RSTCTRL_GPIRST, 0);
	if (ret < 0)
		return ret;

	ret = devm_request_threaded_irq(&pdev->dev,
					irq, NULL, tc3589x_gpio_irq,
					IRQF_ONESHOT, "tc3589x-gpio",
					tc3589x_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
		return ret;
	}

	ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
				     tc3589x_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		return ret;
	}

	ret =  gpiochip_irqchip_add_nested(&tc3589x_gpio->chip,
					   &tc3589x_gpio_irq_chip,
					   0,
					   handle_simple_irq,
					   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(&pdev->dev,
			"could not connect irqchip to gpiochip\n");
		return ret;
	}

	gpiochip_set_nested_irqchip(&tc3589x_gpio->chip,
				    &tc3589x_gpio_irq_chip,
				    irq);

	platform_set_drvdata(pdev, tc3589x_gpio);

	return 0;
}

static struct platform_driver tc3589x_gpio_driver = {
	.driver.name	= "tc3589x-gpio",
	.probe		= tc3589x_gpio_probe,
};

static int __init tc3589x_gpio_init(void)
{
	return platform_driver_register(&tc3589x_gpio_driver);
}
subsys_initcall(tc3589x_gpio_init);
Commit	Line	Data
d88b25be RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
	6	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	7	*/
	8
d88b25be RV	9	#include <linux/init.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/slab.h>
cee1b40d	12	#include <linux/gpio/driver.h>
3113e679	13	#include <linux/of.h>
d88b25be	14	#include <linux/interrupt.h>
c6eda6c5	15	#include <linux/mfd/tc3589x.h>
cee1b40d	16	#include <linux/bitops.h>
d88b25be RV	17
	18	/*
	19	* These registers are modified under the irq bus lock and cached to avoid
	20	* unnecessary writes in bus_sync_unlock.
	21	*/
	22	enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
	23
	24	#define CACHE_NR_REGS 4
	25	#define CACHE_NR_BANKS 3
	26
20406ebf	27	struct tc3589x_gpio {
d88b25be	28	struct gpio_chip chip;
20406ebf	29	struct tc3589x *tc3589x;
d88b25be RV	30	struct device *dev;
d88b25be RV	31	struct mutex irq_lock;
d88b25be RV	32	/* Caches of interrupt control registers for bus_lock */
	33	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	34	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	35	};
	36
0e4011eb	37	static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset)
d88b25be	38	{
b0d38473	39	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	40	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	41	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
cee1b40d	42	u8 mask = BIT(offset % 8);
d88b25be RV	43	int ret;
d88b25be RV	44
20406ebf	45	ret = tc3589x_reg_read(tc3589x, reg);
d88b25be RV	46	if (ret < 0)
	47	return ret;
	48
27ca2267	49	return !!(ret & mask);
d88b25be RV	50	}
d88b25be RV	51
0e4011eb	52	static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
d88b25be	53	{
b0d38473	54	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	55	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	56	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
0e4011eb	57	unsigned int pos = offset % 8;
cee1b40d	58	u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
d88b25be	59
20406ebf	60	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
d88b25be RV	61	}
d88b25be RV	62
20406ebf	63	static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
0e4011eb	64	unsigned int offset, int val)
d88b25be	65	{
b0d38473	66	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	67	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	68	u8 reg = TC3589x_GPIODIR0 + offset / 8;
0e4011eb	69	unsigned int pos = offset % 8;
d88b25be	70
20406ebf	71	tc3589x_gpio_set(chip, offset, val);
d88b25be	72
cee1b40d	73	return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
d88b25be RV	74	}
d88b25be RV	75
20406ebf	76	static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
0e4011eb	77	unsigned int offset)
d88b25be	78	{
b0d38473	79	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	80	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	81	u8 reg = TC3589x_GPIODIR0 + offset / 8;
0e4011eb	82	unsigned int pos = offset % 8;
d88b25be	83
cee1b40d	84	return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
d88b25be RV	85	}
d88b25be RV	86
14063d71	87	static int tc3589x_gpio_get_direction(struct gpio_chip *chip,
0e4011eb	88	unsigned int offset)
14063d71 LW	89	{
	90	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	91	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	92	u8 reg = TC3589x_GPIODIR0 + offset / 8;
0e4011eb	93	unsigned int pos = offset % 8;
14063d71 LW	94	int ret;
	95
	96	ret = tc3589x_reg_read(tc3589x, reg);
	97	if (ret < 0)
	98	return ret;
	99
220a04f0	100	return !(ret & BIT(pos));
14063d71 LW	101	}
14063d71 LW	102
2956b5d9 MW	103	static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
2956b5d9 MW	104	unsigned long config)
8b866b06 LW	105	{
	106	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	107	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	108	/*
	109	* These registers are alterated at each second address
	110	* ODM bit 0 = drive to GND or Hi-Z (open drain)
	111	* ODM bit 1 = drive to VDD or Hi-Z (open source)
	112	*/
	113	u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
	114	u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
0e4011eb	115	unsigned int pos = offset % 8;
8b866b06 LW	116	int ret;
8b866b06 LW	117
2956b5d9 MW	118	switch (pinconf_to_config_param(config)) {
2956b5d9 MW	119	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
8b866b06 LW	120	/* Set open drain mode */
	121	ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
	122	if (ret)
	123	return ret;
	124	/* Enable open drain/source mode */
	125	return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
2956b5d9	126	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
8b866b06 LW	127	/* Set open source mode */
	128	ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
	129	if (ret)
	130	return ret;
	131	/* Enable open drain/source mode */
	132	return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
2956b5d9	133	case PIN_CONFIG_DRIVE_PUSH_PULL:
8b866b06 LW	134	/* Disable open drain/source mode */
	135	return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
	136	default:
	137	break;
	138	}
	139	return -ENOTSUPP;
	140	}
	141
e35b5ab0	142	static const struct gpio_chip template_chip = {
20406ebf	143	.label = "tc3589x",
d88b25be	144	.owner = THIS_MODULE,
20406ebf	145	.get = tc3589x_gpio_get,
20406ebf	146	.set = tc3589x_gpio_set,
14063d71 LW	147	.direction_output = tc3589x_gpio_direction_output,
	148	.direction_input = tc3589x_gpio_direction_input,
	149	.get_direction = tc3589x_gpio_get_direction,
2956b5d9	150	.set_config = tc3589x_gpio_set_config,
9fb1f39e	151	.can_sleep = true,
d88b25be RV	152	};
d88b25be RV	153
33fcc1b8	154	static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
d88b25be	155	{
cf42f1cf	156	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	157	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
efe4c949	158	int offset = d->hwirq;
d88b25be	159	int regoffset = offset / 8;
cee1b40d	160	int mask = BIT(offset % 8);
d88b25be RV	161
d88b25be RV	162	if (type == IRQ_TYPE_EDGE_BOTH) {
20406ebf	163	tc3589x_gpio->regs[REG_IBE][regoffset] \|= mask;
d88b25be RV	164	return 0;
	165	}
	166
20406ebf	167	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
d88b25be RV	168
d88b25be RV	169	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	170	tc3589x_gpio->regs[REG_IS][regoffset] \|= mask;
d88b25be	171	else
20406ebf	172	tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
d88b25be RV	173
d88b25be RV	174	if (type == IRQ_TYPE_EDGE_RISING \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	175	tc3589x_gpio->regs[REG_IEV][regoffset] \|= mask;
d88b25be	176	else
20406ebf	177	tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
d88b25be RV	178
	179	return 0;
	180	}
	181
33fcc1b8	182	static void tc3589x_gpio_irq_lock(struct irq_data *d)
d88b25be	183	{
cf42f1cf	184	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	185	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
d88b25be	186
20406ebf	187	mutex_lock(&tc3589x_gpio->irq_lock);
d88b25be RV	188	}
d88b25be RV	189
33fcc1b8	190	static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
d88b25be	191	{
cf42f1cf	192	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	193	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
20406ebf	194	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be	195	static const u8 regmap[] = {
20406ebf SI	196	[REG_IBE] = TC3589x_GPIOIBE0,
	197	[REG_IEV] = TC3589x_GPIOIEV0,
	198	[REG_IS] = TC3589x_GPIOIS0,
	199	[REG_IE] = TC3589x_GPIOIE0,
d88b25be RV	200	};
	201	int i, j;
	202
	203	for (i = 0; i < CACHE_NR_REGS; i++) {
	204	for (j = 0; j < CACHE_NR_BANKS; j++) {
20406ebf SI	205	u8 old = tc3589x_gpio->oldregs[i][j];
20406ebf SI	206	u8 new = tc3589x_gpio->regs[i][j];
d88b25be RV	207
	208	if (new == old)
	209	continue;
	210
20406ebf SI	211	tc3589x_gpio->oldregs[i][j] = new;
20406ebf SI	212	tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
d88b25be RV	213	}
	214	}
	215
20406ebf	216	mutex_unlock(&tc3589x_gpio->irq_lock);
d88b25be RV	217	}
d88b25be RV	218
33fcc1b8	219	static void tc3589x_gpio_irq_mask(struct irq_data *d)
d88b25be	220	{
cf42f1cf	221	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	222	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
efe4c949	223	int offset = d->hwirq;
d88b25be	224	int regoffset = offset / 8;
cee1b40d	225	int mask = BIT(offset % 8);
d88b25be	226
20406ebf	227	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
d88b25be RV	228	}
d88b25be RV	229
33fcc1b8	230	static void tc3589x_gpio_irq_unmask(struct irq_data *d)
d88b25be	231	{
cf42f1cf	232	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	233	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
efe4c949	234	int offset = d->hwirq;
d88b25be	235	int regoffset = offset / 8;
cee1b40d	236	int mask = BIT(offset % 8);
d88b25be	237
20406ebf	238	tc3589x_gpio->regs[REG_IE][regoffset] \|= mask;
d88b25be RV	239	}
d88b25be RV	240
20406ebf SI	241	static struct irq_chip tc3589x_gpio_irq_chip = {
20406ebf SI	242	.name = "tc3589x-gpio",
33fcc1b8 LB	243	.irq_bus_lock = tc3589x_gpio_irq_lock,
	244	.irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
	245	.irq_mask = tc3589x_gpio_irq_mask,
	246	.irq_unmask = tc3589x_gpio_irq_unmask,
	247	.irq_set_type = tc3589x_gpio_irq_set_type,
d88b25be RV	248	};
d88b25be RV	249
20406ebf	250	static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
d88b25be	251	{
20406ebf SI	252	struct tc3589x_gpio *tc3589x_gpio = dev;
20406ebf SI	253	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be RV	254	u8 status[CACHE_NR_BANKS];
	255	int ret;
	256	int i;
	257
20406ebf	258	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
d88b25be RV	259	ARRAY_SIZE(status), status);
	260	if (ret < 0)
	261	return IRQ_NONE;
	262
	263	for (i = 0; i < ARRAY_SIZE(status); i++) {
	264	unsigned int stat = status[i];
	265	if (!stat)
	266	continue;
	267
	268	while (stat) {
	269	int bit = __ffs(stat);
	270	int line = i * 8 + bit;
cf42f1cf LW	271	int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
cf42f1cf LW	272	line);
d88b25be	273
e300376d	274	handle_nested_irq(irq);
d88b25be RV	275	stat &= ~(1 << bit);
	276	}
	277
20406ebf	278	tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
d88b25be RV	279	}
	280
	281	return IRQ_HANDLED;
	282	}
	283
3836309d	284	static int tc3589x_gpio_probe(struct platform_device *pdev)
d88b25be	285	{
20406ebf	286	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
3113e679	287	struct device_node *np = pdev->dev.of_node;
20406ebf	288	struct tc3589x_gpio *tc3589x_gpio;
d88b25be RV	289	int ret;
	290	int irq;
	291
53e41f55 LW	292	if (!np) {
53e41f55 LW	293	dev_err(&pdev->dev, "No Device Tree node found\n");
3113e679 LJ	294	return -EINVAL;
3113e679 LJ	295	}
d88b25be RV	296
	297	irq = platform_get_irq(pdev, 0);
	298	if (irq < 0)
	299	return irq;
	300
033f2752 LW	301	tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
033f2752 LW	302	GFP_KERNEL);
20406ebf	303	if (!tc3589x_gpio)
d88b25be RV	304	return -ENOMEM;
d88b25be RV	305
20406ebf	306	mutex_init(&tc3589x_gpio->irq_lock);
d88b25be	307
20406ebf SI	308	tc3589x_gpio->dev = &pdev->dev;
20406ebf SI	309	tc3589x_gpio->tc3589x = tc3589x;
d88b25be	310
20406ebf SI	311	tc3589x_gpio->chip = template_chip;
20406ebf SI	312	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
58383c78	313	tc3589x_gpio->chip.parent = &pdev->dev;
90f2d0f7	314	tc3589x_gpio->chip.base = -1;
e90c636b	315	tc3589x_gpio->chip.of_node = np;
d88b25be RV	316
d88b25be RV	317	/* Bring the GPIO module out of reset */
20406ebf SI	318	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
20406ebf SI	319	TC3589x_RSTCTRL_GPIRST, 0);
d88b25be	320	if (ret < 0)
033f2752	321	return ret;
d88b25be	322
033f2752 LW	323	ret = devm_request_threaded_irq(&pdev->dev,
	324	irq, NULL, tc3589x_gpio_irq,
	325	IRQF_ONESHOT, "tc3589x-gpio",
	326	tc3589x_gpio);
d88b25be RV	327	if (ret) {
d88b25be RV	328	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
033f2752	329	return ret;
d88b25be RV	330	}
d88b25be RV	331
f3378b6a LD	332	ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
f3378b6a LD	333	tc3589x_gpio);
d88b25be RV	334	if (ret) {
d88b25be RV	335	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
033f2752	336	return ret;
d88b25be RV	337	}
d88b25be RV	338
d245b3f9 LW	339	ret = gpiochip_irqchip_add_nested(&tc3589x_gpio->chip,
	340	&tc3589x_gpio_irq_chip,
	341	0,
	342	handle_simple_irq,
	343	IRQ_TYPE_NONE);
cf42f1cf LW	344	if (ret) {
	345	dev_err(&pdev->dev,
	346	"could not connect irqchip to gpiochip\n");
	347	return ret;
	348	}
	349
d245b3f9 LW	350	gpiochip_set_nested_irqchip(&tc3589x_gpio->chip,
	351	&tc3589x_gpio_irq_chip,
	352	irq);
3f97d5fc	353
20406ebf	354	platform_set_drvdata(pdev, tc3589x_gpio);
d88b25be RV	355
d88b25be RV	356	return 0;
d88b25be RV	357	}
d88b25be RV	358
20406ebf SI	359	static struct platform_driver tc3589x_gpio_driver = {
20406ebf SI	360	.driver.name = "tc3589x-gpio",
20406ebf	361	.probe = tc3589x_gpio_probe,
d88b25be RV	362	};
d88b25be RV	363
20406ebf	364	static int __init tc3589x_gpio_init(void)
d88b25be	365	{
20406ebf	366	return platform_driver_register(&tc3589x_gpio_driver);
d88b25be	367	}
20406ebf	368	subsys_initcall(tc3589x_gpio_init);