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9c92ab61 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
3c92db9a EG |
2 | /* |
3 | * arch/arm/mach-tegra/gpio.c | |
4 | * | |
5 | * Copyright (c) 2010 Google, Inc | |
11da9054 | 6 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. |
3c92db9a EG |
7 | * |
8 | * Author: | |
9 | * Erik Gilling <konkers@google.com> | |
3c92db9a EG |
10 | */ |
11 | ||
641d0342 | 12 | #include <linux/err.h> |
3c92db9a EG |
13 | #include <linux/init.h> |
14 | #include <linux/irq.h> | |
2e47b8b3 | 15 | #include <linux/interrupt.h> |
3c92db9a | 16 | #include <linux/io.h> |
21041dab | 17 | #include <linux/gpio/driver.h> |
5c1e2c9d | 18 | #include <linux/of_device.h> |
88d8951e SW |
19 | #include <linux/platform_device.h> |
20 | #include <linux/module.h> | |
6f74dc9b | 21 | #include <linux/irqdomain.h> |
de88cbb7 | 22 | #include <linux/irqchip/chained_irq.h> |
3e215d0a | 23 | #include <linux/pinctrl/consumer.h> |
8939ddc7 | 24 | #include <linux/pm.h> |
3c92db9a | 25 | |
3c92db9a EG |
26 | #define GPIO_BANK(x) ((x) >> 5) |
27 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | |
28 | #define GPIO_BIT(x) ((x) & 0x7) | |
29 | ||
b546be0d | 30 | #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ |
5c1e2c9d | 31 | GPIO_PORT(x) * 4) |
3c92db9a | 32 | |
b546be0d LD |
33 | #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) |
34 | #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) | |
35 | #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) | |
36 | #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) | |
37 | #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) | |
38 | #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) | |
39 | #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) | |
40 | #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) | |
3737de42 LD |
41 | #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) |
42 | ||
b546be0d LD |
43 | |
44 | #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) | |
45 | #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) | |
46 | #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) | |
3737de42 | 47 | #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) |
b546be0d LD |
48 | #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) |
49 | #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) | |
50 | #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) | |
3c92db9a EG |
51 | |
52 | #define GPIO_INT_LVL_MASK 0x010101 | |
53 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 | |
54 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 | |
55 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 | |
56 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 | |
57 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 | |
58 | ||
b546be0d LD |
59 | struct tegra_gpio_info; |
60 | ||
3c92db9a | 61 | struct tegra_gpio_bank { |
539b7a39 TR |
62 | unsigned int bank; |
63 | unsigned int irq; | |
3c92db9a | 64 | spinlock_t lvl_lock[4]; |
3737de42 | 65 | spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */ |
8939ddc7 | 66 | #ifdef CONFIG_PM_SLEEP |
2e47b8b3 CC |
67 | u32 cnf[4]; |
68 | u32 out[4]; | |
69 | u32 oe[4]; | |
70 | u32 int_enb[4]; | |
71 | u32 int_lvl[4]; | |
203f31cb | 72 | u32 wake_enb[4]; |
3737de42 | 73 | u32 dbc_enb[4]; |
2e47b8b3 | 74 | #endif |
3737de42 | 75 | u32 dbc_cnt[4]; |
b546be0d | 76 | struct tegra_gpio_info *tgi; |
3c92db9a EG |
77 | }; |
78 | ||
171b92c8 | 79 | struct tegra_gpio_soc_config { |
3737de42 | 80 | bool debounce_supported; |
171b92c8 LD |
81 | u32 bank_stride; |
82 | u32 upper_offset; | |
83 | }; | |
84 | ||
b546be0d LD |
85 | struct tegra_gpio_info { |
86 | struct device *dev; | |
87 | void __iomem *regs; | |
88 | struct irq_domain *irq_domain; | |
89 | struct tegra_gpio_bank *bank_info; | |
90 | const struct tegra_gpio_soc_config *soc; | |
91 | struct gpio_chip gc; | |
92 | struct irq_chip ic; | |
b546be0d LD |
93 | u32 bank_count; |
94 | }; | |
88d8951e | 95 | |
b546be0d LD |
96 | static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, |
97 | u32 val, u32 reg) | |
88d8951e | 98 | { |
b546be0d | 99 | __raw_writel(val, tgi->regs + reg); |
88d8951e SW |
100 | } |
101 | ||
b546be0d | 102 | static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) |
88d8951e | 103 | { |
b546be0d | 104 | return __raw_readl(tgi->regs + reg); |
88d8951e | 105 | } |
3c92db9a | 106 | |
539b7a39 TR |
107 | static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, |
108 | unsigned int bit) | |
3c92db9a EG |
109 | { |
110 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); | |
111 | } | |
112 | ||
b546be0d | 113 | static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, |
539b7a39 | 114 | unsigned int gpio, u32 value) |
3c92db9a EG |
115 | { |
116 | u32 val; | |
117 | ||
118 | val = 0x100 << GPIO_BIT(gpio); | |
119 | if (value) | |
120 | val |= 1 << GPIO_BIT(gpio); | |
b546be0d | 121 | tegra_gpio_writel(tgi, val, reg); |
3c92db9a EG |
122 | } |
123 | ||
539b7a39 | 124 | static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) |
3c92db9a | 125 | { |
b546be0d | 126 | tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); |
3c92db9a EG |
127 | } |
128 | ||
539b7a39 | 129 | static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) |
3c92db9a | 130 | { |
b546be0d | 131 | tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); |
3c92db9a EG |
132 | } |
133 | ||
4bc17860 | 134 | static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) |
3e215d0a | 135 | { |
11da9054 | 136 | return pinctrl_gpio_request(chip->base + offset); |
3e215d0a SW |
137 | } |
138 | ||
4bc17860 | 139 | static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) |
3e215d0a | 140 | { |
b546be0d LD |
141 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
142 | ||
11da9054 | 143 | pinctrl_gpio_free(chip->base + offset); |
b546be0d | 144 | tegra_gpio_disable(tgi, offset); |
3e215d0a SW |
145 | } |
146 | ||
4bc17860 TR |
147 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, |
148 | int value) | |
3c92db9a | 149 | { |
b546be0d LD |
150 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
151 | ||
152 | tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); | |
3c92db9a EG |
153 | } |
154 | ||
4bc17860 | 155 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) |
3c92db9a | 156 | { |
b546be0d | 157 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
539b7a39 | 158 | unsigned int bval = BIT(GPIO_BIT(offset)); |
b546be0d | 159 | |
195812e4 | 160 | /* If gpio is in output mode then read from the out value */ |
b546be0d LD |
161 | if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) |
162 | return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); | |
195812e4 | 163 | |
b546be0d | 164 | return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); |
3c92db9a EG |
165 | } |
166 | ||
4bc17860 TR |
167 | static int tegra_gpio_direction_input(struct gpio_chip *chip, |
168 | unsigned int offset) | |
3c92db9a | 169 | { |
b546be0d | 170 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
11da9054 | 171 | int ret; |
b546be0d LD |
172 | |
173 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); | |
174 | tegra_gpio_enable(tgi, offset); | |
11da9054 LW |
175 | |
176 | ret = pinctrl_gpio_direction_input(chip->base + offset); | |
177 | if (ret < 0) | |
178 | dev_err(tgi->dev, | |
179 | "Failed to set pinctrl input direction of GPIO %d: %d", | |
180 | chip->base + offset, ret); | |
181 | ||
182 | return ret; | |
3c92db9a EG |
183 | } |
184 | ||
4bc17860 TR |
185 | static int tegra_gpio_direction_output(struct gpio_chip *chip, |
186 | unsigned int offset, | |
187 | int value) | |
3c92db9a | 188 | { |
b546be0d | 189 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
11da9054 | 190 | int ret; |
b546be0d | 191 | |
3c92db9a | 192 | tegra_gpio_set(chip, offset, value); |
b546be0d LD |
193 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); |
194 | tegra_gpio_enable(tgi, offset); | |
11da9054 LW |
195 | |
196 | ret = pinctrl_gpio_direction_output(chip->base + offset); | |
197 | if (ret < 0) | |
198 | dev_err(tgi->dev, | |
199 | "Failed to set pinctrl output direction of GPIO %d: %d", | |
200 | chip->base + offset, ret); | |
201 | ||
202 | return ret; | |
3c92db9a EG |
203 | } |
204 | ||
4bc17860 TR |
205 | static int tegra_gpio_get_direction(struct gpio_chip *chip, |
206 | unsigned int offset) | |
f002d07c LD |
207 | { |
208 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); | |
209 | u32 pin_mask = BIT(GPIO_BIT(offset)); | |
210 | u32 cnf, oe; | |
211 | ||
212 | cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); | |
213 | if (!(cnf & pin_mask)) | |
214 | return -EINVAL; | |
215 | ||
216 | oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); | |
217 | ||
21041dab | 218 | return !(oe & pin_mask); |
f002d07c LD |
219 | } |
220 | ||
3737de42 LD |
221 | static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, |
222 | unsigned int debounce) | |
223 | { | |
224 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); | |
225 | struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; | |
226 | unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); | |
227 | unsigned long flags; | |
539b7a39 | 228 | unsigned int port; |
3737de42 LD |
229 | |
230 | if (!debounce_ms) { | |
231 | tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), | |
232 | offset, 0); | |
233 | return 0; | |
234 | } | |
235 | ||
236 | debounce_ms = min(debounce_ms, 255U); | |
237 | port = GPIO_PORT(offset); | |
238 | ||
239 | /* There is only one debounce count register per port and hence | |
240 | * set the maximum of current and requested debounce time. | |
241 | */ | |
242 | spin_lock_irqsave(&bank->dbc_lock[port], flags); | |
243 | if (bank->dbc_cnt[port] < debounce_ms) { | |
244 | tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); | |
245 | bank->dbc_cnt[port] = debounce_ms; | |
246 | } | |
247 | spin_unlock_irqrestore(&bank->dbc_lock[port], flags); | |
248 | ||
249 | tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
2956b5d9 MW |
254 | static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, |
255 | unsigned long config) | |
256 | { | |
257 | u32 debounce; | |
258 | ||
259 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
260 | return -ENOTSUPP; | |
261 | ||
262 | debounce = pinconf_to_config_argument(config); | |
263 | return tegra_gpio_set_debounce(chip, offset, debounce); | |
264 | } | |
265 | ||
4bc17860 | 266 | static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) |
438a99c0 | 267 | { |
b546be0d | 268 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
3c92db9a | 269 | |
b546be0d LD |
270 | return irq_find_mapping(tgi->irq_domain, offset); |
271 | } | |
3c92db9a | 272 | |
37337a8d | 273 | static void tegra_gpio_irq_ack(struct irq_data *d) |
3c92db9a | 274 | { |
b546be0d LD |
275 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
276 | struct tegra_gpio_info *tgi = bank->tgi; | |
539b7a39 | 277 | unsigned int gpio = d->hwirq; |
3c92db9a | 278 | |
b546be0d | 279 | tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); |
3c92db9a EG |
280 | } |
281 | ||
37337a8d | 282 | static void tegra_gpio_irq_mask(struct irq_data *d) |
3c92db9a | 283 | { |
b546be0d LD |
284 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
285 | struct tegra_gpio_info *tgi = bank->tgi; | |
539b7a39 | 286 | unsigned int gpio = d->hwirq; |
3c92db9a | 287 | |
b546be0d | 288 | tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); |
3c92db9a EG |
289 | } |
290 | ||
37337a8d | 291 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
3c92db9a | 292 | { |
b546be0d LD |
293 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
294 | struct tegra_gpio_info *tgi = bank->tgi; | |
539b7a39 | 295 | unsigned int gpio = d->hwirq; |
3c92db9a | 296 | |
b546be0d | 297 | tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); |
3c92db9a EG |
298 | } |
299 | ||
37337a8d | 300 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
3c92db9a | 301 | { |
539b7a39 | 302 | unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; |
37337a8d | 303 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
b546be0d | 304 | struct tegra_gpio_info *tgi = bank->tgi; |
3c92db9a | 305 | unsigned long flags; |
539b7a39 | 306 | u32 val; |
df231f28 | 307 | int ret; |
3c92db9a EG |
308 | |
309 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
310 | case IRQ_TYPE_EDGE_RISING: | |
311 | lvl_type = GPIO_INT_LVL_EDGE_RISING; | |
312 | break; | |
313 | ||
314 | case IRQ_TYPE_EDGE_FALLING: | |
315 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; | |
316 | break; | |
317 | ||
318 | case IRQ_TYPE_EDGE_BOTH: | |
319 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; | |
320 | break; | |
321 | ||
322 | case IRQ_TYPE_LEVEL_HIGH: | |
323 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; | |
324 | break; | |
325 | ||
326 | case IRQ_TYPE_LEVEL_LOW: | |
327 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; | |
328 | break; | |
329 | ||
330 | default: | |
331 | return -EINVAL; | |
332 | } | |
333 | ||
334 | spin_lock_irqsave(&bank->lvl_lock[port], flags); | |
335 | ||
b546be0d | 336 | val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); |
3c92db9a EG |
337 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
338 | val |= lvl_type << GPIO_BIT(gpio); | |
b546be0d | 339 | tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); |
3c92db9a EG |
340 | |
341 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | |
342 | ||
b546be0d LD |
343 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); |
344 | tegra_gpio_enable(tgi, gpio); | |
d941136f | 345 | |
f78709a5 DO |
346 | ret = gpiochip_lock_as_irq(&tgi->gc, gpio); |
347 | if (ret) { | |
348 | dev_err(tgi->dev, | |
349 | "unable to lock Tegra GPIO %u as IRQ\n", gpio); | |
350 | tegra_gpio_disable(tgi, gpio); | |
351 | return ret; | |
352 | } | |
353 | ||
3c92db9a | 354 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
f170d71e | 355 | irq_set_handler_locked(d, handle_level_irq); |
3c92db9a | 356 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
f170d71e | 357 | irq_set_handler_locked(d, handle_edge_irq); |
3c92db9a EG |
358 | |
359 | return 0; | |
360 | } | |
361 | ||
df231f28 SW |
362 | static void tegra_gpio_irq_shutdown(struct irq_data *d) |
363 | { | |
b546be0d LD |
364 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
365 | struct tegra_gpio_info *tgi = bank->tgi; | |
539b7a39 | 366 | unsigned int gpio = d->hwirq; |
df231f28 | 367 | |
b546be0d | 368 | gpiochip_unlock_as_irq(&tgi->gc, gpio); |
df231f28 SW |
369 | } |
370 | ||
bd0b9ac4 | 371 | static void tegra_gpio_irq_handler(struct irq_desc *desc) |
3c92db9a | 372 | { |
539b7a39 | 373 | unsigned int port, pin, gpio; |
9e9509e3 | 374 | bool unmasked = false; |
b546be0d LD |
375 | u32 lvl; |
376 | unsigned long sta; | |
98022940 | 377 | struct irq_chip *chip = irq_desc_get_chip(desc); |
476f8b4c | 378 | struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); |
b546be0d | 379 | struct tegra_gpio_info *tgi = bank->tgi; |
3c92db9a | 380 | |
98022940 | 381 | chained_irq_enter(chip, desc); |
3c92db9a | 382 | |
3c92db9a | 383 | for (port = 0; port < 4; port++) { |
b546be0d LD |
384 | gpio = tegra_gpio_compose(bank->bank, port, 0); |
385 | sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & | |
386 | tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); | |
387 | lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); | |
3c92db9a EG |
388 | |
389 | for_each_set_bit(pin, &sta, 8) { | |
b546be0d LD |
390 | tegra_gpio_writel(tgi, 1 << pin, |
391 | GPIO_INT_CLR(tgi, gpio)); | |
3c92db9a EG |
392 | |
393 | /* if gpio is edge triggered, clear condition | |
20a8a968 | 394 | * before executing the handler so that we don't |
3c92db9a EG |
395 | * miss edges |
396 | */ | |
9e9509e3 MM |
397 | if (!unmasked && lvl & (0x100 << pin)) { |
398 | unmasked = true; | |
98022940 | 399 | chained_irq_exit(chip, desc); |
3c92db9a EG |
400 | } |
401 | ||
c0debb3d GS |
402 | generic_handle_irq(irq_find_mapping(tgi->irq_domain, |
403 | gpio + pin)); | |
3c92db9a EG |
404 | } |
405 | } | |
406 | ||
407 | if (!unmasked) | |
98022940 | 408 | chained_irq_exit(chip, desc); |
3c92db9a EG |
409 | |
410 | } | |
411 | ||
8939ddc7 LD |
412 | #ifdef CONFIG_PM_SLEEP |
413 | static int tegra_gpio_resume(struct device *dev) | |
2e47b8b3 | 414 | { |
7ddb7dce | 415 | struct tegra_gpio_info *tgi = dev_get_drvdata(dev); |
2e47b8b3 | 416 | unsigned long flags; |
539b7a39 | 417 | unsigned int b, p; |
2e47b8b3 CC |
418 | |
419 | local_irq_save(flags); | |
420 | ||
b546be0d LD |
421 | for (b = 0; b < tgi->bank_count; b++) { |
422 | struct tegra_gpio_bank *bank = &tgi->bank_info[b]; | |
2e47b8b3 CC |
423 | |
424 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
4bc17860 TR |
425 | unsigned int gpio = (b << 5) | (p << 3); |
426 | ||
b546be0d LD |
427 | tegra_gpio_writel(tgi, bank->cnf[p], |
428 | GPIO_CNF(tgi, gpio)); | |
3737de42 LD |
429 | |
430 | if (tgi->soc->debounce_supported) { | |
431 | tegra_gpio_writel(tgi, bank->dbc_cnt[p], | |
432 | GPIO_DBC_CNT(tgi, gpio)); | |
433 | tegra_gpio_writel(tgi, bank->dbc_enb[p], | |
434 | GPIO_MSK_DBC_EN(tgi, gpio)); | |
435 | } | |
436 | ||
b546be0d LD |
437 | tegra_gpio_writel(tgi, bank->out[p], |
438 | GPIO_OUT(tgi, gpio)); | |
439 | tegra_gpio_writel(tgi, bank->oe[p], | |
440 | GPIO_OE(tgi, gpio)); | |
441 | tegra_gpio_writel(tgi, bank->int_lvl[p], | |
442 | GPIO_INT_LVL(tgi, gpio)); | |
443 | tegra_gpio_writel(tgi, bank->int_enb[p], | |
444 | GPIO_INT_ENB(tgi, gpio)); | |
2e47b8b3 CC |
445 | } |
446 | } | |
447 | ||
448 | local_irq_restore(flags); | |
8939ddc7 | 449 | return 0; |
2e47b8b3 CC |
450 | } |
451 | ||
8939ddc7 | 452 | static int tegra_gpio_suspend(struct device *dev) |
2e47b8b3 | 453 | { |
7ddb7dce | 454 | struct tegra_gpio_info *tgi = dev_get_drvdata(dev); |
2e47b8b3 | 455 | unsigned long flags; |
539b7a39 | 456 | unsigned int b, p; |
2e47b8b3 | 457 | |
2e47b8b3 | 458 | local_irq_save(flags); |
b546be0d LD |
459 | for (b = 0; b < tgi->bank_count; b++) { |
460 | struct tegra_gpio_bank *bank = &tgi->bank_info[b]; | |
2e47b8b3 CC |
461 | |
462 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
4bc17860 TR |
463 | unsigned int gpio = (b << 5) | (p << 3); |
464 | ||
b546be0d LD |
465 | bank->cnf[p] = tegra_gpio_readl(tgi, |
466 | GPIO_CNF(tgi, gpio)); | |
467 | bank->out[p] = tegra_gpio_readl(tgi, | |
468 | GPIO_OUT(tgi, gpio)); | |
469 | bank->oe[p] = tegra_gpio_readl(tgi, | |
470 | GPIO_OE(tgi, gpio)); | |
3737de42 LD |
471 | if (tgi->soc->debounce_supported) { |
472 | bank->dbc_enb[p] = tegra_gpio_readl(tgi, | |
473 | GPIO_MSK_DBC_EN(tgi, gpio)); | |
474 | bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | | |
475 | bank->dbc_enb[p]; | |
476 | } | |
477 | ||
b546be0d LD |
478 | bank->int_enb[p] = tegra_gpio_readl(tgi, |
479 | GPIO_INT_ENB(tgi, gpio)); | |
480 | bank->int_lvl[p] = tegra_gpio_readl(tgi, | |
481 | GPIO_INT_LVL(tgi, gpio)); | |
203f31cb JL |
482 | |
483 | /* Enable gpio irq for wake up source */ | |
b546be0d LD |
484 | tegra_gpio_writel(tgi, bank->wake_enb[p], |
485 | GPIO_INT_ENB(tgi, gpio)); | |
2e47b8b3 CC |
486 | } |
487 | } | |
488 | local_irq_restore(flags); | |
8939ddc7 | 489 | return 0; |
2e47b8b3 CC |
490 | } |
491 | ||
203f31cb | 492 | static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) |
2e47b8b3 | 493 | { |
37337a8d | 494 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
539b7a39 | 495 | unsigned int gpio = d->hwirq; |
203f31cb JL |
496 | u32 port, bit, mask; |
497 | ||
498 | port = GPIO_PORT(gpio); | |
499 | bit = GPIO_BIT(gpio); | |
500 | mask = BIT(bit); | |
501 | ||
502 | if (enable) | |
503 | bank->wake_enb[port] |= mask; | |
504 | else | |
505 | bank->wake_enb[port] &= ~mask; | |
506 | ||
6845664a | 507 | return irq_set_irq_wake(bank->irq, enable); |
2e47b8b3 CC |
508 | } |
509 | #endif | |
3c92db9a | 510 | |
b59d5fb7 SP |
511 | #ifdef CONFIG_DEBUG_FS |
512 | ||
513 | #include <linux/debugfs.h> | |
514 | #include <linux/seq_file.h> | |
515 | ||
2773eb2f | 516 | static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) |
b59d5fb7 | 517 | { |
b546be0d | 518 | struct tegra_gpio_info *tgi = s->private; |
539b7a39 | 519 | unsigned int i, j; |
b59d5fb7 | 520 | |
b546be0d | 521 | for (i = 0; i < tgi->bank_count; i++) { |
b59d5fb7 | 522 | for (j = 0; j < 4; j++) { |
539b7a39 | 523 | unsigned int gpio = tegra_gpio_compose(i, j, 0); |
4bc17860 | 524 | |
b59d5fb7 | 525 | seq_printf(s, |
539b7a39 | 526 | "%u:%u %02x %02x %02x %02x %02x %02x %06x\n", |
b59d5fb7 | 527 | i, j, |
b546be0d LD |
528 | tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), |
529 | tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), | |
530 | tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), | |
531 | tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), | |
532 | tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), | |
533 | tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), | |
534 | tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); | |
b59d5fb7 SP |
535 | } |
536 | } | |
537 | return 0; | |
538 | } | |
539 | ||
2773eb2f | 540 | DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio); |
b59d5fb7 | 541 | |
b546be0d | 542 | static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
b59d5fb7 | 543 | { |
9b3b6238 LW |
544 | debugfs_create_file("tegra_gpio", 0444, NULL, tgi, |
545 | &tegra_dbg_gpio_fops); | |
b59d5fb7 SP |
546 | } |
547 | ||
548 | #else | |
549 | ||
b546be0d | 550 | static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
b59d5fb7 SP |
551 | { |
552 | } | |
553 | ||
554 | #endif | |
555 | ||
8939ddc7 LD |
556 | static const struct dev_pm_ops tegra_gpio_pm_ops = { |
557 | SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) | |
558 | }; | |
559 | ||
3836309d | 560 | static int tegra_gpio_probe(struct platform_device *pdev) |
3c92db9a | 561 | { |
b546be0d | 562 | struct tegra_gpio_info *tgi; |
3c92db9a | 563 | struct tegra_gpio_bank *bank; |
539b7a39 | 564 | unsigned int gpio, i, j; |
f57f98a6 | 565 | int ret; |
3c92db9a | 566 | |
b546be0d LD |
567 | tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); |
568 | if (!tgi) | |
569 | return -ENODEV; | |
570 | ||
20133bd5 | 571 | tgi->soc = of_device_get_match_data(&pdev->dev); |
b546be0d | 572 | tgi->dev = &pdev->dev; |
5c1e2c9d | 573 | |
56420903 TR |
574 | ret = platform_irq_count(pdev); |
575 | if (ret < 0) | |
576 | return ret; | |
577 | ||
578 | tgi->bank_count = ret; | |
579 | ||
b546be0d | 580 | if (!tgi->bank_count) { |
3391811c SW |
581 | dev_err(&pdev->dev, "Missing IRQ resource\n"); |
582 | return -ENODEV; | |
583 | } | |
584 | ||
b546be0d LD |
585 | tgi->gc.label = "tegra-gpio"; |
586 | tgi->gc.request = tegra_gpio_request; | |
587 | tgi->gc.free = tegra_gpio_free; | |
588 | tgi->gc.direction_input = tegra_gpio_direction_input; | |
589 | tgi->gc.get = tegra_gpio_get; | |
590 | tgi->gc.direction_output = tegra_gpio_direction_output; | |
591 | tgi->gc.set = tegra_gpio_set; | |
f002d07c | 592 | tgi->gc.get_direction = tegra_gpio_get_direction; |
b546be0d LD |
593 | tgi->gc.to_irq = tegra_gpio_to_irq; |
594 | tgi->gc.base = 0; | |
595 | tgi->gc.ngpio = tgi->bank_count * 32; | |
596 | tgi->gc.parent = &pdev->dev; | |
597 | tgi->gc.of_node = pdev->dev.of_node; | |
598 | ||
599 | tgi->ic.name = "GPIO"; | |
600 | tgi->ic.irq_ack = tegra_gpio_irq_ack; | |
601 | tgi->ic.irq_mask = tegra_gpio_irq_mask; | |
602 | tgi->ic.irq_unmask = tegra_gpio_irq_unmask; | |
603 | tgi->ic.irq_set_type = tegra_gpio_irq_set_type; | |
604 | tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown; | |
605 | #ifdef CONFIG_PM_SLEEP | |
606 | tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake; | |
607 | #endif | |
608 | ||
609 | platform_set_drvdata(pdev, tgi); | |
3391811c | 610 | |
20133bd5 | 611 | if (tgi->soc->debounce_supported) |
2956b5d9 | 612 | tgi->gc.set_config = tegra_gpio_set_config; |
3737de42 | 613 | |
9b882269 | 614 | tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, |
b546be0d LD |
615 | sizeof(*tgi->bank_info), GFP_KERNEL); |
616 | if (!tgi->bank_info) | |
9b882269 | 617 | return -ENOMEM; |
3391811c | 618 | |
b546be0d LD |
619 | tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node, |
620 | tgi->gc.ngpio, | |
621 | &irq_domain_simple_ops, NULL); | |
622 | if (!tgi->irq_domain) | |
d0235677 | 623 | return -ENODEV; |
6f74dc9b | 624 | |
b546be0d | 625 | for (i = 0; i < tgi->bank_count; i++) { |
9c07409c TR |
626 | ret = platform_get_irq(pdev, i); |
627 | if (ret < 0) { | |
628 | dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret); | |
629 | return ret; | |
88d8951e SW |
630 | } |
631 | ||
b546be0d | 632 | bank = &tgi->bank_info[i]; |
88d8951e | 633 | bank->bank = i; |
9c07409c | 634 | bank->irq = ret; |
b546be0d | 635 | bank->tgi = tgi; |
88d8951e SW |
636 | } |
637 | ||
a0b81f1c | 638 | tgi->regs = devm_platform_ioremap_resource(pdev, 0); |
b546be0d LD |
639 | if (IS_ERR(tgi->regs)) |
640 | return PTR_ERR(tgi->regs); | |
88d8951e | 641 | |
b546be0d | 642 | for (i = 0; i < tgi->bank_count; i++) { |
3c92db9a EG |
643 | for (j = 0; j < 4; j++) { |
644 | int gpio = tegra_gpio_compose(i, j, 0); | |
4bc17860 | 645 | |
b546be0d | 646 | tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); |
3c92db9a EG |
647 | } |
648 | } | |
649 | ||
b546be0d | 650 | ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); |
f57f98a6 | 651 | if (ret < 0) { |
b546be0d | 652 | irq_domain_remove(tgi->irq_domain); |
f57f98a6 SW |
653 | return ret; |
654 | } | |
3c92db9a | 655 | |
b546be0d LD |
656 | for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) { |
657 | int irq = irq_create_mapping(tgi->irq_domain, gpio); | |
47008001 | 658 | /* No validity check; all Tegra GPIOs are valid IRQs */ |
3c92db9a | 659 | |
b546be0d | 660 | bank = &tgi->bank_info[GPIO_BANK(gpio)]; |
3c92db9a | 661 | |
47008001 | 662 | irq_set_chip_data(irq, bank); |
b546be0d | 663 | irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq); |
3c92db9a EG |
664 | } |
665 | ||
b546be0d LD |
666 | for (i = 0; i < tgi->bank_count; i++) { |
667 | bank = &tgi->bank_info[i]; | |
3c92db9a | 668 | |
e88d251d RK |
669 | irq_set_chained_handler_and_data(bank->irq, |
670 | tegra_gpio_irq_handler, bank); | |
3c92db9a | 671 | |
3737de42 | 672 | for (j = 0; j < 4; j++) { |
3c92db9a | 673 | spin_lock_init(&bank->lvl_lock[j]); |
3737de42 LD |
674 | spin_lock_init(&bank->dbc_lock[j]); |
675 | } | |
3c92db9a EG |
676 | } |
677 | ||
b546be0d | 678 | tegra_gpio_debuginit(tgi); |
b59d5fb7 | 679 | |
3c92db9a EG |
680 | return 0; |
681 | } | |
682 | ||
804f5680 | 683 | static const struct tegra_gpio_soc_config tegra20_gpio_config = { |
171b92c8 LD |
684 | .bank_stride = 0x80, |
685 | .upper_offset = 0x800, | |
686 | }; | |
687 | ||
804f5680 | 688 | static const struct tegra_gpio_soc_config tegra30_gpio_config = { |
171b92c8 LD |
689 | .bank_stride = 0x100, |
690 | .upper_offset = 0x80, | |
691 | }; | |
692 | ||
3737de42 LD |
693 | static const struct tegra_gpio_soc_config tegra210_gpio_config = { |
694 | .debounce_supported = true, | |
695 | .bank_stride = 0x100, | |
696 | .upper_offset = 0x80, | |
697 | }; | |
698 | ||
171b92c8 | 699 | static const struct of_device_id tegra_gpio_of_match[] = { |
3737de42 | 700 | { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, |
171b92c8 LD |
701 | { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, |
702 | { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, | |
703 | { }, | |
704 | }; | |
705 | ||
88d8951e SW |
706 | static struct platform_driver tegra_gpio_driver = { |
707 | .driver = { | |
708 | .name = "tegra-gpio", | |
8939ddc7 | 709 | .pm = &tegra_gpio_pm_ops, |
88d8951e SW |
710 | .of_match_table = tegra_gpio_of_match, |
711 | }, | |
712 | .probe = tegra_gpio_probe, | |
713 | }; | |
714 | ||
715 | static int __init tegra_gpio_init(void) | |
716 | { | |
717 | return platform_driver_register(&tegra_gpio_driver); | |
718 | } | |
40b25bce | 719 | subsys_initcall(tegra_gpio_init); |