[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-tegra.c

/*
 * arch/arm/mach-tegra/gpio.c
 *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>

#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of.h>

#include <asm/mach/irq.h>

#include <mach/iomap.h>
#include <mach/suspend.h>

#define GPIO_BANK(x)		((x) >> 5)
#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
#define GPIO_BIT(x)		((x) & 0x7)

#define GPIO_REG(x)		(IO_TO_VIRT(TEGRA_GPIO_BASE) +	\
				 GPIO_BANK(x) * 0x80 +		\
				 GPIO_PORT(x) * 4)

#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)

#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + 0x800)
#define GPIO_MSK_OE(x)		(GPIO_REG(x) + 0x810)
#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + 0X820)
#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + 0x840)
#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + 0x850)
#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + 0x860)

#define GPIO_INT_LVL_MASK		0x010101
#define GPIO_INT_LVL_EDGE_RISING	0x000101
#define GPIO_INT_LVL_EDGE_FALLING	0x000100
#define GPIO_INT_LVL_EDGE_BOTH		0x010100
#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
#define GPIO_INT_LVL_LEVEL_LOW		0x000000

struct tegra_gpio_bank {
	int bank;
	int irq;
	spinlock_t lvl_lock[4];
#ifdef CONFIG_PM
	u32 cnf[4];
	u32 out[4];
	u32 oe[4];
	u32 int_enb[4];
	u32 int_lvl[4];
#endif
};


static struct tegra_gpio_bank tegra_gpio_banks[] = {
	{.bank = 0, .irq = INT_GPIO1},
	{.bank = 1, .irq = INT_GPIO2},
	{.bank = 2, .irq = INT_GPIO3},
	{.bank = 3, .irq = INT_GPIO4},
	{.bank = 4, .irq = INT_GPIO5},
	{.bank = 5, .irq = INT_GPIO6},
	{.bank = 6, .irq = INT_GPIO7},
};

static int tegra_gpio_compose(int bank, int port, int bit)
{
	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}

static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
	u32 val;

	val = 0x100 << GPIO_BIT(gpio);
	if (value)
		val |= 1 << GPIO_BIT(gpio);
	__raw_writel(val, reg);
}

void tegra_gpio_enable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}

void tegra_gpio_disable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
}

static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}

static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	return 0;
}

static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	tegra_gpio_set(chip, offset, value);
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	return 0;
}


static struct gpio_chip tegra_gpio_chip = {
	.label			= "tegra-gpio",
	.direction_input	= tegra_gpio_direction_input,
	.get			= tegra_gpio_get,
	.direction_output	= tegra_gpio_direction_output,
	.set			= tegra_gpio_set,
	.base			= 0,
	.ngpio			= TEGRA_NR_GPIOS,
};

static void tegra_gpio_irq_ack(struct irq_data *d)
{
	int gpio = d->irq - INT_GPIO_BASE;

	__raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
}

static void tegra_gpio_irq_mask(struct irq_data *d)
{
	int gpio = d->irq - INT_GPIO_BASE;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
}

static void tegra_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = d->irq - INT_GPIO_BASE;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
}

static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	int gpio = d->irq - INT_GPIO_BASE;
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int port = GPIO_PORT(gpio);
	int lvl_type;
	int val;
	unsigned long flags;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_INT_LVL_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
		break;

	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&bank->lvl_lock[port], flags);

	val = __raw_readl(GPIO_INT_LVL(gpio));
	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	val |= lvl_type << GPIO_BIT(gpio);
	__raw_writel(val, GPIO_INT_LVL(gpio));

	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return 0;
}

static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct tegra_gpio_bank *bank;
	int port;
	int pin;
	int unmasked = 0;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	bank = irq_get_handler_data(irq);

	for (port = 0; port < 4; port++) {
		int gpio = tegra_gpio_compose(bank->bank, port, 0);
		unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
			__raw_readl(GPIO_INT_ENB(gpio));
		u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));

		for_each_set_bit(pin, &sta, 8) {
			__raw_writel(1 << pin, GPIO_INT_CLR(gpio));

			/* if gpio is edge triggered, clear condition
			 * before executing the hander so that we don't
			 * miss edges
			 */
			if (lvl & (0x100 << pin)) {
				unmasked = 1;
				chained_irq_exit(chip, desc);
			}

			generic_handle_irq(gpio_to_irq(gpio + pin));
		}
	}

	if (!unmasked)
		chained_irq_exit(chip, desc);

}

#ifdef CONFIG_PM
void tegra_gpio_resume(void)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);

	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			__raw_writel(bank->cnf[p], GPIO_CNF(gpio));
			__raw_writel(bank->out[p], GPIO_OUT(gpio));
			__raw_writel(bank->oe[p], GPIO_OE(gpio));
			__raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
			__raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
		}
	}

	local_irq_restore(flags);
}

void tegra_gpio_suspend(void)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);
	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
			bank->out[p] = __raw_readl(GPIO_OUT(gpio));
			bank->oe[p] = __raw_readl(GPIO_OE(gpio));
			bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
			bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
		}
	}
	local_irq_restore(flags);
}

static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	return irq_set_irq_wake(bank->irq, enable);
}
#endif

static struct irq_chip tegra_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= tegra_gpio_irq_ack,
	.irq_mask	= tegra_gpio_irq_mask,
	.irq_unmask	= tegra_gpio_irq_unmask,
	.irq_set_type	= tegra_gpio_irq_set_type,
#ifdef CONFIG_PM
	.irq_set_wake	= tegra_gpio_wake_enable,
#endif
};


/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int __init tegra_gpio_init(void)
{
	struct tegra_gpio_bank *bank;
	int gpio;
	int i;
	int j;

	for (i = 0; i < 7; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			__raw_writel(0x00, GPIO_INT_ENB(gpio));
		}
	}

#ifdef CONFIG_OF_GPIO
	/*
	 * This isn't ideal, but it gets things hooked up until this
	 * driver is converted into a platform_device
	 */
	tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
						"nvidia,tegra20-gpio");
#endif /* CONFIG_OF_GPIO */

	gpiochip_add(&tegra_gpio_chip);

	for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
		int irq = TEGRA_GPIO_TO_IRQ(gpio);
		/* No validity check; all Tegra GPIOs are valid IRQs */

		bank = &tegra_gpio_banks[GPIO_BANK(gpio)];

		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_data(irq, bank);
		irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
		bank = &tegra_gpio_banks[i];

		irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
		irq_set_handler_data(bank->irq, bank);

		for (j = 0; j < 4; j++)
			spin_lock_init(&bank->lvl_lock[j]);
	}

	return 0;
}

postcore_initcall(tegra_gpio_init);

void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
{
	int i;

	for (i = 0; i < num; i++) {
		int gpio = table[i].gpio;

		if (table[i].enable)
			tegra_gpio_enable(gpio);
		else
			tegra_gpio_disable(gpio);
	}
}

#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	int i;
	int j;

	for (i = 0; i < 7; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			seq_printf(s,
				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
				i, j,
				__raw_readl(GPIO_CNF(gpio)),
				__raw_readl(GPIO_OE(gpio)),
				__raw_readl(GPIO_OUT(gpio)),
				__raw_readl(GPIO_IN(gpio)),
				__raw_readl(GPIO_INT_STA(gpio)),
				__raw_readl(GPIO_INT_ENB(gpio)),
				__raw_readl(GPIO_INT_LVL(gpio)));
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, dbg_gpio_show, &inode->i_private);
}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init tegra_gpio_debuginit(void)
{
	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
	return 0;
}
late_initcall(tegra_gpio_debuginit);
#endif
Commit	Line	Data
3c92db9a EG	1	/*
	2	* arch/arm/mach-tegra/gpio.c
	3	*
	4	* Copyright (c) 2010 Google, Inc
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/irq.h>
2e47b8b3	22	#include <linux/interrupt.h>
3c92db9a EG	23
	24	#include <linux/io.h>
	25	#include <linux/gpio.h>
df221227	26	#include <linux/of.h>
3c92db9a	27
98022940 WD	28	#include <asm/mach/irq.h>
98022940 WD	29
3c92db9a	30	#include <mach/iomap.h>
2ea67fd1	31	#include <mach/suspend.h>
3c92db9a EG	32
	33	#define GPIO_BANK(x) ((x) >> 5)
	34	#define GPIO_PORT(x) (((x) >> 3) & 0x3)
	35	#define GPIO_BIT(x) ((x) & 0x7)
	36
	37	#define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \
	38	GPIO_BANK(x) * 0x80 + \
	39	GPIO_PORT(x) * 4)
	40
	41	#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
	42	#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
	43	#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
	44	#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
	45	#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
	46	#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
	47	#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
	48	#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
	49
	50	#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800)
	51	#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810)
	52	#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820)
	53	#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840)
	54	#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850)
	55	#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860)
	56
	57	#define GPIO_INT_LVL_MASK 0x010101
	58	#define GPIO_INT_LVL_EDGE_RISING 0x000101
	59	#define GPIO_INT_LVL_EDGE_FALLING 0x000100
	60	#define GPIO_INT_LVL_EDGE_BOTH 0x010100
	61	#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
	62	#define GPIO_INT_LVL_LEVEL_LOW 0x000000
	63
	64	struct tegra_gpio_bank {
	65	int bank;
	66	int irq;
	67	spinlock_t lvl_lock[4];
2e47b8b3 CC	68	#ifdef CONFIG_PM
	69	u32 cnf[4];
	70	u32 out[4];
	71	u32 oe[4];
	72	u32 int_enb[4];
	73	u32 int_lvl[4];
	74	#endif
3c92db9a EG	75	};
	76
	77
	78	static struct tegra_gpio_bank tegra_gpio_banks[] = {
	79	{.bank = 0, .irq = INT_GPIO1},
	80	{.bank = 1, .irq = INT_GPIO2},
	81	{.bank = 2, .irq = INT_GPIO3},
	82	{.bank = 3, .irq = INT_GPIO4},
	83	{.bank = 4, .irq = INT_GPIO5},
	84	{.bank = 5, .irq = INT_GPIO6},
	85	{.bank = 6, .irq = INT_GPIO7},
	86	};
	87
	88	static int tegra_gpio_compose(int bank, int port, int bit)
	89	{
	90	return (bank << 5) \| ((port & 0x3) << 3) \| (bit & 0x7);
	91	}
	92
	93	static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
	94	{
	95	u32 val;
	96
	97	val = 0x100 << GPIO_BIT(gpio);
	98	if (value)
	99	val \|= 1 << GPIO_BIT(gpio);
	100	__raw_writel(val, reg);
	101	}
	102
	103	void tegra_gpio_enable(int gpio)
	104	{
	105	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
	106	}
	107
	108	void tegra_gpio_disable(int gpio)
	109	{
	110	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
	111	}
	112
	113	static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	114	{
	115	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
	116	}
	117
	118	static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
	119	{
	120	return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
	121	}
	122
	123	static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	124	{
	125	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	126	return 0;
	127	}
	128
	129	static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	130	int value)
	131	{
	132	tegra_gpio_set(chip, offset, value);
	133	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	134	return 0;
	135	}
	136
	137
	138
139	static struct gpio_chip tegra_gpio_chip = {
140	.label = "tegra-gpio",
141	.direction_input = tegra_gpio_direction_input,
142	.get = tegra_gpio_get,
143	.direction_output = tegra_gpio_direction_output,
144	.set = tegra_gpio_set,
145	.base = 0,
2e47b8b3	146	.ngpio = TEGRA_NR_GPIOS,
3c92db9a EG	147	};
3c92db9a EG	148
37337a8d	149	static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a	150	{
37337a8d	151	int gpio = d->irq - INT_GPIO_BASE;
3c92db9a EG	152
	153	__raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
	154	}
	155
37337a8d	156	static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a	157	{
37337a8d	158	int gpio = d->irq - INT_GPIO_BASE;
3c92db9a EG	159
	160	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
	161	}
	162
37337a8d	163	static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a	164	{
37337a8d	165	int gpio = d->irq - INT_GPIO_BASE;
3c92db9a EG	166
	167	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
	168	}
	169
37337a8d	170	static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a	171	{
37337a8d LB	172	int gpio = d->irq - INT_GPIO_BASE;
37337a8d LB	173	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
3c92db9a EG	174	int port = GPIO_PORT(gpio);
	175	int lvl_type;
	176	int val;
	177	unsigned long flags;
	178
	179	switch (type & IRQ_TYPE_SENSE_MASK) {
	180	case IRQ_TYPE_EDGE_RISING:
	181	lvl_type = GPIO_INT_LVL_EDGE_RISING;
	182	break;
	183
	184	case IRQ_TYPE_EDGE_FALLING:
	185	lvl_type = GPIO_INT_LVL_EDGE_FALLING;
	186	break;
	187
	188	case IRQ_TYPE_EDGE_BOTH:
	189	lvl_type = GPIO_INT_LVL_EDGE_BOTH;
	190	break;
	191
	192	case IRQ_TYPE_LEVEL_HIGH:
	193	lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
	194	break;
	195
	196	case IRQ_TYPE_LEVEL_LOW:
	197	lvl_type = GPIO_INT_LVL_LEVEL_LOW;
	198	break;
	199
	200	default:
	201	return -EINVAL;
	202	}
	203
	204	spin_lock_irqsave(&bank->lvl_lock[port], flags);
	205
	206	val = __raw_readl(GPIO_INT_LVL(gpio));
	207	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	208	val \|= lvl_type << GPIO_BIT(gpio);
	209	__raw_writel(val, GPIO_INT_LVL(gpio));
	210
	211	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
	212
	213	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
6845664a	214	__irq_set_handler_locked(d->irq, handle_level_irq);
3c92db9a	215	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
6845664a	216	__irq_set_handler_locked(d->irq, handle_edge_irq);
3c92db9a EG	217
	218	return 0;
	219	}
	220
	221	static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	222	{
	223	struct tegra_gpio_bank *bank;
	224	int port;
	225	int pin;
	226	int unmasked = 0;
98022940	227	struct irq_chip *chip = irq_desc_get_chip(desc);
3c92db9a	228
98022940	229	chained_irq_enter(chip, desc);
3c92db9a	230
6845664a	231	bank = irq_get_handler_data(irq);
3c92db9a EG	232
	233	for (port = 0; port < 4; port++) {
	234	int gpio = tegra_gpio_compose(bank->bank, port, 0);
	235	unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
	236	__raw_readl(GPIO_INT_ENB(gpio));
	237	u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
	238
	239	for_each_set_bit(pin, &sta, 8) {
	240	__raw_writel(1 << pin, GPIO_INT_CLR(gpio));
	241
	242	/* if gpio is edge triggered, clear condition
	243	* before executing the hander so that we don't
	244	* miss edges
	245	*/
	246	if (lvl & (0x100 << pin)) {
	247	unmasked = 1;
98022940	248	chained_irq_exit(chip, desc);
3c92db9a EG	249	}
	250
	251	generic_handle_irq(gpio_to_irq(gpio + pin));
	252	}
	253	}
	254
	255	if (!unmasked)
98022940	256	chained_irq_exit(chip, desc);
3c92db9a EG	257
	258	}
	259
2e47b8b3 CC	260	#ifdef CONFIG_PM
	261	void tegra_gpio_resume(void)
	262	{
	263	unsigned long flags;
c8309ef6 CC	264	int b;
c8309ef6 CC	265	int p;
2e47b8b3 CC	266
	267	local_irq_save(flags);
	268
	269	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
	270	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	271
	272	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	273	unsigned int gpio = (b<<5) \| (p<<3);
	274	__raw_writel(bank->cnf[p], GPIO_CNF(gpio));
	275	__raw_writel(bank->out[p], GPIO_OUT(gpio));
	276	__raw_writel(bank->oe[p], GPIO_OE(gpio));
	277	__raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
	278	__raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
	279	}
	280	}
	281
	282	local_irq_restore(flags);
2e47b8b3 CC	283	}
	284
	285	void tegra_gpio_suspend(void)
	286	{
	287	unsigned long flags;
c8309ef6 CC	288	int b;
c8309ef6 CC	289	int p;
2e47b8b3	290
2e47b8b3 CC	291	local_irq_save(flags);
	292	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
	293	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	294
	295	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	296	unsigned int gpio = (b<<5) \| (p<<3);
	297	bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
	298	bank->out[p] = __raw_readl(GPIO_OUT(gpio));
	299	bank->oe[p] = __raw_readl(GPIO_OE(gpio));
	300	bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
	301	bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
	302	}
	303	}
	304	local_irq_restore(flags);
	305	}
	306
37337a8d	307	static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
2e47b8b3	308	{
37337a8d	309	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
6845664a	310	return irq_set_irq_wake(bank->irq, enable);
2e47b8b3 CC	311	}
2e47b8b3 CC	312	#endif
3c92db9a EG	313
	314	static struct irq_chip tegra_gpio_irq_chip = {
	315	.name = "GPIO",
37337a8d LB	316	.irq_ack = tegra_gpio_irq_ack,
	317	.irq_mask = tegra_gpio_irq_mask,
	318	.irq_unmask = tegra_gpio_irq_unmask,
	319	.irq_set_type = tegra_gpio_irq_set_type,
2e47b8b3	320	#ifdef CONFIG_PM
37337a8d	321	.irq_set_wake = tegra_gpio_wake_enable,
2e47b8b3	322	#endif
3c92db9a EG	323	};
	324
	325
	326	/* This lock class tells lockdep that GPIO irqs are in a different
	327	* category than their parents, so it won't report false recursion.
	328	*/
	329	static struct lock_class_key gpio_lock_class;
	330
	331	static int __init tegra_gpio_init(void)
	332	{
	333	struct tegra_gpio_bank *bank;
47008001	334	int gpio;
3c92db9a EG	335	int i;
	336	int j;
	337
	338	for (i = 0; i < 7; i++) {
	339	for (j = 0; j < 4; j++) {
	340	int gpio = tegra_gpio_compose(i, j, 0);
	341	__raw_writel(0x00, GPIO_INT_ENB(gpio));
	342	}
	343	}
	344
df221227 GL	345	#ifdef CONFIG_OF_GPIO
	346	/*
	347	* This isn't ideal, but it gets things hooked up until this
	348	* driver is converted into a platform_device
	349	*/
	350	tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
f7f678a0	351	"nvidia,tegra20-gpio");
df221227 GL	352	#endif /* CONFIG_OF_GPIO */
df221227 GL	353
3c92db9a EG	354	gpiochip_add(&tegra_gpio_chip);
3c92db9a EG	355
47008001 SW	356	for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
	357	int irq = TEGRA_GPIO_TO_IRQ(gpio);
	358	/* No validity check; all Tegra GPIOs are valid IRQs */
3c92db9a	359
47008001 SW	360	bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
	361
	362	irq_set_lockdep_class(irq, &gpio_lock_class);
	363	irq_set_chip_data(irq, bank);
	364	irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
f38c02f3	365	handle_simple_irq);
47008001	366	set_irq_flags(irq, IRQF_VALID);
3c92db9a EG	367	}
	368
	369	for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
	370	bank = &tegra_gpio_banks[i];
	371
6845664a TG	372	irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
6845664a TG	373	irq_set_handler_data(bank->irq, bank);
3c92db9a EG	374
	375	for (j = 0; j < 4; j++)
	376	spin_lock_init(&bank->lvl_lock[j]);
	377	}
	378
	379	return 0;
	380	}
	381
	382	postcore_initcall(tegra_gpio_init);
	383
632095ea OJ	384	void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
	385	{
	386	int i;
	387
	388	for (i = 0; i < num; i++) {
	389	int gpio = table[i].gpio;
	390
	391	if (table[i].enable)
	392	tegra_gpio_enable(gpio);
	393	else
	394	tegra_gpio_disable(gpio);
	395	}
	396	}
	397
3c92db9a EG	398	#ifdef CONFIG_DEBUG_FS
	399
	400	#include <linux/debugfs.h>
	401	#include <linux/seq_file.h>
	402
	403	static int dbg_gpio_show(struct seq_file s, void unused)
	404	{
	405	int i;
	406	int j;
	407
	408	for (i = 0; i < 7; i++) {
	409	for (j = 0; j < 4; j++) {
	410	int gpio = tegra_gpio_compose(i, j, 0);
2e47b8b3 CC	411	seq_printf(s,
	412	"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
	413	i, j,
	414	__raw_readl(GPIO_CNF(gpio)),
	415	__raw_readl(GPIO_OE(gpio)),
	416	__raw_readl(GPIO_OUT(gpio)),
	417	__raw_readl(GPIO_IN(gpio)),
	418	__raw_readl(GPIO_INT_STA(gpio)),
	419	__raw_readl(GPIO_INT_ENB(gpio)),
	420	__raw_readl(GPIO_INT_LVL(gpio)));
3c92db9a EG	421	}
	422	}
	423	return 0;
	424	}
	425
	426	static int dbg_gpio_open(struct inode inode, struct file file)
	427	{
	428	return single_open(file, dbg_gpio_show, &inode->i_private);
	429	}
	430
	431	static const struct file_operations debug_fops = {
	432	.open = dbg_gpio_open,
	433	.read = seq_read,
	434	.llseek = seq_lseek,
	435	.release = single_release,
	436	};
	437
	438	static int __init tegra_gpio_debuginit(void)
	439	{
	440	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
	441	NULL, NULL, &debug_fops);
	442	return 0;
	443	}
	444	late_initcall(tegra_gpio_debuginit);
	445	#endif