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Commit | Line | Data |
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3c92db9a EG |
1 | /* |
2 | * arch/arm/mach-tegra/gpio.c | |
3 | * | |
4 | * Copyright (c) 2010 Google, Inc | |
5 | * | |
6 | * Author: | |
7 | * Erik Gilling <konkers@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
641d0342 | 20 | #include <linux/err.h> |
3c92db9a EG |
21 | #include <linux/init.h> |
22 | #include <linux/irq.h> | |
2e47b8b3 | 23 | #include <linux/interrupt.h> |
3c92db9a EG |
24 | #include <linux/io.h> |
25 | #include <linux/gpio.h> | |
5c1e2c9d | 26 | #include <linux/of_device.h> |
88d8951e SW |
27 | #include <linux/platform_device.h> |
28 | #include <linux/module.h> | |
6f74dc9b | 29 | #include <linux/irqdomain.h> |
de88cbb7 | 30 | #include <linux/irqchip/chained_irq.h> |
3e215d0a | 31 | #include <linux/pinctrl/consumer.h> |
8939ddc7 | 32 | #include <linux/pm.h> |
3c92db9a | 33 | |
3c92db9a EG |
34 | #define GPIO_BANK(x) ((x) >> 5) |
35 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | |
36 | #define GPIO_BIT(x) ((x) & 0x7) | |
37 | ||
b546be0d | 38 | #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ |
5c1e2c9d | 39 | GPIO_PORT(x) * 4) |
3c92db9a | 40 | |
b546be0d LD |
41 | #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) |
42 | #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) | |
43 | #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) | |
44 | #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) | |
45 | #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) | |
46 | #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) | |
47 | #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) | |
48 | #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) | |
3737de42 LD |
49 | #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) |
50 | ||
b546be0d LD |
51 | |
52 | #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) | |
53 | #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) | |
54 | #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) | |
3737de42 | 55 | #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) |
b546be0d LD |
56 | #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) |
57 | #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) | |
58 | #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) | |
3c92db9a EG |
59 | |
60 | #define GPIO_INT_LVL_MASK 0x010101 | |
61 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 | |
62 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 | |
63 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 | |
64 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 | |
65 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 | |
66 | ||
b546be0d LD |
67 | struct tegra_gpio_info; |
68 | ||
3c92db9a EG |
69 | struct tegra_gpio_bank { |
70 | int bank; | |
71 | int irq; | |
72 | spinlock_t lvl_lock[4]; | |
3737de42 | 73 | spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */ |
8939ddc7 | 74 | #ifdef CONFIG_PM_SLEEP |
2e47b8b3 CC |
75 | u32 cnf[4]; |
76 | u32 out[4]; | |
77 | u32 oe[4]; | |
78 | u32 int_enb[4]; | |
79 | u32 int_lvl[4]; | |
203f31cb | 80 | u32 wake_enb[4]; |
3737de42 | 81 | u32 dbc_enb[4]; |
2e47b8b3 | 82 | #endif |
3737de42 | 83 | u32 dbc_cnt[4]; |
b546be0d | 84 | struct tegra_gpio_info *tgi; |
3c92db9a EG |
85 | }; |
86 | ||
171b92c8 | 87 | struct tegra_gpio_soc_config { |
3737de42 | 88 | bool debounce_supported; |
171b92c8 LD |
89 | u32 bank_stride; |
90 | u32 upper_offset; | |
91 | }; | |
92 | ||
b546be0d LD |
93 | struct tegra_gpio_info { |
94 | struct device *dev; | |
95 | void __iomem *regs; | |
96 | struct irq_domain *irq_domain; | |
97 | struct tegra_gpio_bank *bank_info; | |
98 | const struct tegra_gpio_soc_config *soc; | |
99 | struct gpio_chip gc; | |
100 | struct irq_chip ic; | |
101 | struct lock_class_key lock_class; | |
102 | u32 bank_count; | |
103 | }; | |
88d8951e | 104 | |
b546be0d LD |
105 | static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, |
106 | u32 val, u32 reg) | |
88d8951e | 107 | { |
b546be0d | 108 | __raw_writel(val, tgi->regs + reg); |
88d8951e SW |
109 | } |
110 | ||
b546be0d | 111 | static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) |
88d8951e | 112 | { |
b546be0d | 113 | return __raw_readl(tgi->regs + reg); |
88d8951e | 114 | } |
3c92db9a EG |
115 | |
116 | static int tegra_gpio_compose(int bank, int port, int bit) | |
117 | { | |
118 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); | |
119 | } | |
120 | ||
b546be0d LD |
121 | static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, |
122 | int gpio, int value) | |
3c92db9a EG |
123 | { |
124 | u32 val; | |
125 | ||
126 | val = 0x100 << GPIO_BIT(gpio); | |
127 | if (value) | |
128 | val |= 1 << GPIO_BIT(gpio); | |
b546be0d | 129 | tegra_gpio_writel(tgi, val, reg); |
3c92db9a EG |
130 | } |
131 | ||
b546be0d | 132 | static void tegra_gpio_enable(struct tegra_gpio_info *tgi, int gpio) |
3c92db9a | 133 | { |
b546be0d | 134 | tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); |
3c92db9a EG |
135 | } |
136 | ||
b546be0d | 137 | static void tegra_gpio_disable(struct tegra_gpio_info *tgi, int gpio) |
3c92db9a | 138 | { |
b546be0d | 139 | tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); |
3c92db9a EG |
140 | } |
141 | ||
924a0987 | 142 | static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset) |
3e215d0a SW |
143 | { |
144 | return pinctrl_request_gpio(offset); | |
145 | } | |
146 | ||
924a0987 | 147 | static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset) |
3e215d0a | 148 | { |
b546be0d LD |
149 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
150 | ||
3e215d0a | 151 | pinctrl_free_gpio(offset); |
b546be0d | 152 | tegra_gpio_disable(tgi, offset); |
3e215d0a SW |
153 | } |
154 | ||
3c92db9a EG |
155 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
156 | { | |
b546be0d LD |
157 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
158 | ||
159 | tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); | |
3c92db9a EG |
160 | } |
161 | ||
162 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) | |
163 | { | |
b546be0d LD |
164 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
165 | int bval = BIT(GPIO_BIT(offset)); | |
166 | ||
195812e4 | 167 | /* If gpio is in output mode then read from the out value */ |
b546be0d LD |
168 | if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) |
169 | return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); | |
195812e4 | 170 | |
b546be0d | 171 | return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); |
3c92db9a EG |
172 | } |
173 | ||
174 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
175 | { | |
b546be0d LD |
176 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
177 | ||
178 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); | |
179 | tegra_gpio_enable(tgi, offset); | |
3c92db9a EG |
180 | return 0; |
181 | } | |
182 | ||
183 | static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
184 | int value) | |
185 | { | |
b546be0d LD |
186 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
187 | ||
3c92db9a | 188 | tegra_gpio_set(chip, offset, value); |
b546be0d LD |
189 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); |
190 | tegra_gpio_enable(tgi, offset); | |
3c92db9a EG |
191 | return 0; |
192 | } | |
193 | ||
3737de42 LD |
194 | static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, |
195 | unsigned int debounce) | |
196 | { | |
197 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); | |
198 | struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; | |
199 | unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); | |
200 | unsigned long flags; | |
201 | int port; | |
202 | ||
203 | if (!debounce_ms) { | |
204 | tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), | |
205 | offset, 0); | |
206 | return 0; | |
207 | } | |
208 | ||
209 | debounce_ms = min(debounce_ms, 255U); | |
210 | port = GPIO_PORT(offset); | |
211 | ||
212 | /* There is only one debounce count register per port and hence | |
213 | * set the maximum of current and requested debounce time. | |
214 | */ | |
215 | spin_lock_irqsave(&bank->dbc_lock[port], flags); | |
216 | if (bank->dbc_cnt[port] < debounce_ms) { | |
217 | tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); | |
218 | bank->dbc_cnt[port] = debounce_ms; | |
219 | } | |
220 | spin_unlock_irqrestore(&bank->dbc_lock[port], flags); | |
221 | ||
222 | tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
438a99c0 SW |
227 | static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
228 | { | |
b546be0d | 229 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
3c92db9a | 230 | |
b546be0d LD |
231 | return irq_find_mapping(tgi->irq_domain, offset); |
232 | } | |
3c92db9a | 233 | |
37337a8d | 234 | static void tegra_gpio_irq_ack(struct irq_data *d) |
3c92db9a | 235 | { |
b546be0d LD |
236 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
237 | struct tegra_gpio_info *tgi = bank->tgi; | |
6f74dc9b | 238 | int gpio = d->hwirq; |
3c92db9a | 239 | |
b546be0d | 240 | tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); |
3c92db9a EG |
241 | } |
242 | ||
37337a8d | 243 | static void tegra_gpio_irq_mask(struct irq_data *d) |
3c92db9a | 244 | { |
b546be0d LD |
245 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
246 | struct tegra_gpio_info *tgi = bank->tgi; | |
6f74dc9b | 247 | int gpio = d->hwirq; |
3c92db9a | 248 | |
b546be0d | 249 | tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); |
3c92db9a EG |
250 | } |
251 | ||
37337a8d | 252 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
3c92db9a | 253 | { |
b546be0d LD |
254 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
255 | struct tegra_gpio_info *tgi = bank->tgi; | |
6f74dc9b | 256 | int gpio = d->hwirq; |
3c92db9a | 257 | |
b546be0d | 258 | tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); |
3c92db9a EG |
259 | } |
260 | ||
37337a8d | 261 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
3c92db9a | 262 | { |
6f74dc9b | 263 | int gpio = d->hwirq; |
37337a8d | 264 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
b546be0d | 265 | struct tegra_gpio_info *tgi = bank->tgi; |
3c92db9a EG |
266 | int port = GPIO_PORT(gpio); |
267 | int lvl_type; | |
268 | int val; | |
269 | unsigned long flags; | |
df231f28 | 270 | int ret; |
3c92db9a EG |
271 | |
272 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
273 | case IRQ_TYPE_EDGE_RISING: | |
274 | lvl_type = GPIO_INT_LVL_EDGE_RISING; | |
275 | break; | |
276 | ||
277 | case IRQ_TYPE_EDGE_FALLING: | |
278 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; | |
279 | break; | |
280 | ||
281 | case IRQ_TYPE_EDGE_BOTH: | |
282 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; | |
283 | break; | |
284 | ||
285 | case IRQ_TYPE_LEVEL_HIGH: | |
286 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; | |
287 | break; | |
288 | ||
289 | case IRQ_TYPE_LEVEL_LOW: | |
290 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; | |
291 | break; | |
292 | ||
293 | default: | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
b546be0d | 297 | ret = gpiochip_lock_as_irq(&tgi->gc, gpio); |
df231f28 | 298 | if (ret) { |
b546be0d LD |
299 | dev_err(tgi->dev, |
300 | "unable to lock Tegra GPIO %d as IRQ\n", gpio); | |
df231f28 SW |
301 | return ret; |
302 | } | |
303 | ||
3c92db9a EG |
304 | spin_lock_irqsave(&bank->lvl_lock[port], flags); |
305 | ||
b546be0d | 306 | val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); |
3c92db9a EG |
307 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
308 | val |= lvl_type << GPIO_BIT(gpio); | |
b546be0d | 309 | tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); |
3c92db9a EG |
310 | |
311 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | |
312 | ||
b546be0d LD |
313 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); |
314 | tegra_gpio_enable(tgi, gpio); | |
d941136f | 315 | |
3c92db9a | 316 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
f170d71e | 317 | irq_set_handler_locked(d, handle_level_irq); |
3c92db9a | 318 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
f170d71e | 319 | irq_set_handler_locked(d, handle_edge_irq); |
3c92db9a EG |
320 | |
321 | return 0; | |
322 | } | |
323 | ||
df231f28 SW |
324 | static void tegra_gpio_irq_shutdown(struct irq_data *d) |
325 | { | |
b546be0d LD |
326 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
327 | struct tegra_gpio_info *tgi = bank->tgi; | |
df231f28 SW |
328 | int gpio = d->hwirq; |
329 | ||
b546be0d | 330 | gpiochip_unlock_as_irq(&tgi->gc, gpio); |
df231f28 SW |
331 | } |
332 | ||
bd0b9ac4 | 333 | static void tegra_gpio_irq_handler(struct irq_desc *desc) |
3c92db9a | 334 | { |
3c92db9a EG |
335 | int port; |
336 | int pin; | |
337 | int unmasked = 0; | |
b546be0d LD |
338 | int gpio; |
339 | u32 lvl; | |
340 | unsigned long sta; | |
98022940 | 341 | struct irq_chip *chip = irq_desc_get_chip(desc); |
476f8b4c | 342 | struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); |
b546be0d | 343 | struct tegra_gpio_info *tgi = bank->tgi; |
3c92db9a | 344 | |
98022940 | 345 | chained_irq_enter(chip, desc); |
3c92db9a | 346 | |
3c92db9a | 347 | for (port = 0; port < 4; port++) { |
b546be0d LD |
348 | gpio = tegra_gpio_compose(bank->bank, port, 0); |
349 | sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & | |
350 | tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); | |
351 | lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); | |
3c92db9a EG |
352 | |
353 | for_each_set_bit(pin, &sta, 8) { | |
b546be0d LD |
354 | tegra_gpio_writel(tgi, 1 << pin, |
355 | GPIO_INT_CLR(tgi, gpio)); | |
3c92db9a EG |
356 | |
357 | /* if gpio is edge triggered, clear condition | |
20a8a968 | 358 | * before executing the handler so that we don't |
3c92db9a EG |
359 | * miss edges |
360 | */ | |
361 | if (lvl & (0x100 << pin)) { | |
362 | unmasked = 1; | |
98022940 | 363 | chained_irq_exit(chip, desc); |
3c92db9a EG |
364 | } |
365 | ||
366 | generic_handle_irq(gpio_to_irq(gpio + pin)); | |
367 | } | |
368 | } | |
369 | ||
370 | if (!unmasked) | |
98022940 | 371 | chained_irq_exit(chip, desc); |
3c92db9a EG |
372 | |
373 | } | |
374 | ||
8939ddc7 LD |
375 | #ifdef CONFIG_PM_SLEEP |
376 | static int tegra_gpio_resume(struct device *dev) | |
2e47b8b3 | 377 | { |
b546be0d LD |
378 | struct platform_device *pdev = to_platform_device(dev); |
379 | struct tegra_gpio_info *tgi = platform_get_drvdata(pdev); | |
2e47b8b3 | 380 | unsigned long flags; |
c8309ef6 CC |
381 | int b; |
382 | int p; | |
2e47b8b3 CC |
383 | |
384 | local_irq_save(flags); | |
385 | ||
b546be0d LD |
386 | for (b = 0; b < tgi->bank_count; b++) { |
387 | struct tegra_gpio_bank *bank = &tgi->bank_info[b]; | |
2e47b8b3 CC |
388 | |
389 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
390 | unsigned int gpio = (b<<5) | (p<<3); | |
b546be0d LD |
391 | tegra_gpio_writel(tgi, bank->cnf[p], |
392 | GPIO_CNF(tgi, gpio)); | |
3737de42 LD |
393 | |
394 | if (tgi->soc->debounce_supported) { | |
395 | tegra_gpio_writel(tgi, bank->dbc_cnt[p], | |
396 | GPIO_DBC_CNT(tgi, gpio)); | |
397 | tegra_gpio_writel(tgi, bank->dbc_enb[p], | |
398 | GPIO_MSK_DBC_EN(tgi, gpio)); | |
399 | } | |
400 | ||
b546be0d LD |
401 | tegra_gpio_writel(tgi, bank->out[p], |
402 | GPIO_OUT(tgi, gpio)); | |
403 | tegra_gpio_writel(tgi, bank->oe[p], | |
404 | GPIO_OE(tgi, gpio)); | |
405 | tegra_gpio_writel(tgi, bank->int_lvl[p], | |
406 | GPIO_INT_LVL(tgi, gpio)); | |
407 | tegra_gpio_writel(tgi, bank->int_enb[p], | |
408 | GPIO_INT_ENB(tgi, gpio)); | |
2e47b8b3 CC |
409 | } |
410 | } | |
411 | ||
412 | local_irq_restore(flags); | |
8939ddc7 | 413 | return 0; |
2e47b8b3 CC |
414 | } |
415 | ||
8939ddc7 | 416 | static int tegra_gpio_suspend(struct device *dev) |
2e47b8b3 | 417 | { |
b546be0d LD |
418 | struct platform_device *pdev = to_platform_device(dev); |
419 | struct tegra_gpio_info *tgi = platform_get_drvdata(pdev); | |
2e47b8b3 | 420 | unsigned long flags; |
c8309ef6 CC |
421 | int b; |
422 | int p; | |
2e47b8b3 | 423 | |
2e47b8b3 | 424 | local_irq_save(flags); |
b546be0d LD |
425 | for (b = 0; b < tgi->bank_count; b++) { |
426 | struct tegra_gpio_bank *bank = &tgi->bank_info[b]; | |
2e47b8b3 CC |
427 | |
428 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
429 | unsigned int gpio = (b<<5) | (p<<3); | |
b546be0d LD |
430 | bank->cnf[p] = tegra_gpio_readl(tgi, |
431 | GPIO_CNF(tgi, gpio)); | |
432 | bank->out[p] = tegra_gpio_readl(tgi, | |
433 | GPIO_OUT(tgi, gpio)); | |
434 | bank->oe[p] = tegra_gpio_readl(tgi, | |
435 | GPIO_OE(tgi, gpio)); | |
3737de42 LD |
436 | if (tgi->soc->debounce_supported) { |
437 | bank->dbc_enb[p] = tegra_gpio_readl(tgi, | |
438 | GPIO_MSK_DBC_EN(tgi, gpio)); | |
439 | bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | | |
440 | bank->dbc_enb[p]; | |
441 | } | |
442 | ||
b546be0d LD |
443 | bank->int_enb[p] = tegra_gpio_readl(tgi, |
444 | GPIO_INT_ENB(tgi, gpio)); | |
445 | bank->int_lvl[p] = tegra_gpio_readl(tgi, | |
446 | GPIO_INT_LVL(tgi, gpio)); | |
203f31cb JL |
447 | |
448 | /* Enable gpio irq for wake up source */ | |
b546be0d LD |
449 | tegra_gpio_writel(tgi, bank->wake_enb[p], |
450 | GPIO_INT_ENB(tgi, gpio)); | |
2e47b8b3 CC |
451 | } |
452 | } | |
453 | local_irq_restore(flags); | |
8939ddc7 | 454 | return 0; |
2e47b8b3 CC |
455 | } |
456 | ||
203f31cb | 457 | static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) |
2e47b8b3 | 458 | { |
37337a8d | 459 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
203f31cb JL |
460 | int gpio = d->hwirq; |
461 | u32 port, bit, mask; | |
462 | ||
463 | port = GPIO_PORT(gpio); | |
464 | bit = GPIO_BIT(gpio); | |
465 | mask = BIT(bit); | |
466 | ||
467 | if (enable) | |
468 | bank->wake_enb[port] |= mask; | |
469 | else | |
470 | bank->wake_enb[port] &= ~mask; | |
471 | ||
6845664a | 472 | return irq_set_irq_wake(bank->irq, enable); |
2e47b8b3 CC |
473 | } |
474 | #endif | |
3c92db9a | 475 | |
b59d5fb7 SP |
476 | #ifdef CONFIG_DEBUG_FS |
477 | ||
478 | #include <linux/debugfs.h> | |
479 | #include <linux/seq_file.h> | |
480 | ||
481 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
482 | { | |
b546be0d | 483 | struct tegra_gpio_info *tgi = s->private; |
b59d5fb7 SP |
484 | int i; |
485 | int j; | |
486 | ||
b546be0d | 487 | for (i = 0; i < tgi->bank_count; i++) { |
b59d5fb7 SP |
488 | for (j = 0; j < 4; j++) { |
489 | int gpio = tegra_gpio_compose(i, j, 0); | |
490 | seq_printf(s, | |
491 | "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", | |
492 | i, j, | |
b546be0d LD |
493 | tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), |
494 | tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), | |
495 | tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), | |
496 | tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), | |
497 | tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), | |
498 | tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), | |
499 | tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); | |
b59d5fb7 SP |
500 | } |
501 | } | |
502 | return 0; | |
503 | } | |
504 | ||
505 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
506 | { | |
b546be0d | 507 | return single_open(file, dbg_gpio_show, inode->i_private); |
b59d5fb7 SP |
508 | } |
509 | ||
510 | static const struct file_operations debug_fops = { | |
511 | .open = dbg_gpio_open, | |
512 | .read = seq_read, | |
513 | .llseek = seq_lseek, | |
514 | .release = single_release, | |
515 | }; | |
516 | ||
b546be0d | 517 | static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
b59d5fb7 SP |
518 | { |
519 | (void) debugfs_create_file("tegra_gpio", S_IRUGO, | |
b546be0d | 520 | NULL, tgi, &debug_fops); |
b59d5fb7 SP |
521 | } |
522 | ||
523 | #else | |
524 | ||
b546be0d | 525 | static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
b59d5fb7 SP |
526 | { |
527 | } | |
528 | ||
529 | #endif | |
530 | ||
8939ddc7 LD |
531 | static const struct dev_pm_ops tegra_gpio_pm_ops = { |
532 | SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) | |
533 | }; | |
534 | ||
3836309d | 535 | static int tegra_gpio_probe(struct platform_device *pdev) |
3c92db9a | 536 | { |
171b92c8 | 537 | const struct tegra_gpio_soc_config *config; |
b546be0d | 538 | struct tegra_gpio_info *tgi; |
88d8951e | 539 | struct resource *res; |
3c92db9a | 540 | struct tegra_gpio_bank *bank; |
f57f98a6 | 541 | int ret; |
47008001 | 542 | int gpio; |
3c92db9a EG |
543 | int i; |
544 | int j; | |
545 | ||
171b92c8 LD |
546 | config = of_device_get_match_data(&pdev->dev); |
547 | if (!config) { | |
165b6c2f SW |
548 | dev_err(&pdev->dev, "Error: No device match found\n"); |
549 | return -ENODEV; | |
550 | } | |
5c1e2c9d | 551 | |
b546be0d LD |
552 | tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); |
553 | if (!tgi) | |
554 | return -ENODEV; | |
555 | ||
556 | tgi->soc = config; | |
557 | tgi->dev = &pdev->dev; | |
5c1e2c9d | 558 | |
3391811c | 559 | for (;;) { |
b546be0d LD |
560 | res = platform_get_resource(pdev, IORESOURCE_IRQ, |
561 | tgi->bank_count); | |
3391811c SW |
562 | if (!res) |
563 | break; | |
b546be0d | 564 | tgi->bank_count++; |
3391811c | 565 | } |
b546be0d | 566 | if (!tgi->bank_count) { |
3391811c SW |
567 | dev_err(&pdev->dev, "Missing IRQ resource\n"); |
568 | return -ENODEV; | |
569 | } | |
570 | ||
b546be0d LD |
571 | tgi->gc.label = "tegra-gpio"; |
572 | tgi->gc.request = tegra_gpio_request; | |
573 | tgi->gc.free = tegra_gpio_free; | |
574 | tgi->gc.direction_input = tegra_gpio_direction_input; | |
575 | tgi->gc.get = tegra_gpio_get; | |
576 | tgi->gc.direction_output = tegra_gpio_direction_output; | |
577 | tgi->gc.set = tegra_gpio_set; | |
578 | tgi->gc.to_irq = tegra_gpio_to_irq; | |
579 | tgi->gc.base = 0; | |
580 | tgi->gc.ngpio = tgi->bank_count * 32; | |
581 | tgi->gc.parent = &pdev->dev; | |
582 | tgi->gc.of_node = pdev->dev.of_node; | |
583 | ||
584 | tgi->ic.name = "GPIO"; | |
585 | tgi->ic.irq_ack = tegra_gpio_irq_ack; | |
586 | tgi->ic.irq_mask = tegra_gpio_irq_mask; | |
587 | tgi->ic.irq_unmask = tegra_gpio_irq_unmask; | |
588 | tgi->ic.irq_set_type = tegra_gpio_irq_set_type; | |
589 | tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown; | |
590 | #ifdef CONFIG_PM_SLEEP | |
591 | tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake; | |
592 | #endif | |
593 | ||
594 | platform_set_drvdata(pdev, tgi); | |
3391811c | 595 | |
3737de42 LD |
596 | if (config->debounce_supported) |
597 | tgi->gc.set_debounce = tegra_gpio_set_debounce; | |
598 | ||
b546be0d LD |
599 | tgi->bank_info = devm_kzalloc(&pdev->dev, tgi->bank_count * |
600 | sizeof(*tgi->bank_info), GFP_KERNEL); | |
601 | if (!tgi->bank_info) | |
3391811c | 602 | return -ENODEV; |
3391811c | 603 | |
b546be0d LD |
604 | tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node, |
605 | tgi->gc.ngpio, | |
606 | &irq_domain_simple_ops, NULL); | |
607 | if (!tgi->irq_domain) | |
d0235677 | 608 | return -ENODEV; |
6f74dc9b | 609 | |
b546be0d | 610 | for (i = 0; i < tgi->bank_count; i++) { |
88d8951e SW |
611 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); |
612 | if (!res) { | |
613 | dev_err(&pdev->dev, "Missing IRQ resource\n"); | |
614 | return -ENODEV; | |
615 | } | |
616 | ||
b546be0d | 617 | bank = &tgi->bank_info[i]; |
88d8951e SW |
618 | bank->bank = i; |
619 | bank->irq = res->start; | |
b546be0d | 620 | bank->tgi = tgi; |
88d8951e SW |
621 | } |
622 | ||
623 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b546be0d LD |
624 | tgi->regs = devm_ioremap_resource(&pdev->dev, res); |
625 | if (IS_ERR(tgi->regs)) | |
626 | return PTR_ERR(tgi->regs); | |
88d8951e | 627 | |
b546be0d | 628 | for (i = 0; i < tgi->bank_count; i++) { |
3c92db9a EG |
629 | for (j = 0; j < 4; j++) { |
630 | int gpio = tegra_gpio_compose(i, j, 0); | |
b546be0d | 631 | tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); |
3c92db9a EG |
632 | } |
633 | } | |
634 | ||
b546be0d | 635 | ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); |
f57f98a6 | 636 | if (ret < 0) { |
b546be0d | 637 | irq_domain_remove(tgi->irq_domain); |
f57f98a6 SW |
638 | return ret; |
639 | } | |
3c92db9a | 640 | |
b546be0d LD |
641 | for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) { |
642 | int irq = irq_create_mapping(tgi->irq_domain, gpio); | |
47008001 | 643 | /* No validity check; all Tegra GPIOs are valid IRQs */ |
3c92db9a | 644 | |
b546be0d | 645 | bank = &tgi->bank_info[GPIO_BANK(gpio)]; |
3c92db9a | 646 | |
b546be0d | 647 | irq_set_lockdep_class(irq, &tgi->lock_class); |
47008001 | 648 | irq_set_chip_data(irq, bank); |
b546be0d | 649 | irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq); |
3c92db9a EG |
650 | } |
651 | ||
b546be0d LD |
652 | for (i = 0; i < tgi->bank_count; i++) { |
653 | bank = &tgi->bank_info[i]; | |
3c92db9a | 654 | |
e88d251d RK |
655 | irq_set_chained_handler_and_data(bank->irq, |
656 | tegra_gpio_irq_handler, bank); | |
3c92db9a | 657 | |
3737de42 | 658 | for (j = 0; j < 4; j++) { |
3c92db9a | 659 | spin_lock_init(&bank->lvl_lock[j]); |
3737de42 LD |
660 | spin_lock_init(&bank->dbc_lock[j]); |
661 | } | |
3c92db9a EG |
662 | } |
663 | ||
b546be0d | 664 | tegra_gpio_debuginit(tgi); |
b59d5fb7 | 665 | |
3c92db9a EG |
666 | return 0; |
667 | } | |
668 | ||
804f5680 | 669 | static const struct tegra_gpio_soc_config tegra20_gpio_config = { |
171b92c8 LD |
670 | .bank_stride = 0x80, |
671 | .upper_offset = 0x800, | |
672 | }; | |
673 | ||
804f5680 | 674 | static const struct tegra_gpio_soc_config tegra30_gpio_config = { |
171b92c8 LD |
675 | .bank_stride = 0x100, |
676 | .upper_offset = 0x80, | |
677 | }; | |
678 | ||
3737de42 LD |
679 | static const struct tegra_gpio_soc_config tegra210_gpio_config = { |
680 | .debounce_supported = true, | |
681 | .bank_stride = 0x100, | |
682 | .upper_offset = 0x80, | |
683 | }; | |
684 | ||
171b92c8 | 685 | static const struct of_device_id tegra_gpio_of_match[] = { |
3737de42 | 686 | { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, |
171b92c8 LD |
687 | { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, |
688 | { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, | |
689 | { }, | |
690 | }; | |
691 | ||
88d8951e SW |
692 | static struct platform_driver tegra_gpio_driver = { |
693 | .driver = { | |
694 | .name = "tegra-gpio", | |
8939ddc7 | 695 | .pm = &tegra_gpio_pm_ops, |
88d8951e SW |
696 | .of_match_table = tegra_gpio_of_match, |
697 | }, | |
698 | .probe = tegra_gpio_probe, | |
699 | }; | |
700 | ||
701 | static int __init tegra_gpio_init(void) | |
702 | { | |
703 | return platform_driver_register(&tegra_gpio_driver); | |
704 | } | |
3c92db9a | 705 | postcore_initcall(tegra_gpio_init); |