]>
Commit | Line | Data |
---|---|---|
9caf1f22 JH |
1 | /* |
2 | * Toumaz Xenif TZ1090 GPIO handling. | |
3 | * | |
4 | * Copyright (C) 2008-2013 Imagination Technologies Ltd. | |
5 | * | |
6 | * Based on ARM PXA code and others. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/bitops.h> | |
14 | #include <linux/export.h> | |
15 | #include <linux/gpio.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/irqdomain.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/pinctrl/consumer.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/syscore_ops.h> | |
26 | #include <asm/global_lock.h> | |
27 | ||
28 | /* Register offsets from bank base address */ | |
29 | #define REG_GPIO_DIR 0x00 | |
30 | #define REG_GPIO_IRQ_PLRT 0x20 | |
31 | #define REG_GPIO_IRQ_TYPE 0x30 | |
32 | #define REG_GPIO_IRQ_EN 0x40 | |
33 | #define REG_GPIO_IRQ_STS 0x50 | |
34 | #define REG_GPIO_BIT_EN 0x60 | |
35 | #define REG_GPIO_DIN 0x70 | |
36 | #define REG_GPIO_DOUT 0x80 | |
37 | ||
38 | /* REG_GPIO_IRQ_PLRT */ | |
39 | #define REG_GPIO_IRQ_PLRT_LOW 0 | |
40 | #define REG_GPIO_IRQ_PLRT_HIGH 1 | |
41 | ||
42 | /* REG_GPIO_IRQ_TYPE */ | |
43 | #define REG_GPIO_IRQ_TYPE_LEVEL 0 | |
44 | #define REG_GPIO_IRQ_TYPE_EDGE 1 | |
45 | ||
46 | /** | |
47 | * struct tz1090_gpio_bank - GPIO bank private data | |
48 | * @chip: Generic GPIO chip for GPIO bank | |
49 | * @domain: IRQ domain for GPIO bank (may be NULL) | |
50 | * @reg: Base of registers, offset for this GPIO bank | |
51 | * @irq: IRQ number for GPIO bank | |
52 | * @label: Debug GPIO bank label, used for storage of chip->label | |
53 | * | |
54 | * This is the main private data for a GPIO bank. It encapsulates a gpio_chip, | |
55 | * and the callbacks for the gpio_chip can access the private data with the | |
56 | * to_bank() macro below. | |
57 | */ | |
58 | struct tz1090_gpio_bank { | |
59 | struct gpio_chip chip; | |
60 | struct irq_domain *domain; | |
61 | void __iomem *reg; | |
62 | int irq; | |
63 | char label[16]; | |
64 | }; | |
65 | #define to_bank(c) container_of(c, struct tz1090_gpio_bank, chip) | |
66 | ||
67 | /** | |
68 | * struct tz1090_gpio - Overall GPIO device private data | |
69 | * @dev: Device (from platform device) | |
70 | * @reg: Base of GPIO registers | |
71 | * | |
72 | * Represents the overall GPIO device. This structure is actually only | |
73 | * temporary, and used during init. | |
74 | */ | |
75 | struct tz1090_gpio { | |
76 | struct device *dev; | |
77 | void __iomem *reg; | |
78 | }; | |
79 | ||
80 | /** | |
81 | * struct tz1090_gpio_bank_info - Temporary registration info for GPIO bank | |
82 | * @priv: Overall GPIO device private data | |
83 | * @node: Device tree node specific to this GPIO bank | |
84 | * @index: Index of bank in range 0-2 | |
85 | */ | |
86 | struct tz1090_gpio_bank_info { | |
87 | struct tz1090_gpio *priv; | |
88 | struct device_node *node; | |
89 | unsigned int index; | |
90 | }; | |
91 | ||
92 | /* Convenience register accessors */ | |
93 | static inline void tz1090_gpio_write(struct tz1090_gpio_bank *bank, | |
94 | unsigned int reg_offs, u32 data) | |
95 | { | |
96 | iowrite32(data, bank->reg + reg_offs); | |
97 | } | |
98 | ||
99 | static inline u32 tz1090_gpio_read(struct tz1090_gpio_bank *bank, | |
100 | unsigned int reg_offs) | |
101 | { | |
102 | return ioread32(bank->reg + reg_offs); | |
103 | } | |
104 | ||
105 | /* caller must hold LOCK2 */ | |
106 | static inline void _tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank, | |
107 | unsigned int reg_offs, | |
108 | unsigned int offset) | |
109 | { | |
110 | u32 value; | |
111 | ||
112 | value = tz1090_gpio_read(bank, reg_offs); | |
113 | value &= ~BIT(offset); | |
114 | tz1090_gpio_write(bank, reg_offs, value); | |
115 | } | |
116 | ||
117 | static void tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank, | |
118 | unsigned int reg_offs, | |
119 | unsigned int offset) | |
120 | { | |
121 | int lstat; | |
122 | ||
123 | __global_lock2(lstat); | |
124 | _tz1090_gpio_clear_bit(bank, reg_offs, offset); | |
125 | __global_unlock2(lstat); | |
126 | } | |
127 | ||
128 | /* caller must hold LOCK2 */ | |
129 | static inline void _tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank, | |
130 | unsigned int reg_offs, | |
131 | unsigned int offset) | |
132 | { | |
133 | u32 value; | |
134 | ||
135 | value = tz1090_gpio_read(bank, reg_offs); | |
136 | value |= BIT(offset); | |
137 | tz1090_gpio_write(bank, reg_offs, value); | |
138 | } | |
139 | ||
140 | static void tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank, | |
141 | unsigned int reg_offs, | |
142 | unsigned int offset) | |
143 | { | |
144 | int lstat; | |
145 | ||
146 | __global_lock2(lstat); | |
147 | _tz1090_gpio_set_bit(bank, reg_offs, offset); | |
148 | __global_unlock2(lstat); | |
149 | } | |
150 | ||
151 | /* caller must hold LOCK2 */ | |
152 | static inline void _tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank, | |
153 | unsigned int reg_offs, | |
154 | unsigned int offset, | |
155 | bool val) | |
156 | { | |
157 | u32 value; | |
158 | ||
159 | value = tz1090_gpio_read(bank, reg_offs); | |
160 | value &= ~BIT(offset); | |
161 | if (val) | |
162 | value |= BIT(offset); | |
163 | tz1090_gpio_write(bank, reg_offs, value); | |
164 | } | |
165 | ||
166 | static void tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank, | |
167 | unsigned int reg_offs, | |
168 | unsigned int offset, | |
169 | bool val) | |
170 | { | |
171 | int lstat; | |
172 | ||
173 | __global_lock2(lstat); | |
174 | _tz1090_gpio_mod_bit(bank, reg_offs, offset, val); | |
175 | __global_unlock2(lstat); | |
176 | } | |
177 | ||
178 | static inline int tz1090_gpio_read_bit(struct tz1090_gpio_bank *bank, | |
179 | unsigned int reg_offs, | |
180 | unsigned int offset) | |
181 | { | |
182 | return tz1090_gpio_read(bank, reg_offs) & BIT(offset); | |
183 | } | |
184 | ||
185 | /* GPIO chip callbacks */ | |
186 | ||
187 | static int tz1090_gpio_direction_input(struct gpio_chip *chip, | |
188 | unsigned int offset) | |
189 | { | |
190 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
191 | tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset); | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | static int tz1090_gpio_direction_output(struct gpio_chip *chip, | |
197 | unsigned int offset, int output_value) | |
198 | { | |
199 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
200 | int lstat; | |
201 | ||
202 | __global_lock2(lstat); | |
203 | _tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value); | |
204 | _tz1090_gpio_clear_bit(bank, REG_GPIO_DIR, offset); | |
205 | __global_unlock2(lstat); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | /* | |
211 | * Return GPIO level | |
212 | */ | |
213 | static int tz1090_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
214 | { | |
215 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
216 | ||
217 | return tz1090_gpio_read_bit(bank, REG_GPIO_DIN, offset); | |
218 | } | |
219 | ||
220 | /* | |
221 | * Set output GPIO level | |
222 | */ | |
223 | static void tz1090_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
224 | int output_value) | |
225 | { | |
226 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
227 | ||
228 | tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value); | |
229 | } | |
230 | ||
231 | static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset) | |
232 | { | |
233 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
234 | int ret; | |
235 | ||
236 | ret = pinctrl_request_gpio(chip->base + offset); | |
237 | if (ret) | |
238 | return ret; | |
239 | ||
240 | tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset); | |
241 | tz1090_gpio_set_bit(bank, REG_GPIO_BIT_EN, offset); | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset) | |
247 | { | |
248 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
249 | ||
250 | pinctrl_free_gpio(chip->base + offset); | |
251 | ||
252 | tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset); | |
253 | } | |
254 | ||
255 | static int tz1090_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) | |
256 | { | |
257 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
258 | ||
259 | if (!bank->domain) | |
260 | return -EINVAL; | |
261 | ||
262 | return irq_create_mapping(bank->domain, offset); | |
263 | } | |
264 | ||
265 | /* IRQ chip handlers */ | |
266 | ||
267 | /* Get TZ1090 GPIO chip from irq data provided to generic IRQ callbacks */ | |
268 | static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data) | |
269 | { | |
270 | return (struct tz1090_gpio_bank *)data->domain->host_data; | |
271 | } | |
272 | ||
9caf1f22 JH |
273 | static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank, |
274 | unsigned int offset, unsigned int polarity) | |
275 | { | |
276 | tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity); | |
277 | } | |
278 | ||
9caf1f22 JH |
279 | static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank, |
280 | unsigned int offset, unsigned int type) | |
281 | { | |
282 | tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_TYPE, offset, type); | |
283 | } | |
284 | ||
285 | /* set polarity to trigger on next edge, whether rising or falling */ | |
286 | static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank, | |
287 | unsigned int offset) | |
288 | { | |
289 | unsigned int value_p, value_i; | |
290 | int lstat; | |
291 | ||
292 | /* | |
293 | * Set the GPIO's interrupt polarity to the opposite of the current | |
294 | * input value so that the next edge triggers an interrupt. | |
295 | */ | |
296 | __global_lock2(lstat); | |
297 | value_i = ~tz1090_gpio_read(bank, REG_GPIO_DIN); | |
298 | value_p = tz1090_gpio_read(bank, REG_GPIO_IRQ_PLRT); | |
299 | value_p &= ~BIT(offset); | |
300 | value_p |= value_i & BIT(offset); | |
301 | tz1090_gpio_write(bank, REG_GPIO_IRQ_PLRT, value_p); | |
302 | __global_unlock2(lstat); | |
303 | } | |
304 | ||
9caf1f22 JH |
305 | static unsigned int gpio_startup_irq(struct irq_data *data) |
306 | { | |
9caf1f22 JH |
307 | /* |
308 | * This warning indicates that the type of the irq hasn't been set | |
309 | * before enabling the irq. This would normally be done by passing some | |
310 | * trigger flags to request_irq(). | |
311 | */ | |
04777396 | 312 | WARN(irqd_get_trigger_type(data) == IRQ_TYPE_NONE, |
9caf1f22 JH |
313 | "irq type not set before enabling gpio irq %d", data->irq); |
314 | ||
04777396 JH |
315 | irq_gc_ack_clr_bit(data); |
316 | irq_gc_mask_set_bit(data); | |
9caf1f22 JH |
317 | return 0; |
318 | } | |
319 | ||
320 | static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type) | |
321 | { | |
322 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | |
323 | unsigned int type; | |
324 | unsigned int polarity; | |
325 | ||
326 | switch (flow_type) { | |
327 | case IRQ_TYPE_EDGE_BOTH: | |
328 | type = REG_GPIO_IRQ_TYPE_EDGE; | |
329 | polarity = REG_GPIO_IRQ_PLRT_LOW; | |
330 | break; | |
331 | case IRQ_TYPE_EDGE_RISING: | |
332 | type = REG_GPIO_IRQ_TYPE_EDGE; | |
333 | polarity = REG_GPIO_IRQ_PLRT_HIGH; | |
334 | break; | |
335 | case IRQ_TYPE_EDGE_FALLING: | |
336 | type = REG_GPIO_IRQ_TYPE_EDGE; | |
337 | polarity = REG_GPIO_IRQ_PLRT_LOW; | |
338 | break; | |
339 | case IRQ_TYPE_LEVEL_HIGH: | |
340 | type = REG_GPIO_IRQ_TYPE_LEVEL; | |
341 | polarity = REG_GPIO_IRQ_PLRT_HIGH; | |
342 | break; | |
343 | case IRQ_TYPE_LEVEL_LOW: | |
344 | type = REG_GPIO_IRQ_TYPE_LEVEL; | |
345 | polarity = REG_GPIO_IRQ_PLRT_LOW; | |
346 | break; | |
347 | default: | |
348 | return -EINVAL; | |
349 | } | |
350 | ||
351 | tz1090_gpio_irq_type(bank, data->hwirq, type); | |
04777396 | 352 | irq_setup_alt_chip(data, flow_type); |
9caf1f22 JH |
353 | |
354 | if (flow_type == IRQ_TYPE_EDGE_BOTH) | |
355 | tz1090_gpio_irq_next_edge(bank, data->hwirq); | |
356 | else | |
357 | tz1090_gpio_irq_polarity(bank, data->hwirq, polarity); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | #ifdef CONFIG_SUSPEND | |
363 | static int gpio_set_irq_wake(struct irq_data *data, unsigned int on) | |
364 | { | |
365 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | |
366 | ||
367 | #ifdef CONFIG_PM_DEBUG | |
368 | pr_info("irq_wake irq%d state:%d\n", data->irq, on); | |
369 | #endif | |
370 | ||
371 | /* wake on gpio block interrupt */ | |
372 | return irq_set_irq_wake(bank->irq, on); | |
373 | } | |
374 | #else | |
375 | #define gpio_set_irq_wake NULL | |
376 | #endif | |
377 | ||
9caf1f22 JH |
378 | static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
379 | { | |
380 | irq_hw_number_t hw; | |
381 | unsigned int irq_stat, irq_no; | |
382 | struct tz1090_gpio_bank *bank; | |
383 | struct irq_desc *child_desc; | |
384 | ||
385 | bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc); | |
386 | irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) & | |
387 | tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) & | |
388 | tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) & | |
389 | 0x3FFFFFFF; /* 30 bits only */ | |
390 | ||
391 | for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) { | |
392 | if (!(irq_stat & 1)) | |
393 | continue; | |
394 | ||
395 | irq_no = irq_linear_revmap(bank->domain, hw); | |
396 | child_desc = irq_to_desc(irq_no); | |
397 | ||
398 | /* Toggle edge for pin with both edges triggering enabled */ | |
399 | if (irqd_get_trigger_type(&child_desc->irq_data) | |
400 | == IRQ_TYPE_EDGE_BOTH) | |
401 | tz1090_gpio_irq_next_edge(bank, hw); | |
402 | ||
9caf1f22 JH |
403 | generic_handle_irq_desc(irq_no, child_desc); |
404 | } | |
405 | } | |
406 | ||
9caf1f22 JH |
407 | static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info) |
408 | { | |
409 | struct device_node *np = info->node; | |
410 | struct device *dev = info->priv->dev; | |
411 | struct tz1090_gpio_bank *bank; | |
04777396 JH |
412 | struct irq_chip_generic *gc; |
413 | int err; | |
9caf1f22 JH |
414 | |
415 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); | |
416 | if (!bank) { | |
417 | dev_err(dev, "unable to allocate driver data\n"); | |
418 | return -ENOMEM; | |
419 | } | |
420 | ||
421 | /* Offset the main registers to the first register in this bank */ | |
422 | bank->reg = info->priv->reg + info->index * 4; | |
423 | ||
424 | /* Set up GPIO chip */ | |
425 | snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u", | |
426 | info->index); | |
427 | bank->chip.label = bank->label; | |
428 | bank->chip.dev = dev; | |
429 | bank->chip.direction_input = tz1090_gpio_direction_input; | |
430 | bank->chip.direction_output = tz1090_gpio_direction_output; | |
431 | bank->chip.get = tz1090_gpio_get; | |
432 | bank->chip.set = tz1090_gpio_set; | |
433 | bank->chip.free = tz1090_gpio_free; | |
434 | bank->chip.request = tz1090_gpio_request; | |
435 | bank->chip.to_irq = tz1090_gpio_to_irq; | |
436 | bank->chip.of_node = np; | |
437 | ||
438 | /* GPIO numbering from 0 */ | |
439 | bank->chip.base = info->index * 30; | |
440 | bank->chip.ngpio = 30; | |
441 | ||
442 | /* Add the GPIO bank */ | |
443 | gpiochip_add(&bank->chip); | |
444 | ||
445 | /* Get the GPIO bank IRQ if provided */ | |
446 | bank->irq = irq_of_parse_and_map(np, 0); | |
447 | ||
448 | /* The interrupt is optional (it may be used by another core on chip) */ | |
449 | if (bank->irq < 0) { | |
450 | dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n", | |
451 | info->index); | |
452 | return 0; | |
453 | } | |
454 | ||
455 | dev_info(dev, "Setting up IRQs for GPIO bank %u\n", | |
456 | info->index); | |
457 | ||
458 | /* | |
459 | * Initialise all interrupts to disabled so we don't get | |
460 | * spurious ones on a dirty boot and hit the BUG_ON in the | |
461 | * handler. | |
462 | */ | |
463 | tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0); | |
464 | ||
465 | /* Add a virtual IRQ for each GPIO */ | |
466 | bank->domain = irq_domain_add_linear(np, | |
467 | bank->chip.ngpio, | |
04777396 | 468 | &irq_generic_chip_ops, |
9caf1f22 JH |
469 | bank); |
470 | ||
04777396 JH |
471 | /* Set up a generic irq chip with 2 chip types (level and edge) */ |
472 | err = irq_alloc_domain_generic_chips(bank->domain, bank->chip.ngpio, 2, | |
473 | bank->label, handle_bad_irq, 0, 0, | |
474 | IRQ_GC_INIT_NESTED_LOCK); | |
475 | if (err) { | |
476 | dev_info(dev, | |
477 | "irq_alloc_domain_generic_chips failed for bank %u, IRQs disabled\n", | |
478 | info->index); | |
479 | irq_domain_remove(bank->domain); | |
480 | return 0; | |
481 | } | |
482 | ||
483 | gc = irq_get_domain_generic_chip(bank->domain, 0); | |
484 | gc->reg_base = bank->reg; | |
485 | ||
486 | /* level chip type */ | |
487 | gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; | |
488 | gc->chip_types[0].handler = handle_level_irq; | |
489 | gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS; | |
490 | gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN; | |
491 | gc->chip_types[0].chip.irq_startup = gpio_startup_irq, | |
492 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit, | |
493 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit, | |
494 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit, | |
495 | gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type, | |
496 | gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake, | |
497 | gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND, | |
498 | ||
499 | /* edge chip type */ | |
500 | gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; | |
501 | gc->chip_types[1].handler = handle_edge_irq; | |
502 | gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS; | |
503 | gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN; | |
504 | gc->chip_types[1].chip.irq_startup = gpio_startup_irq, | |
505 | gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit, | |
506 | gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit, | |
507 | gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit, | |
508 | gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type, | |
509 | gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake, | |
510 | gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND, | |
511 | ||
9caf1f22 JH |
512 | /* Setup chained handler for this GPIO bank */ |
513 | irq_set_handler_data(bank->irq, bank); | |
514 | irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler); | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
519 | static void tz1090_gpio_register_banks(struct tz1090_gpio *priv) | |
520 | { | |
521 | struct device_node *np = priv->dev->of_node; | |
522 | struct device_node *node; | |
523 | ||
524 | for_each_available_child_of_node(np, node) { | |
525 | struct tz1090_gpio_bank_info info; | |
526 | u32 addr; | |
527 | int ret; | |
528 | ||
529 | ret = of_property_read_u32(node, "reg", &addr); | |
530 | if (ret) { | |
531 | dev_err(priv->dev, "invalid reg on %s\n", | |
532 | node->full_name); | |
533 | continue; | |
534 | } | |
535 | if (addr >= 3) { | |
536 | dev_err(priv->dev, "index %u in %s out of range\n", | |
537 | addr, node->full_name); | |
538 | continue; | |
539 | } | |
540 | ||
541 | info.index = addr; | |
542 | info.node = of_node_get(node); | |
543 | info.priv = priv; | |
544 | ||
545 | ret = tz1090_gpio_bank_probe(&info); | |
546 | if (ret) { | |
547 | dev_err(priv->dev, "failure registering %s\n", | |
548 | node->full_name); | |
549 | of_node_put(node); | |
550 | continue; | |
551 | } | |
552 | } | |
553 | } | |
554 | ||
555 | static int tz1090_gpio_probe(struct platform_device *pdev) | |
556 | { | |
557 | struct device_node *np = pdev->dev.of_node; | |
558 | struct resource *res_regs; | |
559 | struct tz1090_gpio priv; | |
560 | ||
561 | if (!np) { | |
562 | dev_err(&pdev->dev, "must be instantiated via devicetree\n"); | |
563 | return -ENOENT; | |
564 | } | |
565 | ||
566 | res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
567 | if (!res_regs) { | |
568 | dev_err(&pdev->dev, "cannot find registers resource\n"); | |
569 | return -ENOENT; | |
570 | } | |
571 | ||
572 | priv.dev = &pdev->dev; | |
573 | ||
574 | /* Ioremap the registers */ | |
575 | priv.reg = devm_ioremap(&pdev->dev, res_regs->start, | |
576 | res_regs->end - res_regs->start); | |
577 | if (!priv.reg) { | |
578 | dev_err(&pdev->dev, "unable to ioremap registers\n"); | |
579 | return -ENOMEM; | |
580 | } | |
581 | ||
582 | /* Look for banks */ | |
583 | tz1090_gpio_register_banks(&priv); | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | static struct of_device_id tz1090_gpio_of_match[] = { | |
589 | { .compatible = "img,tz1090-gpio" }, | |
590 | { }, | |
591 | }; | |
592 | ||
593 | static struct platform_driver tz1090_gpio_driver = { | |
594 | .driver = { | |
595 | .name = "tz1090-gpio", | |
596 | .owner = THIS_MODULE, | |
597 | .of_match_table = tz1090_gpio_of_match, | |
598 | }, | |
599 | .probe = tz1090_gpio_probe, | |
600 | }; | |
601 | ||
602 | static int __init tz1090_gpio_init(void) | |
603 | { | |
604 | return platform_driver_register(&tz1090_gpio_driver); | |
605 | } | |
606 | subsys_initcall(tz1090_gpio_init); |