[mirror_ubuntu-focal-kernel.git] / drivers / gpio / gpio-vf610.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Freescale vf610 GPIO support through PORT and GPIO
 *
 * Copyright (c) 2014 Toradex AG.
 *
 * Author: Stefan Agner <stefan@agner.ch>.
 */
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>

#define VF610_GPIO_PER_PORT		32

struct fsl_gpio_soc_data {
	/* SoCs has a Port Data Direction Register (PDDR) */
	bool have_paddr;
};

struct vf610_gpio_port {
	struct gpio_chip gc;
	struct irq_chip ic;
	void __iomem *base;
	void __iomem *gpio_base;
	const struct fsl_gpio_soc_data *sdata;
	u8 irqc[VF610_GPIO_PER_PORT];
	struct clk *clk_port;
	struct clk *clk_gpio;
	int irq;
};

#define GPIO_PDOR		0x00
#define GPIO_PSOR		0x04
#define GPIO_PCOR		0x08
#define GPIO_PTOR		0x0c
#define GPIO_PDIR		0x10
#define GPIO_PDDR		0x14

#define PORT_PCR(n)		((n) * 0x4)
#define PORT_PCR_IRQC_OFFSET	16

#define PORT_ISFR		0xa0
#define PORT_DFER		0xc0
#define PORT_DFCR		0xc4
#define PORT_DFWR		0xc8

#define PORT_INT_OFF		0x0
#define PORT_INT_LOGIC_ZERO	0x8
#define PORT_INT_RISING_EDGE	0x9
#define PORT_INT_FALLING_EDGE	0xa
#define PORT_INT_EITHER_EDGE	0xb
#define PORT_INT_LOGIC_ONE	0xc

static const struct fsl_gpio_soc_data imx_data = {
	.have_paddr = true,
};

static const struct of_device_id vf610_gpio_dt_ids[] = {
	{ .compatible = "fsl,vf610-gpio",	.data = NULL, },
	{ .compatible = "fsl,imx7ulp-gpio",	.data = &imx_data, },
	{ /* sentinel */ }
};

static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
{
	writel_relaxed(val, reg);
}

static inline u32 vf610_gpio_readl(void __iomem *reg)
{
	return readl_relaxed(reg);
}

static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	unsigned long mask = BIT(gpio);
	unsigned long offset = GPIO_PDIR;

	if (port->sdata && port->sdata->have_paddr) {
		mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		if (mask)
			offset = GPIO_PDOR;
	}

	return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
}

static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	unsigned long mask = BIT(gpio);
	unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;

	vf610_gpio_writel(mask, port->gpio_base + offset);
}

static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	unsigned long mask = BIT(gpio);
	u32 val;

	if (port->sdata && port->sdata->have_paddr) {
		val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		val &= ~mask;
		vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	}

	return pinctrl_gpio_direction_input(chip->base + gpio);
}

static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
				       int value)
{
	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	unsigned long mask = BIT(gpio);

	if (port->sdata && port->sdata->have_paddr)
		vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);

	vf610_gpio_set(chip, gpio, value);

	return pinctrl_gpio_direction_output(chip->base + gpio);
}

static void vf610_gpio_irq_handler(struct irq_desc *desc)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_desc_get_handler_data(desc));
	struct irq_chip *chip = irq_desc_get_chip(desc);
	int pin;
	unsigned long irq_isfr;

	chained_irq_enter(chip, desc);

	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);

	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
		vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);

		generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
	}

	chained_irq_exit(chip, desc);
}

static void vf610_gpio_irq_ack(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	int gpio = d->hwirq;

	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
}

static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	u8 irqc;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irqc = PORT_INT_RISING_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irqc = PORT_INT_FALLING_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		irqc = PORT_INT_EITHER_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irqc = PORT_INT_LOGIC_ZERO;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irqc = PORT_INT_LOGIC_ONE;
		break;
	default:
		return -EINVAL;
	}

	port->irqc[d->hwirq] = irqc;

	if (type & IRQ_TYPE_LEVEL_MASK)
		irq_set_handler_locked(d, handle_level_irq);
	else
		irq_set_handler_locked(d, handle_edge_irq);

	return 0;
}

static void vf610_gpio_irq_mask(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);

	vf610_gpio_writel(0, pcr_base);
}

static void vf610_gpio_irq_unmask(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);

	vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
			  pcr_base);
}

static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static void vf610_gpio_disable_clk(void *data)
{
	clk_disable_unprepare(data);
}

static int vf610_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct vf610_gpio_port *port;
	struct gpio_chip *gc;
	struct irq_chip *ic;
	int i;
	int ret;

	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->sdata = of_device_get_match_data(dev);
	port->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(port->base))
		return PTR_ERR(port->base);

	port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
	if (IS_ERR(port->gpio_base))
		return PTR_ERR(port->gpio_base);

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	port->clk_port = devm_clk_get(dev, "port");
	ret = PTR_ERR_OR_ZERO(port->clk_port);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_port);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_port);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		/*
		 * Percolate deferrals, for anything else,
		 * just live without the clocking.
		 */
		return ret;
	}

	port->clk_gpio = devm_clk_get(dev, "gpio");
	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_gpio);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_gpio);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		return ret;
	}

	gc = &port->gc;
	gc->of_node = np;
	gc->parent = dev;
	gc->label = "vf610-gpio";
	gc->ngpio = VF610_GPIO_PER_PORT;
	gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;

	gc->request = gpiochip_generic_request;
	gc->free = gpiochip_generic_free;
	gc->direction_input = vf610_gpio_direction_input;
	gc->get = vf610_gpio_get;
	gc->direction_output = vf610_gpio_direction_output;
	gc->set = vf610_gpio_set;

	ic = &port->ic;
	ic->name = "gpio-vf610";
	ic->irq_ack = vf610_gpio_irq_ack;
	ic->irq_mask = vf610_gpio_irq_mask;
	ic->irq_unmask = vf610_gpio_irq_unmask;
	ic->irq_set_type = vf610_gpio_irq_set_type;
	ic->irq_set_wake = vf610_gpio_irq_set_wake;

	ret = devm_gpiochip_add_data(dev, gc, port);
	if (ret < 0)
		return ret;

	/* Mask all GPIO interrupts */
	for (i = 0; i < gc->ngpio; i++)
		vf610_gpio_writel(0, port->base + PORT_PCR(i));

	/* Clear the interrupt status register for all GPIO's */
	vf610_gpio_writel(~0, port->base + PORT_ISFR);

	ret = gpiochip_irqchip_add(gc, ic, 0, handle_edge_irq, IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "failed to add irqchip\n");
		return ret;
	}
	gpiochip_set_chained_irqchip(gc, ic, port->irq,
				     vf610_gpio_irq_handler);

	return 0;
}

static struct platform_driver vf610_gpio_driver = {
	.driver		= {
		.name	= "gpio-vf610",
		.of_match_table = vf610_gpio_dt_ids,
	},
	.probe		= vf610_gpio_probe,
};

builtin_platform_driver(vf610_gpio_driver);
Commit	Line	Data
36e2add1	1	// SPDX-License-Identifier: GPL-2.0+
7f2691a1	2	/*
adaaf63e	3	* Freescale vf610 GPIO support through PORT and GPIO
7f2691a1 SA	4	*
	5	* Copyright (c) 2014 Toradex AG.
	6	*
	7	* Author: Stefan Agner <stefan@agner.ch>.
7f2691a1	8	*/
7f2691a1	9	#include <linux/bitops.h>
91393622	10	#include <linux/clk.h>
7f2691a1	11	#include <linux/err.h>
45e8296c	12	#include <linux/gpio/driver.h>
7f2691a1 SA	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
7f2691a1 SA	18	#include <linux/platform_device.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/of_irq.h>
	22
	23	#define VF610_GPIO_PER_PORT 32
	24
659d8a62 DA	25	struct fsl_gpio_soc_data {
	26	/* SoCs has a Port Data Direction Register (PDDR) */
	27	bool have_paddr;
	28	};
	29
7f2691a1 SA	30	struct vf610_gpio_port {
7f2691a1 SA	31	struct gpio_chip gc;
338aa107	32	struct irq_chip ic;
7f2691a1 SA	33	void __iomem *base;
7f2691a1 SA	34	void __iomem *gpio_base;
659d8a62	35	const struct fsl_gpio_soc_data *sdata;
7f2691a1	36	u8 irqc[VF610_GPIO_PER_PORT];
91393622 D	37	struct clk *clk_port;
91393622 D	38	struct clk *clk_gpio;
7f2691a1 SA	39	int irq;
	40	};
	41
	42	#define GPIO_PDOR 0x00
	43	#define GPIO_PSOR 0x04
	44	#define GPIO_PCOR 0x08
	45	#define GPIO_PTOR 0x0c
	46	#define GPIO_PDIR 0x10
659d8a62	47	#define GPIO_PDDR 0x14
7f2691a1 SA	48
	49	#define PORT_PCR(n) ((n) * 0x4)
	50	#define PORT_PCR_IRQC_OFFSET 16
	51
	52	#define PORT_ISFR 0xa0
	53	#define PORT_DFER 0xc0
	54	#define PORT_DFCR 0xc4
	55	#define PORT_DFWR 0xc8
	56
	57	#define PORT_INT_OFF 0x0
	58	#define PORT_INT_LOGIC_ZERO 0x8
	59	#define PORT_INT_RISING_EDGE 0x9
	60	#define PORT_INT_FALLING_EDGE 0xa
	61	#define PORT_INT_EITHER_EDGE 0xb
	62	#define PORT_INT_LOGIC_ONE 0xc
	63
659d8a62 DA	64	static const struct fsl_gpio_soc_data imx_data = {
	65	.have_paddr = true,
	66	};
	67
7f2691a1	68	static const struct of_device_id vf610_gpio_dt_ids[] = {
659d8a62 DA	69	{ .compatible = "fsl,vf610-gpio", .data = NULL, },
659d8a62 DA	70	{ .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
7f2691a1 SA	71	{ /* sentinel */ }
	72	};
	73
	74	static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
	75	{
	76	writel_relaxed(val, reg);
	77	}
	78
	79	static inline u32 vf610_gpio_readl(void __iomem *reg)
	80	{
	81	return readl_relaxed(reg);
	82	}
	83
7f2691a1 SA	84	static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
7f2691a1 SA	85	{
65389b49	86	struct vf610_gpio_port *port = gpiochip_get_data(gc);
659d8a62	87	unsigned long mask = BIT(gpio);
4a8909d0	88	unsigned long offset = GPIO_PDIR;
659d8a62 DA	89
	90	if (port->sdata && port->sdata->have_paddr) {
	91	mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
4a8909d0 AS	92	if (mask)
4a8909d0 AS	93	offset = GPIO_PDOR;
659d8a62	94	}
4a8909d0 AS	95
4a8909d0 AS	96	return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
7f2691a1 SA	97	}
	98
	99	static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	100	{
65389b49	101	struct vf610_gpio_port *port = gpiochip_get_data(gc);
7f2691a1	102	unsigned long mask = BIT(gpio);
a262555b	103	unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
7f2691a1	104
a262555b	105	vf610_gpio_writel(mask, port->gpio_base + offset);
7f2691a1 SA	106	}
	107
	108	static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
	109	{
659d8a62 DA	110	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	111	unsigned long mask = BIT(gpio);
	112	u32 val;
	113
	114	if (port->sdata && port->sdata->have_paddr) {
	115	val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
	116	val &= ~mask;
	117	vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	118	}
	119
7f2691a1 SA	120	return pinctrl_gpio_direction_input(chip->base + gpio);
	121	}
	122
	123	static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
	124	int value)
	125	{
659d8a62 DA	126	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	127	unsigned long mask = BIT(gpio);
	128
	129	if (port->sdata && port->sdata->have_paddr)
	130	vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);
	131
7f2691a1 SA	132	vf610_gpio_set(chip, gpio, value);
	133
	134	return pinctrl_gpio_direction_output(chip->base + gpio);
	135	}
	136
bd0b9ac4	137	static void vf610_gpio_irq_handler(struct irq_desc *desc)
7f2691a1	138	{
2f930643	139	struct vf610_gpio_port *port =
65389b49	140	gpiochip_get_data(irq_desc_get_handler_data(desc));
7f2691a1 SA	141	struct irq_chip *chip = irq_desc_get_chip(desc);
	142	int pin;
	143	unsigned long irq_isfr;
	144
	145	chained_irq_enter(chip, desc);
	146
	147	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
	148
	149	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
	150	vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
	151
f0fbe7bc	152	generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
7f2691a1 SA	153	}
	154
	155	chained_irq_exit(chip, desc);
	156	}
	157
	158	static void vf610_gpio_irq_ack(struct irq_data *d)
	159	{
2f930643	160	struct vf610_gpio_port *port =
65389b49	161	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	162	int gpio = d->hwirq;
	163
	164	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
	165	}
	166
	167	static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
	168	{
2f930643	169	struct vf610_gpio_port *port =
65389b49	170	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	171	u8 irqc;
	172
	173	switch (type) {
	174	case IRQ_TYPE_EDGE_RISING:
	175	irqc = PORT_INT_RISING_EDGE;
	176	break;
	177	case IRQ_TYPE_EDGE_FALLING:
	178	irqc = PORT_INT_FALLING_EDGE;
	179	break;
	180	case IRQ_TYPE_EDGE_BOTH:
	181	irqc = PORT_INT_EITHER_EDGE;
	182	break;
	183	case IRQ_TYPE_LEVEL_LOW:
	184	irqc = PORT_INT_LOGIC_ZERO;
	185	break;
	186	case IRQ_TYPE_LEVEL_HIGH:
	187	irqc = PORT_INT_LOGIC_ONE;
	188	break;
	189	default:
	190	return -EINVAL;
	191	}
	192
	193	port->irqc[d->hwirq] = irqc;
	194
fd968115	195	if (type & IRQ_TYPE_LEVEL_MASK)
a7147db0	196	irq_set_handler_locked(d, handle_level_irq);
fd968115	197	else
a7147db0	198	irq_set_handler_locked(d, handle_edge_irq);
fd968115	199
7f2691a1 SA	200	return 0;
	201	}
	202
	203	static void vf610_gpio_irq_mask(struct irq_data *d)
	204	{
2f930643	205	struct vf610_gpio_port *port =
65389b49	206	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	207	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
	208
	209	vf610_gpio_writel(0, pcr_base);
	210	}
	211
	212	static void vf610_gpio_irq_unmask(struct irq_data *d)
	213	{
2f930643	214	struct vf610_gpio_port *port =
65389b49	215	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	216	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
	217
	218	vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
	219	pcr_base);
	220	}
	221
	222	static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
	223	{
2f930643	224	struct vf610_gpio_port *port =
65389b49	225	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	226
	227	if (enable)
	228	enable_irq_wake(port->irq);
	229	else
	230	disable_irq_wake(port->irq);
	231
	232	return 0;
	233	}
	234
db9ed63c AS	235	static void vf610_gpio_disable_clk(void *data)
	236	{
	237	clk_disable_unprepare(data);
	238	}
7f2691a1 SA	239
	240	static int vf610_gpio_probe(struct platform_device *pdev)
	241	{
	242	struct device *dev = &pdev->dev;
	243	struct device_node *np = dev->of_node;
	244	struct vf610_gpio_port *port;
7f2691a1	245	struct gpio_chip *gc;
338aa107	246	struct irq_chip *ic;
7ae710f9	247	int i;
7f2691a1 SA	248	int ret;
7f2691a1 SA	249
2e35bb6c	250	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
7f2691a1 SA	251	if (!port)
	252	return -ENOMEM;
	253
23e577eb	254	port->sdata = of_device_get_match_data(dev);
df53665b	255	port->base = devm_platform_ioremap_resource(pdev, 0);
7f2691a1 SA	256	if (IS_ERR(port->base))
	257	return PTR_ERR(port->base);
	258
df53665b	259	port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
7f2691a1 SA	260	if (IS_ERR(port->gpio_base))
	261	return PTR_ERR(port->gpio_base);
	262
	263	port->irq = platform_get_irq(pdev, 0);
	264	if (port->irq < 0)
	265	return port->irq;
	266
2e35bb6c	267	port->clk_port = devm_clk_get(dev, "port");
663ba742 AS	268	ret = PTR_ERR_OR_ZERO(port->clk_port);
663ba742 AS	269	if (!ret) {
91393622 D	270	ret = clk_prepare_enable(port->clk_port);
	271	if (ret)
	272	return ret;
db9ed63c AS	273	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	274	port->clk_port);
	275	if (ret)
	276	return ret;
663ba742	277	} else if (ret == -EPROBE_DEFER) {
91393622 D	278	/*
	279	* Percolate deferrals, for anything else,
	280	* just live without the clocking.
	281	*/
663ba742	282	return ret;
91393622 D	283	}
91393622 D	284
2e35bb6c	285	port->clk_gpio = devm_clk_get(dev, "gpio");
663ba742 AS	286	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
663ba742 AS	287	if (!ret) {
91393622	288	ret = clk_prepare_enable(port->clk_gpio);
db9ed63c	289	if (ret)
91393622	290	return ret;
fc57949c AS	291	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	292	port->clk_gpio);
	293	if (ret)
91393622	294	return ret;
663ba742 AS	295	} else if (ret == -EPROBE_DEFER) {
663ba742 AS	296	return ret;
91393622 D	297	}
91393622 D	298
7f2691a1 SA	299	gc = &port->gc;
7f2691a1 SA	300	gc->of_node = np;
58383c78	301	gc->parent = dev;
d32efe37 AL	302	gc->label = "vf610-gpio";
d32efe37 AL	303	gc->ngpio = VF610_GPIO_PER_PORT;
7f2691a1 SA	304	gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
7f2691a1 SA	305
203f0daa JG	306	gc->request = gpiochip_generic_request;
203f0daa JG	307	gc->free = gpiochip_generic_free;
d32efe37 AL	308	gc->direction_input = vf610_gpio_direction_input;
	309	gc->get = vf610_gpio_get;
	310	gc->direction_output = vf610_gpio_direction_output;
	311	gc->set = vf610_gpio_set;
7f2691a1	312
338aa107 AS	313	ic = &port->ic;
	314	ic->name = "gpio-vf610";
	315	ic->irq_ack = vf610_gpio_irq_ack;
	316	ic->irq_mask = vf610_gpio_irq_mask;
	317	ic->irq_unmask = vf610_gpio_irq_unmask;
	318	ic->irq_set_type = vf610_gpio_irq_set_type;
	319	ic->irq_set_wake = vf610_gpio_irq_set_wake;
	320
a74b4b11	321	ret = devm_gpiochip_add_data(dev, gc, port);
7f2691a1 SA	322	if (ret < 0)
	323	return ret;
	324
7ae710f9 AL	325	/* Mask all GPIO interrupts */
	326	for (i = 0; i < gc->ngpio; i++)
	327	vf610_gpio_writel(0, port->base + PORT_PCR(i));
	328
7f2691a1 SA	329	/* Clear the interrupt status register for all GPIO's */
	330	vf610_gpio_writel(~0, port->base + PORT_ISFR);
	331
338aa107	332	ret = gpiochip_irqchip_add(gc, ic, 0, handle_edge_irq, IRQ_TYPE_NONE);
7f2691a1 SA	333	if (ret) {
7f2691a1 SA	334	dev_err(dev, "failed to add irqchip\n");
7f2691a1 SA	335	return ret;
7f2691a1 SA	336	}
338aa107	337	gpiochip_set_chained_irqchip(gc, ic, port->irq,
7f2691a1 SA	338	vf610_gpio_irq_handler);
	339
	340	return 0;
	341	}
	342
	343	static struct platform_driver vf610_gpio_driver = {
	344	.driver = {
	345	.name = "gpio-vf610",
7f2691a1 SA	346	.of_match_table = vf610_gpio_dt_ids,
	347	},
	348	.probe = vf610_gpio_probe,
	349	};
	350
df950da1	351	builtin_platform_driver(vf610_gpio_driver);