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1 | /* |
2 | * Intel Whiskey Cove PMIC GPIO Driver | |
3 | * | |
4 | * This driver is written based on gpio-crystalcove.c | |
5 | * | |
6 | * Copyright (C) 2016 Intel Corporation. All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License version | |
10 | * 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/bitops.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/gpio/driver.h> | |
21 | #include <linux/mfd/intel_soc_pmic.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/regmap.h> | |
24 | #include <linux/seq_file.h> | |
25 | ||
26 | /* | |
27 | * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks: | |
28 | * Bank 0: Pin 0 - 6 | |
29 | * Bank 1: Pin 7 - 10 | |
30 | * Bank 2: Pin 11 -12 | |
31 | * Each pin has one output control register and one input control register. | |
32 | */ | |
33 | #define BANK0_NR_PINS 7 | |
34 | #define BANK1_NR_PINS 4 | |
35 | #define BANK2_NR_PINS 2 | |
36 | #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS) | |
37 | #define WCOVE_VGPIO_NUM 94 | |
38 | /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */ | |
39 | #define GPIO_OUT_CTRL_BASE 0x4e44 | |
40 | /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */ | |
41 | #define GPIO_IN_CTRL_BASE 0x4e51 | |
42 | ||
43 | /* | |
44 | * GPIO interrupts are organized in two groups: | |
45 | * Group 0: Bank 0 pins (Pin 0 - 6) | |
46 | * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12) | |
47 | * Each group has two registers (one bit per pin): status and mask. | |
48 | */ | |
49 | #define GROUP0_NR_IRQS 7 | |
50 | #define GROUP1_NR_IRQS 6 | |
51 | #define IRQ_MASK_BASE 0x4e19 | |
52 | #define IRQ_STATUS_BASE 0x4e0b | |
53 | #define UPDATE_IRQ_TYPE BIT(0) | |
54 | #define UPDATE_IRQ_MASK BIT(1) | |
55 | ||
56 | #define CTLI_INTCNT_DIS (0 << 1) | |
57 | #define CTLI_INTCNT_NE (1 << 1) | |
58 | #define CTLI_INTCNT_PE (2 << 1) | |
59 | #define CTLI_INTCNT_BE (3 << 1) | |
60 | ||
61 | #define CTLO_DIR_IN (0 << 5) | |
62 | #define CTLO_DIR_OUT (1 << 5) | |
63 | ||
64 | #define CTLO_DRV_MASK (1 << 4) | |
65 | #define CTLO_DRV_OD (0 << 4) | |
66 | #define CTLO_DRV_CMOS (1 << 4) | |
67 | ||
68 | #define CTLO_DRV_REN (1 << 3) | |
69 | ||
70 | #define CTLO_RVAL_2KDOWN (0 << 1) | |
71 | #define CTLO_RVAL_2KUP (1 << 1) | |
72 | #define CTLO_RVAL_50KDOWN (2 << 1) | |
73 | #define CTLO_RVAL_50KUP (3 << 1) | |
74 | ||
75 | #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP) | |
76 | #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET) | |
77 | ||
78 | enum ctrl_register { | |
79 | CTRL_IN, | |
80 | CTRL_OUT, | |
81 | }; | |
82 | ||
83 | /* | |
84 | * struct wcove_gpio - Whiskey Cove GPIO controller | |
85 | * @buslock: for bus lock/sync and unlock. | |
86 | * @chip: the abstract gpio_chip structure. | |
87 | * @dev: the gpio device | |
88 | * @regmap: the regmap from the parent device. | |
89 | * @regmap_irq_chip: the regmap of the gpio irq chip. | |
90 | * @update: pending IRQ setting update, to be written to the chip upon unlock. | |
91 | * @intcnt: the Interrupt Detect value to be written. | |
92 | * @set_irq_mask: true if the IRQ mask needs to be set, false to clear. | |
93 | */ | |
94 | struct wcove_gpio { | |
95 | struct mutex buslock; | |
96 | struct gpio_chip chip; | |
97 | struct device *dev; | |
98 | struct regmap *regmap; | |
99 | struct regmap_irq_chip_data *regmap_irq_chip; | |
100 | int update; | |
101 | int intcnt; | |
102 | bool set_irq_mask; | |
103 | }; | |
104 | ||
105 | static inline unsigned int to_reg(int gpio, enum ctrl_register reg_type) | |
106 | { | |
107 | unsigned int reg; | |
108 | int bank; | |
109 | ||
110 | if (gpio < BANK0_NR_PINS) | |
111 | bank = 0; | |
112 | else if (gpio < BANK0_NR_PINS + BANK1_NR_PINS) | |
113 | bank = 1; | |
114 | else | |
115 | bank = 2; | |
116 | ||
117 | if (reg_type == CTRL_IN) | |
118 | reg = GPIO_IN_CTRL_BASE + bank; | |
119 | else | |
120 | reg = GPIO_OUT_CTRL_BASE + bank; | |
121 | ||
122 | return reg; | |
123 | } | |
124 | ||
125 | static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio) | |
126 | { | |
127 | unsigned int reg, mask; | |
128 | ||
129 | if (gpio < GROUP0_NR_IRQS) { | |
130 | reg = IRQ_MASK_BASE; | |
131 | mask = BIT(gpio % GROUP0_NR_IRQS); | |
132 | } else { | |
133 | reg = IRQ_MASK_BASE + 1; | |
134 | mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS); | |
135 | } | |
136 | ||
137 | if (wg->set_irq_mask) | |
138 | regmap_update_bits(wg->regmap, reg, mask, mask); | |
139 | else | |
140 | regmap_update_bits(wg->regmap, reg, mask, 0); | |
141 | } | |
142 | ||
143 | static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio) | |
144 | { | |
145 | unsigned int reg = to_reg(gpio, CTRL_IN); | |
146 | ||
147 | regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); | |
148 | } | |
149 | ||
150 | static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) | |
151 | { | |
152 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
153 | ||
154 | return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT), | |
155 | CTLO_INPUT_SET); | |
156 | } | |
157 | ||
158 | static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, | |
159 | int value) | |
160 | { | |
161 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
162 | ||
163 | return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT), | |
164 | CTLO_OUTPUT_SET | value); | |
165 | } | |
166 | ||
167 | static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) | |
168 | { | |
169 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
170 | unsigned int val; | |
171 | int ret; | |
172 | ||
173 | ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &val); | |
174 | if (ret) | |
175 | return ret; | |
176 | ||
177 | return val & 0x1; | |
178 | } | |
179 | ||
180 | static void wcove_gpio_set(struct gpio_chip *chip, | |
181 | unsigned int gpio, int value) | |
182 | { | |
183 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
184 | ||
185 | if (value) | |
186 | regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 1); | |
187 | else | |
188 | regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 0); | |
189 | } | |
190 | ||
191 | static int wcove_gpio_set_single_ended(struct gpio_chip *chip, | |
192 | unsigned int gpio, | |
193 | enum single_ended_mode mode) | |
194 | { | |
195 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
196 | ||
197 | switch (mode) { | |
198 | case LINE_MODE_OPEN_DRAIN: | |
199 | return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), | |
200 | CTLO_DRV_MASK, CTLO_DRV_OD); | |
201 | case LINE_MODE_PUSH_PULL: | |
202 | return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), | |
203 | CTLO_DRV_MASK, CTLO_DRV_CMOS); | |
204 | default: | |
205 | break; | |
206 | } | |
207 | ||
208 | return -ENOTSUPP; | |
209 | } | |
210 | ||
211 | static int wcove_irq_type(struct irq_data *data, unsigned int type) | |
212 | { | |
213 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
214 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
215 | ||
216 | switch (type) { | |
217 | case IRQ_TYPE_NONE: | |
218 | wg->intcnt = CTLI_INTCNT_DIS; | |
219 | break; | |
220 | case IRQ_TYPE_EDGE_BOTH: | |
221 | wg->intcnt = CTLI_INTCNT_BE; | |
222 | break; | |
223 | case IRQ_TYPE_EDGE_RISING: | |
224 | wg->intcnt = CTLI_INTCNT_PE; | |
225 | break; | |
226 | case IRQ_TYPE_EDGE_FALLING: | |
227 | wg->intcnt = CTLI_INTCNT_NE; | |
228 | break; | |
229 | default: | |
230 | return -EINVAL; | |
231 | } | |
232 | ||
233 | wg->update |= UPDATE_IRQ_TYPE; | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | static void wcove_bus_lock(struct irq_data *data) | |
239 | { | |
240 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
241 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
242 | ||
243 | mutex_lock(&wg->buslock); | |
244 | } | |
245 | ||
246 | static void wcove_bus_sync_unlock(struct irq_data *data) | |
247 | { | |
248 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
249 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
250 | int gpio = data->hwirq; | |
251 | ||
252 | if (wg->update & UPDATE_IRQ_TYPE) | |
253 | wcove_update_irq_ctrl(wg, gpio); | |
254 | if (wg->update & UPDATE_IRQ_MASK) | |
255 | wcove_update_irq_mask(wg, gpio); | |
256 | wg->update = 0; | |
257 | ||
258 | mutex_unlock(&wg->buslock); | |
259 | } | |
260 | ||
261 | static void wcove_irq_unmask(struct irq_data *data) | |
262 | { | |
263 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
264 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
265 | ||
266 | wg->set_irq_mask = false; | |
267 | wg->update |= UPDATE_IRQ_MASK; | |
268 | } | |
269 | ||
270 | static void wcove_irq_mask(struct irq_data *data) | |
271 | { | |
272 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
273 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
274 | ||
275 | wg->set_irq_mask = true; | |
276 | wg->update |= UPDATE_IRQ_MASK; | |
277 | } | |
278 | ||
279 | static struct irq_chip wcove_irqchip = { | |
280 | .name = "Whiskey Cove", | |
281 | .irq_mask = wcove_irq_mask, | |
282 | .irq_unmask = wcove_irq_unmask, | |
283 | .irq_set_type = wcove_irq_type, | |
284 | .irq_bus_lock = wcove_bus_lock, | |
285 | .irq_bus_sync_unlock = wcove_bus_sync_unlock, | |
286 | }; | |
287 | ||
288 | static irqreturn_t wcove_gpio_irq_handler(int irq, void *data) | |
289 | { | |
290 | struct wcove_gpio *wg = (struct wcove_gpio *)data; | |
291 | unsigned int pending, virq, gpio, mask, offset; | |
292 | u8 p[2]; | |
293 | ||
294 | if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { | |
295 | dev_err(wg->dev, "Failed to read irq status register\n"); | |
296 | return IRQ_NONE; | |
297 | } | |
298 | ||
299 | pending = p[0] | (p[1] << 8); | |
300 | if (!pending) | |
301 | return IRQ_NONE; | |
302 | ||
303 | /* Iterate until no interrupt is pending */ | |
304 | while (pending) { | |
305 | /* One iteration is for all pending bits */ | |
306 | for_each_set_bit(gpio, (const unsigned long *)&pending, | |
307 | GROUP0_NR_IRQS) { | |
308 | offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0; | |
309 | mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) : | |
310 | BIT(gpio); | |
311 | virq = irq_find_mapping(wg->chip.irqdomain, gpio); | |
312 | handle_nested_irq(virq); | |
313 | regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset, | |
314 | mask, mask); | |
315 | } | |
316 | ||
317 | /* Next iteration */ | |
318 | if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { | |
319 | dev_err(wg->dev, "Failed to read irq status\n"); | |
320 | break; | |
321 | } | |
322 | ||
323 | pending = p[0] | (p[1] << 8); | |
324 | } | |
325 | ||
326 | return IRQ_HANDLED; | |
327 | } | |
328 | ||
329 | static void wcove_gpio_dbg_show(struct seq_file *s, | |
330 | struct gpio_chip *chip) | |
331 | { | |
332 | unsigned int ctlo, ctli, irq_mask, irq_status; | |
333 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
334 | int gpio, offset, group, ret = 0; | |
335 | ||
336 | for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) { | |
337 | group = gpio < GROUP0_NR_IRQS ? 0 : 1; | |
338 | ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); | |
339 | ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); | |
340 | ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group, | |
341 | &irq_mask); | |
342 | ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group, | |
343 | &irq_status); | |
344 | if (ret) { | |
345 | pr_err("Failed to read registers: ctrl out/in or irq status/mask\n"); | |
346 | break; | |
347 | } | |
348 | ||
349 | offset = gpio % 8; | |
350 | seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n", | |
351 | gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", | |
352 | ctli & 0x1 ? "hi" : "lo", | |
353 | ctli & CTLI_INTCNT_NE ? "fall" : " ", | |
354 | ctli & CTLI_INTCNT_PE ? "rise" : " ", | |
355 | ctlo, | |
356 | irq_mask & BIT(offset) ? "mask " : "unmask", | |
357 | irq_status & BIT(offset) ? "pending" : " "); | |
358 | } | |
359 | } | |
360 | ||
361 | static int wcove_gpio_probe(struct platform_device *pdev) | |
362 | { | |
363 | struct intel_soc_pmic *pmic; | |
364 | struct wcove_gpio *wg; | |
365 | int virq, ret, irq; | |
366 | struct device *dev; | |
367 | ||
368 | /* | |
369 | * This gpio platform device is created by a mfd device (see | |
370 | * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information | |
371 | * shared by all sub-devices created by the mfd device, the regmap | |
372 | * pointer for instance, is stored as driver data of the mfd device | |
373 | * driver. | |
374 | */ | |
375 | pmic = dev_get_drvdata(pdev->dev.parent); | |
376 | if (!pmic) | |
377 | return -ENODEV; | |
378 | ||
379 | irq = platform_get_irq(pdev, 0); | |
380 | if (irq < 0) | |
381 | return irq; | |
382 | ||
383 | dev = &pdev->dev; | |
384 | ||
385 | wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL); | |
386 | if (!wg) | |
387 | return -ENOMEM; | |
388 | ||
389 | wg->regmap_irq_chip = pmic->irq_chip_data_level2; | |
390 | ||
391 | platform_set_drvdata(pdev, wg); | |
392 | ||
393 | mutex_init(&wg->buslock); | |
394 | wg->chip.label = KBUILD_MODNAME; | |
395 | wg->chip.direction_input = wcove_gpio_dir_in; | |
396 | wg->chip.direction_output = wcove_gpio_dir_out; | |
397 | wg->chip.get = wcove_gpio_get; | |
398 | wg->chip.set = wcove_gpio_set; | |
399 | wg->chip.set_single_ended = wcove_gpio_set_single_ended, | |
400 | wg->chip.base = -1; | |
401 | wg->chip.ngpio = WCOVE_VGPIO_NUM; | |
402 | wg->chip.can_sleep = true; | |
403 | wg->chip.parent = pdev->dev.parent; | |
404 | wg->chip.dbg_show = wcove_gpio_dbg_show; | |
405 | wg->dev = dev; | |
406 | wg->regmap = pmic->regmap; | |
407 | ||
408 | ret = devm_gpiochip_add_data(dev, &wg->chip, wg); | |
409 | if (ret) { | |
410 | dev_err(dev, "Failed to add gpiochip: %d\n", ret); | |
411 | return ret; | |
412 | } | |
413 | ||
414 | ret = gpiochip_irqchip_add(&wg->chip, &wcove_irqchip, 0, | |
415 | handle_simple_irq, IRQ_TYPE_NONE); | |
416 | if (ret) { | |
417 | dev_err(dev, "Failed to add irqchip: %d\n", ret); | |
418 | return ret; | |
419 | } | |
420 | ||
421 | virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq); | |
422 | if (virq < 0) { | |
423 | dev_err(dev, "Failed to get virq by irq %d\n", irq); | |
424 | return virq; | |
425 | } | |
426 | ||
427 | ret = devm_request_threaded_irq(dev, virq, NULL, | |
428 | wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg); | |
429 | if (ret) { | |
430 | dev_err(dev, "Failed to request irq %d\n", virq); | |
431 | return ret; | |
432 | } | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | /* | |
438 | * Whiskey Cove PMIC itself is a analog device(but with digital control | |
439 | * interface) providing power management support for other devices in | |
440 | * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver. | |
441 | */ | |
442 | static struct platform_driver wcove_gpio_driver = { | |
443 | .driver = { | |
444 | .name = "bxt_wcove_gpio", | |
445 | }, | |
446 | .probe = wcove_gpio_probe, | |
447 | }; | |
448 | ||
449 | module_platform_driver(wcove_gpio_driver); | |
450 | ||
451 | MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>"); | |
452 | MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>"); | |
453 | MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver"); | |
454 | MODULE_LICENSE("GPL v2"); | |
455 | MODULE_ALIAS("platform:bxt_wcove_gpio"); |