[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-xilinx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Xilinx gpio driver for xps/axi_gpio IP.
 *
 * Copyright 2008 - 2013 Xilinx, Inc.
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/slab.h>

/* Register Offset Definitions */
#define XGPIO_DATA_OFFSET   (0x0)	/* Data register  */
#define XGPIO_TRI_OFFSET    (0x4)	/* I/O direction register  */

#define XGPIO_CHANNEL_OFFSET	0x8

/* Read/Write access to the GPIO registers */
#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
# define xgpio_readreg(offset)		readl(offset)
# define xgpio_writereg(offset, val)	writel(val, offset)
#else
# define xgpio_readreg(offset)		__raw_readl(offset)
# define xgpio_writereg(offset, val)	__raw_writel(val, offset)
#endif

/**
 * struct xgpio_instance - Stores information about GPIO device
 * @gc: GPIO chip
 * @regs: register block
 * @gpio_width: GPIO width for every channel
 * @gpio_state: GPIO state shadow register
 * @gpio_dir: GPIO direction shadow register
 * @gpio_lock: Lock used for synchronization
 * @clk: clock resource for this driver
 */
struct xgpio_instance {
	struct gpio_chip gc;
	void __iomem *regs;
	unsigned int gpio_width[2];
	u32 gpio_state[2];
	u32 gpio_dir[2];
	spinlock_t gpio_lock[2];
	struct clk *clk;
};

static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
{
	if (gpio >= chip->gpio_width[0])
		return 1;

	return 0;
}

static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio)
{
	if (xgpio_index(chip, gpio))
		return XGPIO_CHANNEL_OFFSET;

	return 0;
}

static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
{
	if (xgpio_index(chip, gpio))
		return gpio - chip->gpio_width[0];

	return gpio;
}

/**
 * xgpio_get - Read the specified signal of the GPIO device.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 *
 * This function reads the specified signal of the GPIO device.
 *
 * Return:
 * 0 if direction of GPIO signals is set as input otherwise it
 * returns negative error value.
 */
static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	u32 val;

	val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET +
			    xgpio_regoffset(chip, gpio));

	return !!(val & BIT(xgpio_offset(chip, gpio)));
}

/**
 * xgpio_set - Write the specified signal of the GPIO device.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * This function writes the specified value in to the specified signal of the
 * GPIO device.
 */
static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	unsigned long flags;
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	int index =  xgpio_index(chip, gpio);
	int offset =  xgpio_offset(chip, gpio);

	spin_lock_irqsave(&chip->gpio_lock[index], flags);

	/* Write to GPIO signal and set its direction to output */
	if (val)
		chip->gpio_state[index] |= BIT(offset);
	else
		chip->gpio_state[index] &= ~BIT(offset);

	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
		       xgpio_regoffset(chip, gpio), chip->gpio_state[index]);

	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
}

/**
 * xgpio_set_multiple - Write the specified signals of the GPIO device.
 * @gc:     Pointer to gpio_chip device structure.
 * @mask:   Mask of the GPIOS to modify.
 * @bits:   Value to be wrote on each GPIO
 *
 * This function writes the specified values into the specified signals of the
 * GPIO devices.
 */
static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
			       unsigned long *bits)
{
	unsigned long flags;
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	int index = xgpio_index(chip, 0);
	int offset, i;

	spin_lock_irqsave(&chip->gpio_lock[index], flags);

	/* Write to GPIO signals */
	for (i = 0; i < gc->ngpio; i++) {
		if (*mask == 0)
			break;
		/* Once finished with an index write it out to the register */
		if (index !=  xgpio_index(chip, i)) {
			xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
				       index * XGPIO_CHANNEL_OFFSET,
				       chip->gpio_state[index]);
			spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
			index =  xgpio_index(chip, i);
			spin_lock_irqsave(&chip->gpio_lock[index], flags);
		}
		if (__test_and_clear_bit(i, mask)) {
			offset =  xgpio_offset(chip, i);
			if (test_bit(i, bits))
				chip->gpio_state[index] |= BIT(offset);
			else
				chip->gpio_state[index] &= ~BIT(offset);
		}
	}

	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
		       index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]);

	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
}

/**
 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 *
 * Return:
 * 0 - if direction of GPIO signals is set as input
 * otherwise it returns negative error value.
 */
static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	unsigned long flags;
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	int index =  xgpio_index(chip, gpio);
	int offset =  xgpio_offset(chip, gpio);

	spin_lock_irqsave(&chip->gpio_lock[index], flags);

	/* Set the GPIO bit in shadow register and set direction as input */
	chip->gpio_dir[index] |= BIT(offset);
	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
		       xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);

	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);

	return 0;
}

/**
 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * This function sets the direction of specified GPIO signal as output.
 *
 * Return:
 * If all GPIO signals of GPIO chip is configured as input then it returns
 * error otherwise it returns 0.
 */
static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	unsigned long flags;
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	int index =  xgpio_index(chip, gpio);
	int offset =  xgpio_offset(chip, gpio);

	spin_lock_irqsave(&chip->gpio_lock[index], flags);

	/* Write state of GPIO signal */
	if (val)
		chip->gpio_state[index] |= BIT(offset);
	else
		chip->gpio_state[index] &= ~BIT(offset);
	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
			xgpio_regoffset(chip, gpio), chip->gpio_state[index]);

	/* Clear the GPIO bit in shadow register and set direction as output */
	chip->gpio_dir[index] &= ~BIT(offset);
	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
			xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);

	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);

	return 0;
}

/**
 * xgpio_save_regs - Set initial values of GPIO pins
 * @chip: Pointer to GPIO instance
 */
static void xgpio_save_regs(struct xgpio_instance *chip)
{
	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET,	chip->gpio_state[0]);
	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);

	if (!chip->gpio_width[1])
		return;

	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
		       chip->gpio_state[1]);
	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
		       chip->gpio_dir[1]);
}

/**
 * xgpio_remove - Remove method for the GPIO device.
 * @pdev: pointer to the platform device
 *
 * This function remove gpiochips and frees all the allocated resources.
 *
 * Return: 0 always
 */
static int xgpio_remove(struct platform_device *pdev)
{
	struct xgpio_instance *gpio = platform_get_drvdata(pdev);

	clk_disable_unprepare(gpio->clk);

	return 0;
}

/**
 * xgpio_of_probe - Probe method for the GPIO device.
 * @pdev: pointer to the platform device
 *
 * Return:
 * It returns 0, if the driver is bound to the GPIO device, or
 * a negative value if there is an error.
 */
static int xgpio_probe(struct platform_device *pdev)
{
	struct xgpio_instance *chip;
	int status = 0;
	struct device_node *np = pdev->dev.of_node;
	u32 is_dual;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	platform_set_drvdata(pdev, chip);

	/* Update GPIO state shadow register with default value */
	if (of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]))
		chip->gpio_state[0] = 0x0;

	/* Update GPIO direction shadow register with default value */
	if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
		chip->gpio_dir[0] = 0xFFFFFFFF;

	/*
	 * Check device node and parent device node for device width
	 * and assume default width of 32
	 */
	if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
		chip->gpio_width[0] = 32;

	spin_lock_init(&chip->gpio_lock[0]);

	if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
		is_dual = 0;

	if (is_dual) {
		/* Update GPIO state shadow register with default value */
		if (of_property_read_u32(np, "xlnx,dout-default-2",
					 &chip->gpio_state[1]))
			chip->gpio_state[1] = 0x0;

		/* Update GPIO direction shadow register with default value */
		if (of_property_read_u32(np, "xlnx,tri-default-2",
					 &chip->gpio_dir[1]))
			chip->gpio_dir[1] = 0xFFFFFFFF;

		/*
		 * Check device node and parent device node for device width
		 * and assume default width of 32
		 */
		if (of_property_read_u32(np, "xlnx,gpio2-width",
					 &chip->gpio_width[1]))
			chip->gpio_width[1] = 32;

		spin_lock_init(&chip->gpio_lock[1]);
	}

	chip->gc.base = -1;
	chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
	chip->gc.parent = &pdev->dev;
	chip->gc.direction_input = xgpio_dir_in;
	chip->gc.direction_output = xgpio_dir_out;
	chip->gc.get = xgpio_get;
	chip->gc.set = xgpio_set;
	chip->gc.set_multiple = xgpio_set_multiple;

	chip->gc.label = dev_name(&pdev->dev);

	chip->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(chip->regs)) {
		dev_err(&pdev->dev, "failed to ioremap memory resource\n");
		return PTR_ERR(chip->regs);
	}

	chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
	if (IS_ERR(chip->clk)) {
		if (PTR_ERR(chip->clk) != -EPROBE_DEFER)
			dev_dbg(&pdev->dev, "Input clock not found\n");
		return PTR_ERR(chip->clk);
	}

	status = clk_prepare_enable(chip->clk);
	if (status < 0) {
		dev_err(&pdev->dev, "Failed to prepare clk\n");
		return status;
	}

	xgpio_save_regs(chip);

	status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
	if (status) {
		dev_err(&pdev->dev, "failed to add GPIO chip\n");
		clk_disable_unprepare(chip->clk);
		return status;
	}

	return 0;
}

static const struct of_device_id xgpio_of_match[] = {
	{ .compatible = "xlnx,xps-gpio-1.00.a", },
	{ /* end of list */ },
};

MODULE_DEVICE_TABLE(of, xgpio_of_match);

static struct platform_driver xgpio_plat_driver = {
	.probe		= xgpio_probe,
	.remove		= xgpio_remove,
	.driver		= {
			.name = "gpio-xilinx",
			.of_match_table	= xgpio_of_match,
	},
};

static int __init xgpio_init(void)
{
	return platform_driver_register(&xgpio_plat_driver);
}

subsys_initcall(xgpio_init);

static void __exit xgpio_exit(void)
{
	platform_driver_unregister(&xgpio_plat_driver);
}
module_exit(xgpio_exit);

MODULE_AUTHOR("Xilinx, Inc.");
MODULE_DESCRIPTION("Xilinx GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
6e75fc04	1	// SPDX-License-Identifier: GPL-2.0-only
0bcb6069	2	/*
74600ee0	3	* Xilinx gpio driver for xps/axi_gpio IP.
0bcb6069	4	*
74600ee0	5	* Copyright 2008 - 2013 Xilinx, Inc.
0bcb6069 JL	6	*/
0bcb6069 JL	7
74600ee0	8	#include <linux/bitops.h>
65bbe531	9	#include <linux/clk.h>
0bcb6069	10	#include <linux/errno.h>
8c669fe6 SN	11	#include <linux/gpio/driver.h>
	12	#include <linux/init.h>
	13	#include <linux/io.h>
bb207ef1	14	#include <linux/module.h>
0bcb6069 JL	15	#include <linux/of_device.h>
0bcb6069 JL	16	#include <linux/of_platform.h>
5a0e3ad6	17	#include <linux/slab.h>
0bcb6069 JL	18
	19	/* Register Offset Definitions */
	20	#define XGPIO_DATA_OFFSET (0x0) /* Data register */
	21	#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
	22
74600ee0 MS	23	#define XGPIO_CHANNEL_OFFSET 0x8
	24
	25	/* Read/Write access to the GPIO registers */
c54c58ba	26	#if defined(CONFIG_ARCH_ZYNQ) \|\| defined(CONFIG_X86)
cc090d61 MS	27	# define xgpio_readreg(offset) readl(offset)
	28	# define xgpio_writereg(offset, val) writel(val, offset)
	29	#else
	30	# define xgpio_readreg(offset) __raw_readl(offset)
	31	# define xgpio_writereg(offset, val) __raw_writel(val, offset)
	32	#endif
74600ee0 MS	33
	34	/**
	35	* struct xgpio_instance - Stores information about GPIO device
1ebd0687 RH	36	* @gc: GPIO chip
1ebd0687 RH	37	* @regs: register block
3c1b5c9b	38	* @gpio_width: GPIO width for every channel
4ae798fa RR	39	* @gpio_state: GPIO state shadow register
	40	* @gpio_dir: GPIO direction shadow register
	41	* @gpio_lock: Lock used for synchronization
65bbe531	42	* @clk: clock resource for this driver
74600ee0	43	*/
0bcb6069	44	struct xgpio_instance {
1ebd0687 RH	45	struct gpio_chip gc;
1ebd0687 RH	46	void __iomem *regs;
1d6902d3 RR	47	unsigned int gpio_width[2];
	48	u32 gpio_state[2];
	49	u32 gpio_dir[2];
	50	spinlock_t gpio_lock[2];
65bbe531	51	struct clk *clk;
749564ff RR	52	};
749564ff RR	53
1d6902d3 RR	54	static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
	55	{
	56	if (gpio >= chip->gpio_width[0])
	57	return 1;
	58
	59	return 0;
	60	}
	61
	62	static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio)
	63	{
	64	if (xgpio_index(chip, gpio))
	65	return XGPIO_CHANNEL_OFFSET;
	66
	67	return 0;
	68	}
	69
	70	static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
	71	{
	72	if (xgpio_index(chip, gpio))
	73	return gpio - chip->gpio_width[0];
	74
	75	return gpio;
	76	}
0bcb6069 JL	77
	78	/**
	79	* xgpio_get - Read the specified signal of the GPIO device.
	80	* @gc: Pointer to gpio_chip device structure.
	81	* @gpio: GPIO signal number.
	82	*
4ae798fa RR	83	* This function reads the specified signal of the GPIO device.
	84	*
	85	* Return:
	86	* 0 if direction of GPIO signals is set as input otherwise it
	87	* returns negative error value.
0bcb6069 JL	88	*/
	89	static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
	90	{
097d88e9	91	struct xgpio_instance *chip = gpiochip_get_data(gc);
1d6902d3	92	u32 val;
0bcb6069	93
1ebd0687	94	val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET +
1d6902d3 RR	95	xgpio_regoffset(chip, gpio));
	96
	97	return !!(val & BIT(xgpio_offset(chip, gpio)));
0bcb6069 JL	98	}
	99
	100	/**
	101	* xgpio_set - Write the specified signal of the GPIO device.
	102	* @gc: Pointer to gpio_chip device structure.
	103	* @gpio: GPIO signal number.
	104	* @val: Value to be written to specified signal.
	105	*
	106	* This function writes the specified value in to the specified signal of the
	107	* GPIO device.
	108	*/
	109	static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	110	{
	111	unsigned long flags;
097d88e9	112	struct xgpio_instance *chip = gpiochip_get_data(gc);
1d6902d3 RR	113	int index = xgpio_index(chip, gpio);
1d6902d3 RR	114	int offset = xgpio_offset(chip, gpio);
0bcb6069	115
1d6902d3	116	spin_lock_irqsave(&chip->gpio_lock[index], flags);
0bcb6069 JL	117
	118	/* Write to GPIO signal and set its direction to output */
	119	if (val)
1d6902d3	120	chip->gpio_state[index] \|= BIT(offset);
0bcb6069	121	else
1d6902d3	122	chip->gpio_state[index] &= ~BIT(offset);
74600ee0	123
1ebd0687	124	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
1d6902d3	125	xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
0bcb6069	126
1d6902d3	127	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
0bcb6069 JL	128	}
0bcb6069 JL	129
8e7c1b80 IR	130	/**
	131	* xgpio_set_multiple - Write the specified signals of the GPIO device.
	132	* @gc: Pointer to gpio_chip device structure.
	133	* @mask: Mask of the GPIOS to modify.
	134	* @bits: Value to be wrote on each GPIO
	135	*
	136	* This function writes the specified values into the specified signals of the
	137	* GPIO devices.
	138	*/
	139	static void xgpio_set_multiple(struct gpio_chip gc, unsigned long mask,
	140	unsigned long *bits)
	141	{
	142	unsigned long flags;
8e7c1b80 IR	143	struct xgpio_instance *chip = gpiochip_get_data(gc);
	144	int index = xgpio_index(chip, 0);
	145	int offset, i;
	146
	147	spin_lock_irqsave(&chip->gpio_lock[index], flags);
	148
	149	/* Write to GPIO signals */
	150	for (i = 0; i < gc->ngpio; i++) {
	151	if (*mask == 0)
	152	break;
c3afa804	153	/* Once finished with an index write it out to the register */
8e7c1b80	154	if (index != xgpio_index(chip, i)) {
1ebd0687	155	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
c3afa804	156	index * XGPIO_CHANNEL_OFFSET,
8e7c1b80 IR	157	chip->gpio_state[index]);
	158	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
	159	index = xgpio_index(chip, i);
	160	spin_lock_irqsave(&chip->gpio_lock[index], flags);
	161	}
	162	if (__test_and_clear_bit(i, mask)) {
	163	offset = xgpio_offset(chip, i);
	164	if (test_bit(i, bits))
	165	chip->gpio_state[index] \|= BIT(offset);
	166	else
	167	chip->gpio_state[index] &= ~BIT(offset);
	168	}
	169	}
	170
1ebd0687	171	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
c3afa804	172	index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]);
8e7c1b80 IR	173
	174	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
	175	}
	176
0bcb6069 JL	177	/**
	178	* xgpio_dir_in - Set the direction of the specified GPIO signal as input.
	179	* @gc: Pointer to gpio_chip device structure.
	180	* @gpio: GPIO signal number.
	181	*
4ae798fa RR	182	* Return:
	183	* 0 - if direction of GPIO signals is set as input
	184	* otherwise it returns negative error value.
0bcb6069 JL	185	*/
	186	static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	187	{
	188	unsigned long flags;
097d88e9	189	struct xgpio_instance *chip = gpiochip_get_data(gc);
1d6902d3 RR	190	int index = xgpio_index(chip, gpio);
1d6902d3 RR	191	int offset = xgpio_offset(chip, gpio);
0bcb6069	192
1d6902d3	193	spin_lock_irqsave(&chip->gpio_lock[index], flags);
0bcb6069 JL	194
0bcb6069 JL	195	/* Set the GPIO bit in shadow register and set direction as input */
1d6902d3	196	chip->gpio_dir[index] \|= BIT(offset);
1ebd0687	197	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
1d6902d3	198	xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
0bcb6069	199
1d6902d3	200	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
0bcb6069 JL	201
	202	return 0;
	203	}
	204
	205	/**
	206	* xgpio_dir_out - Set the direction of the specified GPIO signal as output.
	207	* @gc: Pointer to gpio_chip device structure.
	208	* @gpio: GPIO signal number.
	209	* @val: Value to be written to specified signal.
	210	*
4ae798fa RR	211	* This function sets the direction of specified GPIO signal as output.
	212	*
	213	* Return:
	214	* If all GPIO signals of GPIO chip is configured as input then it returns
0bcb6069 JL	215	* error otherwise it returns 0.
	216	*/
	217	static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	218	{
	219	unsigned long flags;
097d88e9	220	struct xgpio_instance *chip = gpiochip_get_data(gc);
1d6902d3 RR	221	int index = xgpio_index(chip, gpio);
1d6902d3 RR	222	int offset = xgpio_offset(chip, gpio);
0bcb6069	223
1d6902d3	224	spin_lock_irqsave(&chip->gpio_lock[index], flags);
0bcb6069 JL	225
	226	/* Write state of GPIO signal */
	227	if (val)
1d6902d3	228	chip->gpio_state[index] \|= BIT(offset);
0bcb6069	229	else
1d6902d3	230	chip->gpio_state[index] &= ~BIT(offset);
1ebd0687	231	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
1d6902d3	232	xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
0bcb6069 JL	233
0bcb6069 JL	234	/* Clear the GPIO bit in shadow register and set direction as output */
1d6902d3	235	chip->gpio_dir[index] &= ~BIT(offset);
1ebd0687	236	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
1d6902d3	237	xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
0bcb6069	238
1d6902d3	239	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
0bcb6069 JL	240
	241	return 0;
	242	}
	243
	244	/**
	245	* xgpio_save_regs - Set initial values of GPIO pins
1ebd0687	246	* @chip: Pointer to GPIO instance
0bcb6069	247	*/
1ebd0687	248	static void xgpio_save_regs(struct xgpio_instance *chip)
0bcb6069	249	{
1ebd0687 RH	250	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]);
1ebd0687 RH	251	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);
1d6902d3 RR	252
	253	if (!chip->gpio_width[1])
	254	return;
	255
1ebd0687	256	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
1d6902d3	257	chip->gpio_state[1]);
1ebd0687	258	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
1d6902d3	259	chip->gpio_dir[1]);
0bcb6069 JL	260	}
0bcb6069 JL	261
0230a41e SN	262	/**
	263	* xgpio_remove - Remove method for the GPIO device.
	264	* @pdev: pointer to the platform device
	265	*
	266	* This function remove gpiochips and frees all the allocated resources.
	267	*
	268	* Return: 0 always
	269	*/
	270	static int xgpio_remove(struct platform_device *pdev)
	271	{
	272	struct xgpio_instance *gpio = platform_get_drvdata(pdev);
	273
	274	clk_disable_unprepare(gpio->clk);
	275
	276	return 0;
	277	}
	278
0bcb6069 JL	279	/**
0bcb6069 JL	280	* xgpio_of_probe - Probe method for the GPIO device.
749564ff	281	* @pdev: pointer to the platform device
0bcb6069	282	*
4ae798fa RR	283	* Return:
	284	* It returns 0, if the driver is bound to the GPIO device, or
	285	* a negative value if there is an error.
0bcb6069	286	*/
749564ff	287	static int xgpio_probe(struct platform_device *pdev)
0bcb6069 JL	288	{
0bcb6069 JL	289	struct xgpio_instance *chip;
0bcb6069	290	int status = 0;
749564ff	291	struct device_node *np = pdev->dev.of_node;
1d6902d3	292	u32 is_dual;
0bcb6069	293
1d6902d3 RR	294	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1d6902d3 RR	295	if (!chip)
0bcb6069	296	return -ENOMEM;
0bcb6069	297
1d6902d3	298	platform_set_drvdata(pdev, chip);
749564ff	299
0bcb6069	300	/* Update GPIO state shadow register with default value */
bea67aea SN	301	if (of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]))
bea67aea SN	302	chip->gpio_state[0] = 0x0;
0bcb6069 JL	303
0bcb6069 JL	304	/* Update GPIO direction shadow register with default value */
1d6902d3 RR	305	if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
1d6902d3 RR	306	chip->gpio_dir[0] = 0xFFFFFFFF;
6f8bf500	307
1b4c5a6e GV	308	/*
	309	* Check device node and parent device node for device width
	310	* and assume default width of 32
	311	*/
1d6902d3 RR	312	if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
	313	chip->gpio_width[0] = 32;
	314
	315	spin_lock_init(&chip->gpio_lock[0]);
	316
	317	if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
	318	is_dual = 0;
0bcb6069	319
1d6902d3 RR	320	if (is_dual) {
1d6902d3 RR	321	/* Update GPIO state shadow register with default value */
bea67aea SN	322	if (of_property_read_u32(np, "xlnx,dout-default-2",
	323	&chip->gpio_state[1]))
	324	chip->gpio_state[1] = 0x0;
1d6902d3 RR	325
	326	/* Update GPIO direction shadow register with default value */
	327	if (of_property_read_u32(np, "xlnx,tri-default-2",
	328	&chip->gpio_dir[1]))
	329	chip->gpio_dir[1] = 0xFFFFFFFF;
0bcb6069	330
1d6902d3 RR	331	/*
	332	* Check device node and parent device node for device width
	333	* and assume default width of 32
	334	*/
	335	if (of_property_read_u32(np, "xlnx,gpio2-width",
	336	&chip->gpio_width[1]))
	337	chip->gpio_width[1] = 32;
	338
	339	spin_lock_init(&chip->gpio_lock[1]);
	340	}
	341
1ebd0687 RH	342	chip->gc.base = -1;
	343	chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
	344	chip->gc.parent = &pdev->dev;
	345	chip->gc.direction_input = xgpio_dir_in;
	346	chip->gc.direction_output = xgpio_dir_out;
	347	chip->gc.get = xgpio_get;
	348	chip->gc.set = xgpio_set;
	349	chip->gc.set_multiple = xgpio_set_multiple;
	350
	351	chip->gc.label = dev_name(&pdev->dev);
	352
	353	chip->regs = devm_platform_ioremap_resource(pdev, 0);
	354	if (IS_ERR(chip->regs)) {
	355	dev_err(&pdev->dev, "failed to ioremap memory resource\n");
	356	return PTR_ERR(chip->regs);
	357	}
0bcb6069	358
65bbe531 SN	359	chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
	360	if (IS_ERR(chip->clk)) {
	361	if (PTR_ERR(chip->clk) != -EPROBE_DEFER)
	362	dev_dbg(&pdev->dev, "Input clock not found\n");
	363	return PTR_ERR(chip->clk);
	364	}
	365
	366	status = clk_prepare_enable(chip->clk);
	367	if (status < 0) {
	368	dev_err(&pdev->dev, "Failed to prepare clk\n");
	369	return status;
	370	}
	371
1ebd0687	372	xgpio_save_regs(chip);
0bcb6069	373
1ebd0687	374	status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
0bcb6069	375	if (status) {
1ebd0687	376	dev_err(&pdev->dev, "failed to add GPIO chip\n");
65bbe531	377	clk_disable_unprepare(chip->clk);
0bcb6069 JL	378	return status;
0bcb6069 JL	379	}
74600ee0	380
0bcb6069 JL	381	return 0;
	382	}
	383
9992bc95	384	static const struct of_device_id xgpio_of_match[] = {
0bcb6069 JL	385	{ .compatible = "xlnx,xps-gpio-1.00.a", },
	386	{ /* end of list */ },
	387	};
	388
749564ff	389	MODULE_DEVICE_TABLE(of, xgpio_of_match);
0bcb6069	390
749564ff RR	391	static struct platform_driver xgpio_plat_driver = {
749564ff RR	392	.probe = xgpio_probe,
0230a41e	393	.remove = xgpio_remove,
749564ff RR	394	.driver = {
	395	.name = "gpio-xilinx",
	396	.of_match_table = xgpio_of_match,
	397	},
	398	};
0bcb6069	399
749564ff RR	400	static int __init xgpio_init(void)
	401	{
	402	return platform_driver_register(&xgpio_plat_driver);
0bcb6069 JL	403	}
0bcb6069 JL	404
0bcb6069	405	subsys_initcall(xgpio_init);
749564ff RR	406
	407	static void __exit xgpio_exit(void)
	408	{
	409	platform_driver_unregister(&xgpio_plat_driver);
	410	}
	411	module_exit(xgpio_exit);
0bcb6069 JL	412
	413	MODULE_AUTHOR("Xilinx, Inc.");
	414	MODULE_DESCRIPTION("Xilinx GPIO driver");
	415	MODULE_LICENSE("GPL");