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ff718800 KP |
1 | /* |
2 | * Copyright (C) 2003-2015 Broadcom Corporation | |
3 | * All Rights Reserved | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/gpio.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/of_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/interrupt.h> | |
83ea24fd | 21 | #include <linux/irqchip/chained_irq.h> |
ff718800 KP |
22 | |
23 | /* | |
24 | * XLP GPIO has multiple 32 bit registers for each feature where each register | |
25 | * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96 | |
26 | * require 3 32-bit registers for each feature. | |
27 | * Here we only define offset of the first register for each feature. Offset of | |
28 | * the registers for pins greater than 32 can be calculated as following(Use | |
29 | * GPIO_INT_STAT as example): | |
30 | * | |
31 | * offset = (gpio / XLP_GPIO_REGSZ) * 4; | |
32 | * reg_addr = addr + offset; | |
33 | * | |
34 | * where addr is base address of the that feature register and gpio is the pin. | |
35 | */ | |
36 | #define GPIO_OUTPUT_EN 0x00 | |
37 | #define GPIO_PADDRV 0x08 | |
38 | #define GPIO_INT_EN00 0x18 | |
39 | #define GPIO_INT_EN10 0x20 | |
40 | #define GPIO_INT_EN20 0x28 | |
41 | #define GPIO_INT_EN30 0x30 | |
42 | #define GPIO_INT_POL 0x38 | |
43 | #define GPIO_INT_TYPE 0x40 | |
44 | #define GPIO_INT_STAT 0x48 | |
45 | ||
46 | #define GPIO_9XX_BYTESWAP 0X00 | |
47 | #define GPIO_9XX_CTRL 0X04 | |
48 | #define GPIO_9XX_OUTPUT_EN 0x14 | |
49 | #define GPIO_9XX_PADDRV 0x24 | |
50 | /* | |
51 | * Only for 4 interrupt enable reg are defined for now, | |
52 | * total reg available are 12. | |
53 | */ | |
54 | #define GPIO_9XX_INT_EN00 0x44 | |
55 | #define GPIO_9XX_INT_EN10 0x54 | |
56 | #define GPIO_9XX_INT_EN20 0x64 | |
57 | #define GPIO_9XX_INT_EN30 0x74 | |
58 | #define GPIO_9XX_INT_POL 0x104 | |
59 | #define GPIO_9XX_INT_TYPE 0x114 | |
60 | #define GPIO_9XX_INT_STAT 0x124 | |
61 | ||
62 | #define GPIO_3XX_INT_EN00 0x18 | |
63 | #define GPIO_3XX_INT_EN10 0x20 | |
64 | #define GPIO_3XX_INT_EN20 0x28 | |
65 | #define GPIO_3XX_INT_EN30 0x30 | |
66 | #define GPIO_3XX_INT_POL 0x78 | |
67 | #define GPIO_3XX_INT_TYPE 0x80 | |
68 | #define GPIO_3XX_INT_STAT 0x88 | |
69 | ||
70 | /* Interrupt type register mask */ | |
71 | #define XLP_GPIO_IRQ_TYPE_LVL 0x0 | |
72 | #define XLP_GPIO_IRQ_TYPE_EDGE 0x1 | |
73 | ||
74 | /* Interrupt polarity register mask */ | |
75 | #define XLP_GPIO_IRQ_POL_HIGH 0x0 | |
76 | #define XLP_GPIO_IRQ_POL_LOW 0x1 | |
77 | ||
78 | #define XLP_GPIO_REGSZ 32 | |
79 | #define XLP_GPIO_IRQ_BASE 768 | |
80 | #define XLP_MAX_NR_GPIO 96 | |
81 | ||
82 | /* XLP variants supported by this driver */ | |
83 | enum { | |
84 | XLP_GPIO_VARIANT_XLP832 = 1, | |
85 | XLP_GPIO_VARIANT_XLP316, | |
86 | XLP_GPIO_VARIANT_XLP208, | |
87 | XLP_GPIO_VARIANT_XLP980, | |
88 | XLP_GPIO_VARIANT_XLP532 | |
89 | }; | |
90 | ||
91 | struct xlp_gpio_priv { | |
92 | struct gpio_chip chip; | |
93 | DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO); | |
94 | void __iomem *gpio_intr_en; /* pointer to first intr enable reg */ | |
95 | void __iomem *gpio_intr_stat; /* pointer to first intr status reg */ | |
96 | void __iomem *gpio_intr_type; /* pointer to first intr type reg */ | |
97 | void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */ | |
98 | void __iomem *gpio_out_en; /* pointer to first output enable reg */ | |
99 | void __iomem *gpio_paddrv; /* pointer to first pad drive reg */ | |
100 | spinlock_t lock; | |
101 | }; | |
102 | ||
103 | static struct xlp_gpio_priv *gpio_chip_to_xlp_priv(struct gpio_chip *gc) | |
104 | { | |
105 | return container_of(gc, struct xlp_gpio_priv, chip); | |
106 | } | |
107 | ||
108 | static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio) | |
109 | { | |
110 | u32 pos, regset; | |
111 | ||
112 | pos = gpio % XLP_GPIO_REGSZ; | |
113 | regset = (gpio / XLP_GPIO_REGSZ) * 4; | |
114 | return !!(readl(addr + regset) & BIT(pos)); | |
115 | } | |
116 | ||
117 | static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state) | |
118 | { | |
119 | u32 value, pos, regset; | |
120 | ||
121 | pos = gpio % XLP_GPIO_REGSZ; | |
122 | regset = (gpio / XLP_GPIO_REGSZ) * 4; | |
123 | value = readl(addr + regset); | |
124 | ||
125 | if (state) | |
126 | value |= BIT(pos); | |
127 | else | |
128 | value &= ~BIT(pos); | |
129 | ||
130 | writel(value, addr + regset); | |
131 | } | |
132 | ||
133 | static void xlp_gpio_irq_disable(struct irq_data *d) | |
134 | { | |
135 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
136 | struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); | |
137 | unsigned long flags; | |
138 | ||
139 | spin_lock_irqsave(&priv->lock, flags); | |
140 | xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); | |
141 | __clear_bit(d->hwirq, priv->gpio_enabled_mask); | |
142 | spin_unlock_irqrestore(&priv->lock, flags); | |
143 | } | |
144 | ||
145 | static void xlp_gpio_irq_mask_ack(struct irq_data *d) | |
146 | { | |
147 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
148 | struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); | |
149 | unsigned long flags; | |
150 | ||
151 | spin_lock_irqsave(&priv->lock, flags); | |
152 | xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); | |
153 | xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1); | |
154 | __clear_bit(d->hwirq, priv->gpio_enabled_mask); | |
155 | spin_unlock_irqrestore(&priv->lock, flags); | |
156 | } | |
157 | ||
158 | static void xlp_gpio_irq_unmask(struct irq_data *d) | |
159 | { | |
160 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
161 | struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); | |
162 | unsigned long flags; | |
163 | ||
164 | spin_lock_irqsave(&priv->lock, flags); | |
165 | xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1); | |
166 | __set_bit(d->hwirq, priv->gpio_enabled_mask); | |
167 | spin_unlock_irqrestore(&priv->lock, flags); | |
168 | } | |
169 | ||
170 | static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type) | |
171 | { | |
172 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
173 | struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); | |
174 | int pol, irq_type; | |
175 | ||
176 | switch (type) { | |
177 | case IRQ_TYPE_EDGE_RISING: | |
178 | irq_type = XLP_GPIO_IRQ_TYPE_EDGE; | |
179 | pol = XLP_GPIO_IRQ_POL_HIGH; | |
180 | break; | |
181 | case IRQ_TYPE_EDGE_FALLING: | |
182 | irq_type = XLP_GPIO_IRQ_TYPE_EDGE; | |
183 | pol = XLP_GPIO_IRQ_POL_LOW; | |
184 | break; | |
185 | case IRQ_TYPE_LEVEL_HIGH: | |
186 | irq_type = XLP_GPIO_IRQ_TYPE_LVL; | |
187 | pol = XLP_GPIO_IRQ_POL_HIGH; | |
188 | break; | |
189 | case IRQ_TYPE_LEVEL_LOW: | |
190 | irq_type = XLP_GPIO_IRQ_TYPE_LVL; | |
191 | pol = XLP_GPIO_IRQ_POL_LOW; | |
192 | break; | |
193 | default: | |
194 | return -EINVAL; | |
195 | } | |
196 | ||
197 | xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type); | |
198 | xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol); | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
203 | static struct irq_chip xlp_gpio_irq_chip = { | |
204 | .name = "XLP-GPIO", | |
205 | .irq_mask_ack = xlp_gpio_irq_mask_ack, | |
206 | .irq_disable = xlp_gpio_irq_disable, | |
207 | .irq_set_type = xlp_gpio_set_irq_type, | |
208 | .irq_unmask = xlp_gpio_irq_unmask, | |
209 | .flags = IRQCHIP_ONESHOT_SAFE, | |
210 | }; | |
211 | ||
83ea24fd | 212 | static void xlp_gpio_generic_handler(struct irq_desc *desc) |
ff718800 | 213 | { |
83ea24fd KP |
214 | struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc); |
215 | struct irq_chip *irqchip = irq_desc_get_chip(desc); | |
ff718800 KP |
216 | int gpio, regoff; |
217 | u32 gpio_stat; | |
218 | ||
219 | regoff = -1; | |
220 | gpio_stat = 0; | |
83ea24fd KP |
221 | |
222 | chained_irq_enter(irqchip, desc); | |
ff718800 KP |
223 | for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) { |
224 | if (regoff != gpio / XLP_GPIO_REGSZ) { | |
225 | regoff = gpio / XLP_GPIO_REGSZ; | |
226 | gpio_stat = readl(priv->gpio_intr_stat + regoff * 4); | |
227 | } | |
83ea24fd | 228 | |
ff718800 KP |
229 | if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ)) |
230 | generic_handle_irq(irq_find_mapping( | |
231 | priv->chip.irqdomain, gpio)); | |
232 | } | |
83ea24fd | 233 | chained_irq_exit(irqchip, desc); |
ff718800 KP |
234 | } |
235 | ||
236 | static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state) | |
237 | { | |
238 | struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); | |
239 | ||
240 | BUG_ON(gpio >= gc->ngpio); | |
241 | xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1); | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio) | |
247 | { | |
248 | struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); | |
249 | ||
250 | BUG_ON(gpio >= gc->ngpio); | |
251 | xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0); | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
256 | static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio) | |
257 | { | |
258 | struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); | |
259 | ||
260 | BUG_ON(gpio >= gc->ngpio); | |
261 | return xlp_gpio_get_reg(priv->gpio_paddrv, gpio); | |
262 | } | |
263 | ||
264 | static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state) | |
265 | { | |
266 | struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); | |
267 | ||
268 | BUG_ON(gpio >= gc->ngpio); | |
269 | xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state); | |
270 | } | |
271 | ||
272 | static const struct of_device_id xlp_gpio_of_ids[] = { | |
273 | { | |
274 | .compatible = "netlogic,xlp832-gpio", | |
275 | .data = (void *)XLP_GPIO_VARIANT_XLP832, | |
276 | }, | |
277 | { | |
278 | .compatible = "netlogic,xlp316-gpio", | |
279 | .data = (void *)XLP_GPIO_VARIANT_XLP316, | |
280 | }, | |
281 | { | |
282 | .compatible = "netlogic,xlp208-gpio", | |
283 | .data = (void *)XLP_GPIO_VARIANT_XLP208, | |
284 | }, | |
285 | { | |
286 | .compatible = "netlogic,xlp980-gpio", | |
287 | .data = (void *)XLP_GPIO_VARIANT_XLP980, | |
288 | }, | |
289 | { | |
290 | .compatible = "netlogic,xlp532-gpio", | |
291 | .data = (void *)XLP_GPIO_VARIANT_XLP532, | |
292 | }, | |
293 | { /* sentinel */ }, | |
294 | }; | |
295 | MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids); | |
296 | ||
297 | static int xlp_gpio_probe(struct platform_device *pdev) | |
298 | { | |
299 | struct gpio_chip *gc; | |
300 | struct resource *iores; | |
301 | struct xlp_gpio_priv *priv; | |
302 | const struct of_device_id *of_id; | |
303 | void __iomem *gpio_base; | |
304 | int irq_base, irq, err; | |
305 | int ngpio; | |
306 | u32 soc_type; | |
307 | ||
308 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
309 | if (!iores) | |
310 | return -ENODEV; | |
311 | ||
312 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
313 | if (!priv) | |
314 | return -ENOMEM; | |
315 | ||
316 | gpio_base = devm_ioremap_resource(&pdev->dev, iores); | |
317 | if (IS_ERR(gpio_base)) | |
318 | return PTR_ERR(gpio_base); | |
319 | ||
320 | irq = platform_get_irq(pdev, 0); | |
321 | if (irq < 0) | |
322 | return irq; | |
323 | ||
324 | of_id = of_match_device(xlp_gpio_of_ids, &pdev->dev); | |
325 | if (!of_id) { | |
326 | dev_err(&pdev->dev, "Failed to get soc type!\n"); | |
327 | return -ENODEV; | |
328 | } | |
329 | ||
330 | soc_type = (uintptr_t) of_id->data; | |
331 | ||
332 | switch (soc_type) { | |
333 | case XLP_GPIO_VARIANT_XLP832: | |
334 | priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN; | |
335 | priv->gpio_paddrv = gpio_base + GPIO_PADDRV; | |
336 | priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT; | |
337 | priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE; | |
338 | priv->gpio_intr_pol = gpio_base + GPIO_INT_POL; | |
339 | priv->gpio_intr_en = gpio_base + GPIO_INT_EN00; | |
340 | ngpio = 41; | |
341 | break; | |
342 | case XLP_GPIO_VARIANT_XLP208: | |
343 | case XLP_GPIO_VARIANT_XLP316: | |
344 | priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN; | |
345 | priv->gpio_paddrv = gpio_base + GPIO_PADDRV; | |
346 | priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT; | |
347 | priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE; | |
348 | priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL; | |
349 | priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00; | |
350 | ||
351 | ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57; | |
352 | break; | |
353 | case XLP_GPIO_VARIANT_XLP980: | |
354 | case XLP_GPIO_VARIANT_XLP532: | |
355 | priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN; | |
356 | priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV; | |
357 | priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT; | |
358 | priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE; | |
359 | priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL; | |
360 | priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00; | |
361 | ||
362 | ngpio = (soc_type == XLP_GPIO_VARIANT_XLP980) ? 66 : 67; | |
363 | break; | |
364 | default: | |
365 | dev_err(&pdev->dev, "Unknown Processor type!\n"); | |
366 | return -ENODEV; | |
367 | } | |
368 | ||
369 | bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO); | |
370 | ||
371 | gc = &priv->chip; | |
372 | ||
b8a3f52e AL |
373 | gc->owner = THIS_MODULE; |
374 | gc->label = dev_name(&pdev->dev); | |
ff718800 | 375 | gc->base = 0; |
58383c78 | 376 | gc->parent = &pdev->dev; |
ff718800 KP |
377 | gc->ngpio = ngpio; |
378 | gc->of_node = pdev->dev.of_node; | |
379 | gc->direction_output = xlp_gpio_dir_output; | |
380 | gc->direction_input = xlp_gpio_dir_input; | |
381 | gc->set = xlp_gpio_set; | |
382 | gc->get = xlp_gpio_get; | |
383 | ||
384 | spin_lock_init(&priv->lock); | |
ff718800 KP |
385 | irq_base = irq_alloc_descs(-1, XLP_GPIO_IRQ_BASE, gc->ngpio, 0); |
386 | if (irq_base < 0) { | |
387 | dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); | |
a0c81ce0 | 388 | return -ENODEV; |
ff718800 KP |
389 | } |
390 | ||
391 | err = gpiochip_add(gc); | |
392 | if (err < 0) | |
393 | goto out_free_desc; | |
394 | ||
395 | err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base, | |
396 | handle_level_irq, IRQ_TYPE_NONE); | |
397 | if (err) { | |
398 | dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n"); | |
399 | goto out_gpio_remove; | |
400 | } | |
401 | ||
83ea24fd KP |
402 | gpiochip_set_chained_irqchip(gc, &xlp_gpio_irq_chip, irq, |
403 | xlp_gpio_generic_handler); | |
404 | ||
ff718800 KP |
405 | dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio); |
406 | ||
407 | return 0; | |
408 | ||
409 | out_gpio_remove: | |
410 | gpiochip_remove(gc); | |
411 | out_free_desc: | |
412 | irq_free_descs(irq_base, gc->ngpio); | |
413 | return err; | |
414 | } | |
415 | ||
416 | static struct platform_driver xlp_gpio_driver = { | |
417 | .driver = { | |
418 | .name = "xlp-gpio", | |
419 | .of_match_table = xlp_gpio_of_ids, | |
420 | }, | |
421 | .probe = xlp_gpio_probe, | |
422 | }; | |
423 | module_platform_driver(xlp_gpio_driver); | |
424 | ||
425 | MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>"); | |
426 | MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>"); | |
427 | MODULE_DESCRIPTION("Netlogic XLP GPIO Driver"); | |
428 | MODULE_LICENSE("GPL v2"); |