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[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-zynq.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
3242ba11
HK		 2/*
3 * Xilinx Zynq GPIO device driver
4 *
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
3242ba11
HK		 6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
fdcfec11 13#include <linux/spinlock.h>
3242ba11
HK		 14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
bdf7a4ae 18#include <linux/of.h>
3242ba11
HK		 19
20#define DRIVER_NAME "zynq-gpio"
21
22/* Maximum banks */
23#define ZYNQ_GPIO_MAX_BANK 4
bdf7a4ae 24#define ZYNQMP_GPIO_MAX_BANK 6
67500244 25#define VERSAL_GPIO_MAX_BANK 4
73c612fe 26#define PMC_GPIO_MAX_BANK 5
67500244 27#define VERSAL_UNUSED_BANKS 2
3242ba11
HK		 28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
bdf7a4ae
AKV		 34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
40
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
3242ba11 62
3242ba11
HK		 63/* Register offsets for the GPIO device */
64/* LSW Mask & Data -WO */
65#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
66/* MSW Mask & Data -WO */
67#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
68/* Data Register-RW */
06aa0908 69#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
3242ba11
HK		 70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */
72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
73/* Output enable reg-RW */
74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
75/* Interrupt mask reg-RO */
76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
77/* Interrupt enable reg-WO */
78#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
79/* Interrupt disable reg-WO */
80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
81/* Interrupt status reg-RO */
82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
83/* Interrupt type reg-RW */
84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
85/* Interrupt polarity reg-RW */
86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
87/* Interrupt on any, reg-RW */
88#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
89
90/* Disable all interrupts mask */
91#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
92
93/* Mid pin number of a bank */
94#define ZYNQ_GPIO_MID_PIN_NUM 16
95
96/* GPIO upper 16 bit mask */
97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
98
3638bd4a
SB		 99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
06aa0908 101#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
67500244 102#define GPIO_QUIRK_VERSAL BIT(2)
e3296f19 103
e11de4de
SD		 104struct gpio_regs {
105 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
106 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
107 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
108 u32 outen[ZYNQMP_GPIO_MAX_BANK];
109 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
110 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
111 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
112 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
113 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
114};
eb73d6ea 115
3242ba11
HK		 116/**
117 * struct zynq_gpio - gpio device private data structure
118 * @chip: instance of the gpio_chip
119 * @base_addr: base address of the GPIO device
120 * @clk: clock resource for this controller
59e22114 121 * @irq: interrupt for the GPIO device
bdf7a4ae 122 * @p_data: pointer to platform data
e11de4de 123 * @context: context registers
fdcfec11 124 * @dirlock: lock used for direction in/out synchronization
3242ba11
HK		 125 */
126struct zynq_gpio {
127 struct gpio_chip chip;
128 void __iomem *base_addr;
129 struct clk *clk;
59e22114 130 int irq;
bdf7a4ae 131 const struct zynq_platform_data *p_data;
e11de4de 132 struct gpio_regs context;
fdcfec11 133 spinlock_t dirlock; /* lock */
bdf7a4ae
AKV		 134};
135
136/**
137 * struct zynq_platform_data - zynq gpio platform data structure
138 * @label: string to store in gpio->label
6ae5104c 139 * @quirks: Flags is used to identify the platform
bdf7a4ae
AKV		 140 * @ngpio: max number of gpio pins
141 * @max_bank: maximum number of gpio banks
142 * @bank_min: this array represents bank's min pin
143 * @bank_max: this array represents bank's max pin
6ae5104c 144 */
bdf7a4ae
AKV		 145struct zynq_platform_data {
146 const char *label;
e3296f19 147 u32 quirks;
bdf7a4ae
AKV		 148 u16 ngpio;
149 int max_bank;
150 int bank_min[ZYNQMP_GPIO_MAX_BANK];
151 int bank_max[ZYNQMP_GPIO_MAX_BANK];
3242ba11
HK		 152};
153
6dd85950
LPC		 154static struct irq_chip zynq_gpio_level_irqchip;
155static struct irq_chip zynq_gpio_edge_irqchip;
fa9795d1 156
3638bd4a
SB		 157/**
158 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
159 * @gpio: Pointer to driver data struct
160 *
161 * Return: 0 if zynqmp, 1 if zynq.
162 */
163static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
164{
165 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
166}
167
06aa0908
SM		 168/**
169 * gpio_data_ro_bug - test if HW bug exists or not
170 * @gpio: Pointer to driver data struct
171 *
172 * Return: 0 if bug doesnot exist, 1 if bug exists.
173 */
174static int gpio_data_ro_bug(struct zynq_gpio *gpio)
175{
176 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
177}
178
3242ba11
HK		 179/**
180 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
181 * for a given pin in the GPIO device
182 * @pin_num: gpio pin number within the device
183 * @bank_num: an output parameter used to return the bank number of the gpio
184 * pin
185 * @bank_pin_num: an output parameter used to return pin number within a bank
186 * for the given gpio pin
6ae5104c 187 * @gpio: gpio device data structure
3242ba11
HK		 188 *
189 * Returns the bank number and pin offset within the bank.
190 */
191static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
192 unsigned int *bank_num,
bdf7a4ae
AKV		 193 unsigned int *bank_pin_num,
194 struct zynq_gpio *gpio)
3242ba11 195{
bdf7a4ae
AKV		 196 int bank;
197
198 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
199 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
16ee62e5 200 (pin_num <= gpio->p_data->bank_max[bank])) {
2717cfca
NM		 201 *bank_num = bank;
202 *bank_pin_num = pin_num -
203 gpio->p_data->bank_min[bank];
204 return;
bdf7a4ae 205 }
67500244
SD		 206 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
207 bank = bank + VERSAL_UNUSED_BANKS;
3242ba11 208 }
3242ba11 209
bdf7a4ae
AKV		 210 /* default */
211 WARN(true, "invalid GPIO pin number: %u", pin_num);
212 *bank_num = 0;
213 *bank_pin_num = 0;
214}
016da144 215
3242ba11
HK		 216/**
217 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
218 * @chip: gpio_chip instance to be worked on
219 * @pin: gpio pin number within the device
220 *
221 * This function reads the state of the specified pin of the GPIO device.
222 *
223 * Return: 0 if the pin is low, 1 if pin is high.
224 */
225static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
226{
227 u32 data;
228 unsigned int bank_num, bank_pin_num;
31a89447 229 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 230
bdf7a4ae 231 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11 232
06aa0908
SM		 233 if (gpio_data_ro_bug(gpio)) {
234 if (zynq_gpio_is_zynq(gpio)) {
235 if (bank_num <= 1) {
236 data = readl_relaxed(gpio->base_addr +
237 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
238 } else {
239 data = readl_relaxed(gpio->base_addr +
240 ZYNQ_GPIO_DATA_OFFSET(bank_num));
241 }
242 } else {
243 if (bank_num <= 2) {
244 data = readl_relaxed(gpio->base_addr +
245 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
246 } else {
247 data = readl_relaxed(gpio->base_addr +
248 ZYNQ_GPIO_DATA_OFFSET(bank_num));
249 }
250 }
251 } else {
252 data = readl_relaxed(gpio->base_addr +
253 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
254 }
3242ba11
HK		 255 return (data >> bank_pin_num) & 1;
256}
257
258/**
259 * zynq_gpio_set_value - Modify the state of the pin with specified value
260 * @chip: gpio_chip instance to be worked on
261 * @pin: gpio pin number within the device
262 * @state: value used to modify the state of the specified pin
263 *
264 * This function calculates the register offset (i.e to lower 16 bits or
265 * upper 16 bits) based on the given pin number and sets the state of a
266 * gpio pin to the specified value. The state is either 0 or non-zero.
267 */
268static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
269 int state)
270{
271 unsigned int reg_offset, bank_num, bank_pin_num;
31a89447 272 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 273
bdf7a4ae 274 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 275
276 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
277 /* only 16 data bits in bit maskable reg */
278 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
279 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
280 } else {
281 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
282 }
283
284 /*
285 * get the 32 bit value to be written to the mask/data register where
286 * the upper 16 bits is the mask and lower 16 bits is the data
287 */
288 state = !!state;
289 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
290 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
291
292 writel_relaxed(state, gpio->base_addr + reg_offset);
293}
294
295/**
296 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
297 * @chip: gpio_chip instance to be worked on
298 * @pin: gpio pin number within the device
299 *
300 * This function uses the read-modify-write sequence to set the direction of
301 * the gpio pin as input.
302 *
303 * Return: 0 always
304 */
305static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
306{
307 u32 reg;
308 unsigned int bank_num, bank_pin_num;
fdcfec11 309 unsigned long flags;
31a89447 310 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 311
bdf7a4ae 312 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11 313
e3296f19
NM		 314 /*
315 * On zynq bank 0 pins 7 and 8 are special and cannot be used
316 * as inputs.
317 */
3638bd4a 318 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
16ee62e5 319 (bank_pin_num == 7 || bank_pin_num == 8))
3242ba11
HK		 320 return -EINVAL;
321
322 /* clear the bit in direction mode reg to set the pin as input */
fdcfec11 323 spin_lock_irqsave(&gpio->dirlock, flags);
3242ba11
HK		 324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
325 reg &= ~BIT(bank_pin_num);
326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
fdcfec11 327 spin_unlock_irqrestore(&gpio->dirlock, flags);
3242ba11
HK		 328
329 return 0;
330}
331
332/**
333 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
334 * @chip: gpio_chip instance to be worked on
335 * @pin: gpio pin number within the device
336 * @state: value to be written to specified pin
337 *
338 * This function sets the direction of specified GPIO pin as output, configures
339 * the Output Enable register for the pin and uses zynq_gpio_set to set
340 * the state of the pin to the value specified.
341 *
342 * Return: 0 always
343 */
344static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
345 int state)
346{
347 u32 reg;
348 unsigned int bank_num, bank_pin_num;
fdcfec11 349 unsigned long flags;
31a89447 350 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 351
bdf7a4ae 352 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 353
354 /* set the GPIO pin as output */
fdcfec11 355 spin_lock_irqsave(&gpio->dirlock, flags);
3242ba11
HK		 356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
357 reg |= BIT(bank_pin_num);
358 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
359
360 /* configure the output enable reg for the pin */
361 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
362 reg |= BIT(bank_pin_num);
363 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
fdcfec11 364 spin_unlock_irqrestore(&gpio->dirlock, flags);
3242ba11
HK		 365
366 /* set the state of the pin */
367 zynq_gpio_set_value(chip, pin, state);
368 return 0;
369}
370
6169005c
BM		 371/**
372 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
373 * @chip: gpio_chip instance to be worked on
374 * @pin: gpio pin number within the device
375 *
376 * This function returns the direction of the specified GPIO.
377 *
e42615ec 378 * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN
6169005c
BM		 379 */
380static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
381{
382 u32 reg;
383 unsigned int bank_num, bank_pin_num;
384 struct zynq_gpio *gpio = gpiochip_get_data(chip);
385
386 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
387
388 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
389
e42615ec
MV		 390 if (reg & BIT(bank_pin_num))
391 return GPIO_LINE_DIRECTION_OUT;
392
393 return GPIO_LINE_DIRECTION_IN;
6169005c
BM		 394}
395
3242ba11
HK		 396/**
397 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
398 * @irq_data: per irq and chip data passed down to chip functions
399 *
400 * This function calculates gpio pin number from irq number and sets the
401 * bit in the Interrupt Disable register of the corresponding bank to disable
402 * interrupts for that pin.
403 */
404static void zynq_gpio_irq_mask(struct irq_data *irq_data)
405{
406 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 407 struct zynq_gpio *gpio =
31a89447 408 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 409
410 device_pin_num = irq_data->hwirq;
bdf7a4ae 411 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 412 writel_relaxed(BIT(bank_pin_num),
413 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
414}
415
416/**
417 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
418 * @irq_data: irq data containing irq number of gpio pin for the interrupt
419 * to enable
420 *
421 * This function calculates the gpio pin number from irq number and sets the
422 * bit in the Interrupt Enable register of the corresponding bank to enable
423 * interrupts for that pin.
424 */
425static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
426{
427 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 428 struct zynq_gpio *gpio =
31a89447 429 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 430
431 device_pin_num = irq_data->hwirq;
bdf7a4ae 432 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 433 writel_relaxed(BIT(bank_pin_num),
434 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
435}
436
190dc2e6
LPC		 437/**
438 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
439 * @irq_data: irq data containing irq number of gpio pin for the interrupt
440 * to ack
441 *
442 * This function calculates gpio pin number from irq number and sets the bit
443 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
444 */
445static void zynq_gpio_irq_ack(struct irq_data *irq_data)
446{
447 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 448 struct zynq_gpio *gpio =
31a89447 449 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
190dc2e6
LPC		 450
451 device_pin_num = irq_data->hwirq;
bdf7a4ae 452 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
190dc2e6
LPC		 453 writel_relaxed(BIT(bank_pin_num),
454 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
455}
456
457/**
458 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
459 * @irq_data: irq data containing irq number of gpio pin for the interrupt
460 * to enable
461 *
20a8a968 462 * Clears the INTSTS bit and unmasks the given interrupt.
190dc2e6
LPC		 463 */
464static void zynq_gpio_irq_enable(struct irq_data *irq_data)
465{
466 /*
467 * The Zynq GPIO controller does not disable interrupt detection when
468 * the interrupt is masked and only disables the propagation of the
469 * interrupt. This means when the controller detects an interrupt
470 * condition while the interrupt is logically disabled it will propagate
471 * that interrupt event once the interrupt is enabled. This will cause
472 * the interrupt consumer to see spurious interrupts to prevent this
473 * first make sure that the interrupt is not asserted and then enable
474 * it.
475 */
476 zynq_gpio_irq_ack(irq_data);
477 zynq_gpio_irq_unmask(irq_data);
478}
479
3242ba11
HK		 480/**
481 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
482 * @irq_data: irq data containing irq number of gpio pin
483 * @type: interrupt type that is to be set for the gpio pin
484 *
485 * This function gets the gpio pin number and its bank from the gpio pin number
486 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
487 *
488 * Return: 0, negative error otherwise.
489 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
490 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
491 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
492 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
493 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
494 */
495static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
496{
497 u32 int_type, int_pol, int_any;
498 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 499 struct zynq_gpio *gpio =
31a89447 500 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 501
502 device_pin_num = irq_data->hwirq;
bdf7a4ae 503 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 504
505 int_type = readl_relaxed(gpio->base_addr +
506 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
507 int_pol = readl_relaxed(gpio->base_addr +
508 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
509 int_any = readl_relaxed(gpio->base_addr +
510 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
511
512 /*
513 * based on the type requested, configure the INT_TYPE, INT_POLARITY
514 * and INT_ANY registers
515 */
516 switch (type) {
517 case IRQ_TYPE_EDGE_RISING:
518 int_type |= BIT(bank_pin_num);
519 int_pol |= BIT(bank_pin_num);
520 int_any &= ~BIT(bank_pin_num);
521 break;
522 case IRQ_TYPE_EDGE_FALLING:
523 int_type |= BIT(bank_pin_num);
524 int_pol &= ~BIT(bank_pin_num);
525 int_any &= ~BIT(bank_pin_num);
526 break;
527 case IRQ_TYPE_EDGE_BOTH:
528 int_type |= BIT(bank_pin_num);
529 int_any |= BIT(bank_pin_num);
530 break;
531 case IRQ_TYPE_LEVEL_HIGH:
532 int_type &= ~BIT(bank_pin_num);
533 int_pol |= BIT(bank_pin_num);
534 break;
535 case IRQ_TYPE_LEVEL_LOW:
536 int_type &= ~BIT(bank_pin_num);
537 int_pol &= ~BIT(bank_pin_num);
538 break;
539 default:
540 return -EINVAL;
541 }
542
543 writel_relaxed(int_type,
544 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
545 writel_relaxed(int_pol,
546 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
547 writel_relaxed(int_any,
548 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
6dd85950 549
16ee62e5 550 if (type & IRQ_TYPE_LEVEL_MASK)
47c08462 551 irq_set_chip_handler_name_locked(irq_data,
16ee62e5
MS		 552 &zynq_gpio_level_irqchip,
553 handle_fasteoi_irq, NULL);
554 else
47c08462 555 irq_set_chip_handler_name_locked(irq_data,
16ee62e5
MS		 556 &zynq_gpio_edge_irqchip,
557 handle_level_irq, NULL);
6dd85950 558
3242ba11
HK		 559 return 0;
560}
561
562static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
563{
fa9795d1 564 struct zynq_gpio *gpio =
31a89447 565 gpiochip_get_data(irq_data_get_irq_chip_data(data));
59e22114
ES		 566
567 irq_set_irq_wake(gpio->irq, on);
3242ba11
HK		 568
569 return 0;
570}
571
c2df3de0
TP		 572static int zynq_gpio_irq_reqres(struct irq_data *d)
573{
574 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
575 int ret;
576
577 ret = pm_runtime_get_sync(chip->parent);
578 if (ret < 0)
579 return ret;
580
581 return gpiochip_reqres_irq(chip, d->hwirq);
582}
583
584static void zynq_gpio_irq_relres(struct irq_data *d)
585{
586 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
587
588 gpiochip_relres_irq(chip, d->hwirq);
589 pm_runtime_put(chip->parent);
590}
591
3242ba11 592/* irq chip descriptor */
6dd85950 593static struct irq_chip zynq_gpio_level_irqchip = {
3242ba11 594 .name = DRIVER_NAME,
190dc2e6 595 .irq_enable = zynq_gpio_irq_enable,
6dd85950
LPC		 596 .irq_eoi = zynq_gpio_irq_ack,
597 .irq_mask = zynq_gpio_irq_mask,
598 .irq_unmask = zynq_gpio_irq_unmask,
599 .irq_set_type = zynq_gpio_set_irq_type,
600 .irq_set_wake = zynq_gpio_set_wake,
c2df3de0
TP		 601 .irq_request_resources = zynq_gpio_irq_reqres,
602 .irq_release_resources = zynq_gpio_irq_relres,
a1946778
ES		 603 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
604 IRQCHIP_MASK_ON_SUSPEND,
6dd85950
LPC		 605};
606
607static struct irq_chip zynq_gpio_edge_irqchip = {
608 .name = DRIVER_NAME,
609 .irq_enable = zynq_gpio_irq_enable,
610 .irq_ack = zynq_gpio_irq_ack,
3242ba11
HK		 611 .irq_mask = zynq_gpio_irq_mask,
612 .irq_unmask = zynq_gpio_irq_unmask,
613 .irq_set_type = zynq_gpio_set_irq_type,
614 .irq_set_wake = zynq_gpio_set_wake,
c2df3de0
TP		 615 .irq_request_resources = zynq_gpio_irq_reqres,
616 .irq_release_resources = zynq_gpio_irq_relres,
a1946778 617 .flags = IRQCHIP_MASK_ON_SUSPEND,
3242ba11
HK		 618};
619
5a2533a7
LPC		 620static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
621 unsigned int bank_num,
622 unsigned long pending)
623{
bdf7a4ae 624 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
f0fbe7bc 625 struct irq_domain *irqdomain = gpio->chip.irq.domain;
5a2533a7
LPC		 626 int offset;
627
628 if (!pending)
629 return;
630
631 for_each_set_bit(offset, &pending, 32) {
632 unsigned int gpio_irq;
633
016da144 634 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
5a2533a7
LPC		 635 generic_handle_irq(gpio_irq);
636 }
637}
638
3242ba11
HK		 639/**
640 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
3242ba11
HK		 641 * @desc: irq descriptor instance of the 'irq'
642 *
643 * This function reads the Interrupt Status Register of each bank to get the
644 * gpio pin number which has triggered an interrupt. It then acks the triggered
645 * interrupt and calls the pin specific handler set by the higher layer
646 * application for that pin.
647 * Note: A bug is reported if no handler is set for the gpio pin.
648 */
bd0b9ac4 649static void zynq_gpio_irqhandler(struct irq_desc *desc)
3242ba11
HK		 650{
651 u32 int_sts, int_enb;
652 unsigned int bank_num;
fa9795d1 653 struct zynq_gpio *gpio =
31a89447 654 gpiochip_get_data(irq_desc_get_handler_data(desc));
3242ba11
HK		 655 struct irq_chip *irqchip = irq_desc_get_chip(desc);
656
657 chained_irq_enter(irqchip, desc);
658
bdf7a4ae 659 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
3242ba11
HK		 660 int_sts = readl_relaxed(gpio->base_addr +
661 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
662 int_enb = readl_relaxed(gpio->base_addr +
663 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
5a2533a7 664 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
67500244
SD		 665 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
666 bank_num = bank_num + VERSAL_UNUSED_BANKS;
3242ba11
HK		 667 }
668
669 chained_irq_exit(irqchip, desc);
670}
671
e11de4de
SD		 672static void zynq_gpio_save_context(struct zynq_gpio *gpio)
673{
674 unsigned int bank_num;
675
676 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
677 gpio->context.datalsw[bank_num] =
678 readl_relaxed(gpio->base_addr +
679 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
680 gpio->context.datamsw[bank_num] =
681 readl_relaxed(gpio->base_addr +
682 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
683 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
684 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
685 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
686 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
687 gpio->context.int_type[bank_num] =
688 readl_relaxed(gpio->base_addr +
689 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
690 gpio->context.int_polarity[bank_num] =
691 readl_relaxed(gpio->base_addr +
692 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
693 gpio->context.int_any[bank_num] =
694 readl_relaxed(gpio->base_addr +
695 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
67500244
SD		 696 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
697 bank_num = bank_num + VERSAL_UNUSED_BANKS;
e11de4de
SD		 698 }
699}
700
701static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
702{
703 unsigned int bank_num;
704
705 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
36f2e720
SM		 706 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
707 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
e11de4de
SD		 708 writel_relaxed(gpio->context.datalsw[bank_num],
709 gpio->base_addr +
710 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
711 writel_relaxed(gpio->context.datamsw[bank_num],
712 gpio->base_addr +
713 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
714 writel_relaxed(gpio->context.dirm[bank_num],
715 gpio->base_addr +
716 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
e11de4de
SD		 717 writel_relaxed(gpio->context.int_type[bank_num],
718 gpio->base_addr +
719 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
720 writel_relaxed(gpio->context.int_polarity[bank_num],
721 gpio->base_addr +
722 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
723 writel_relaxed(gpio->context.int_any[bank_num],
724 gpio->base_addr +
725 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
36f2e720
SM		 726 writel_relaxed(~(gpio->context.int_en[bank_num]),
727 gpio->base_addr +
728 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
67500244
SD		 729 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
730 bank_num = bank_num + VERSAL_UNUSED_BANKS;
e11de4de
SD		 731 }
732}
eb73d6ea 733
3242ba11
HK		 734static int __maybe_unused zynq_gpio_suspend(struct device *dev)
735{
a76e865e 736 struct zynq_gpio *gpio = dev_get_drvdata(dev);
5e3a8ecd 737 struct irq_data *data = irq_get_irq_data(gpio->irq);
59e22114 738
26ebdbf8
SD		 739 if (!device_may_wakeup(dev))
740 disable_irq(gpio->irq);
741
e11de4de
SD		 742 if (!irqd_is_wakeup_set(data)) {
743 zynq_gpio_save_context(gpio);
3242ba11 744 return pm_runtime_force_suspend(dev);
e11de4de 745 }
3242ba11
HK		 746
747 return 0;
748}
749
750static int __maybe_unused zynq_gpio_resume(struct device *dev)
751{
a76e865e 752 struct zynq_gpio *gpio = dev_get_drvdata(dev);
5e3a8ecd 753 struct irq_data *data = irq_get_irq_data(gpio->irq);
e11de4de 754 int ret;
59e22114 755
26ebdbf8
SD		 756 if (!device_may_wakeup(dev))
757 enable_irq(gpio->irq);
758
e11de4de
SD		 759 if (!irqd_is_wakeup_set(data)) {
760 ret = pm_runtime_force_resume(dev);
761 zynq_gpio_restore_context(gpio);
762 return ret;
763 }
3242ba11
HK		 764
765 return 0;
766}
767
768static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
769{
38ccad02 770 struct zynq_gpio *gpio = dev_get_drvdata(dev);
3242ba11
HK		 771
772 clk_disable_unprepare(gpio->clk);
773
774 return 0;
775}
776
777static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
778{
38ccad02 779 struct zynq_gpio *gpio = dev_get_drvdata(dev);
3242ba11
HK		 780
781 return clk_prepare_enable(gpio->clk);
782}
783
2717cfca 784static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
3242ba11
HK		 785{
786 int ret;
787
58383c78 788 ret = pm_runtime_get_sync(chip->parent);
3242ba11
HK		 789
790 /*
791 * If the device is already active pm_runtime_get() will return 1 on
792 * success, but gpio_request still needs to return 0.
793 */
794 return ret < 0 ? ret : 0;
795}
796
2717cfca 797static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
3242ba11 798{
58383c78 799 pm_runtime_put(chip->parent);
3242ba11
HK		 800}
801
802static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
803 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
6ed23b80 804 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
16ee62e5 805 zynq_gpio_runtime_resume, NULL)
3242ba11
HK		 806};
807
67500244
SD		 808static const struct zynq_platform_data versal_gpio_def = {
809 .label = "versal_gpio",
810 .quirks = GPIO_QUIRK_VERSAL,
811 .ngpio = 58,
812 .max_bank = VERSAL_GPIO_MAX_BANK,
813 .bank_min[0] = 0,
814 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
815 .bank_min[3] = 26,
816 .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
817};
818
73c612fe
SD		 819static const struct zynq_platform_data pmc_gpio_def = {
820 .label = "pmc_gpio",
821 .ngpio = 116,
822 .max_bank = PMC_GPIO_MAX_BANK,
823 .bank_min[0] = 0,
824 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
825 .bank_min[1] = 26,
826 .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
827 .bank_min[3] = 52,
828 .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
829 .bank_min[4] = 84,
830 .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
831};
832
bdf7a4ae
AKV		 833static const struct zynq_platform_data zynqmp_gpio_def = {
834 .label = "zynqmp_gpio",
06aa0908 835 .quirks = GPIO_QUIRK_DATA_RO_BUG,
bdf7a4ae
AKV		 836 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
837 .max_bank = ZYNQMP_GPIO_MAX_BANK,
838 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
839 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
840 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
841 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
842 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
843 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
844 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
845 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
846 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
847 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
848 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
849 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
850};
851
852static const struct zynq_platform_data zynq_gpio_def = {
853 .label = "zynq_gpio",
06aa0908 854 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
bdf7a4ae
AKV		 855 .ngpio = ZYNQ_GPIO_NR_GPIOS,
856 .max_bank = ZYNQ_GPIO_MAX_BANK,
857 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
858 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
859 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
860 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
861 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
862 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
863 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
864 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
865};
866
867static const struct of_device_id zynq_gpio_of_match[] = {
7808c42b
MY		 868 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
869 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
67500244 870 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
73c612fe 871 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
bdf7a4ae
AKV		 872 { /* end of table */ }
873};
874MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
875
3242ba11
HK		 876/**
877 * zynq_gpio_probe - Initialization method for a zynq_gpio device
878 * @pdev: platform device instance
879 *
880 * This function allocates memory resources for the gpio device and registers
881 * all the banks of the device. It will also set up interrupts for the gpio
882 * pins.
883 * Note: Interrupts are disabled for all the banks during initialization.
884 *
885 * Return: 0 on success, negative error otherwise.
886 */
887static int zynq_gpio_probe(struct platform_device *pdev)
888{
59e22114 889 int ret, bank_num;
3242ba11
HK		 890 struct zynq_gpio *gpio;
891 struct gpio_chip *chip;
f6a7053d 892 struct gpio_irq_chip *girq;
bdf7a4ae 893 const struct of_device_id *match;
3242ba11
HK		 894
895 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
896 if (!gpio)
897 return -ENOMEM;
898
bdf7a4ae
AKV		 899 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
900 if (!match) {
901 dev_err(&pdev->dev, "of_match_node() failed\n");
902 return -EINVAL;
903 }
904 gpio->p_data = match->data;
3242ba11
HK		 905 platform_set_drvdata(pdev, gpio);
906
77bc0e69 907 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
3242ba11
HK		 908 if (IS_ERR(gpio->base_addr))
909 return PTR_ERR(gpio->base_addr);
910
59e22114 911 gpio->irq = platform_get_irq(pdev, 0);
15bddb7d 912 if (gpio->irq < 0)
59e22114 913 return gpio->irq;
3242ba11
HK		 914
915 /* configure the gpio chip */
916 chip = &gpio->chip;
bdf7a4ae 917 chip->label = gpio->p_data->label;
3242ba11 918 chip->owner = THIS_MODULE;
58383c78 919 chip->parent = &pdev->dev;
3242ba11
HK		 920 chip->get = zynq_gpio_get_value;
921 chip->set = zynq_gpio_set_value;
922 chip->request = zynq_gpio_request;
923 chip->free = zynq_gpio_free;
924 chip->direction_input = zynq_gpio_dir_in;
925 chip->direction_output = zynq_gpio_dir_out;
6169005c 926 chip->get_direction = zynq_gpio_get_direction;
060f3ebf 927 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
bdf7a4ae 928 chip->ngpio = gpio->p_data->ngpio;
3242ba11 929
3773c195 930 /* Retrieve GPIO clock */
3242ba11
HK		 931 gpio->clk = devm_clk_get(&pdev->dev, NULL);
932 if (IS_ERR(gpio->clk)) {
00774281
SD		 933 if (PTR_ERR(gpio->clk) != -EPROBE_DEFER)
934 dev_err(&pdev->dev, "input clock not found.\n");
3242ba11
HK		 935 return PTR_ERR(gpio->clk);
936 }
0f84f29f
HG		 937 ret = clk_prepare_enable(gpio->clk);
938 if (ret) {
939 dev_err(&pdev->dev, "Unable to enable clock.\n");
940 return ret;
941 }
3773c195 942
fdcfec11
GL		 943 spin_lock_init(&gpio->dirlock);
944
0f84f29f 945 pm_runtime_set_active(&pdev->dev);
3773c195
MS		 946 pm_runtime_enable(&pdev->dev);
947 ret = pm_runtime_get_sync(&pdev->dev);
948 if (ret < 0)
615d23f8 949 goto err_pm_dis;
3242ba11 950
3242ba11 951 /* disable interrupts for all banks */
67500244 952 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
3242ba11
HK		 953 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
954 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
67500244
SD		 955 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
956 bank_num = bank_num + VERSAL_UNUSED_BANKS;
957 }
3242ba11 958
f6a7053d
LW		 959 /* Set up the GPIO irqchip */
960 girq = &chip->irq;
961 girq->chip = &zynq_gpio_edge_irqchip;
962 girq->parent_handler = zynq_gpio_irqhandler;
963 girq->num_parents = 1;
964 girq->parents = devm_kcalloc(&pdev->dev, 1,
965 sizeof(*girq->parents),
966 GFP_KERNEL);
967 if (!girq->parents) {
968 ret = -ENOMEM;
969 goto err_pm_put;
3242ba11 970 }
f6a7053d
LW		 971 girq->parents[0] = gpio->irq;
972 girq->default_type = IRQ_TYPE_NONE;
973 girq->handler = handle_level_irq;
3242ba11 974
f6a7053d
LW		 975 /* report a bug if gpio chip registration fails */
976 ret = gpiochip_add_data(chip, gpio);
977 if (ret) {
978 dev_err(&pdev->dev, "Failed to add gpio chip\n");
979 goto err_pm_put;
980 }
3242ba11 981
26ebdbf8
SD		 982 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
983 device_init_wakeup(&pdev->dev, 1);
3773c195 984 pm_runtime_put(&pdev->dev);
3242ba11 985
3242ba11
HK		 986 return 0;
987
3773c195
MS		 988err_pm_put:
989 pm_runtime_put(&pdev->dev);
615d23f8
SD		 990err_pm_dis:
991 pm_runtime_disable(&pdev->dev);
0f84f29f 992 clk_disable_unprepare(gpio->clk);
3242ba11
HK		 993
994 return ret;
995}
996
997/**
998 * zynq_gpio_remove - Driver removal function
999 * @pdev: platform device instance
1000 *
1001 * Return: 0 always
1002 */
1003static int zynq_gpio_remove(struct platform_device *pdev)
1004{
3242ba11
HK		 1005 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
1006
1007 pm_runtime_get_sync(&pdev->dev);
da26d5d8 1008 gpiochip_remove(&gpio->chip);
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HK		 1009 clk_disable_unprepare(gpio->clk);
1010 device_set_wakeup_capable(&pdev->dev, 0);
6b956af0 1011 pm_runtime_disable(&pdev->dev);
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HK		 1012 return 0;
1013}
1014
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HK		 1015static struct platform_driver zynq_gpio_driver = {
1016 .driver = {
1017 .name = DRIVER_NAME,
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HK		 1018 .pm = &zynq_gpio_dev_pm_ops,
1019 .of_match_table = zynq_gpio_of_match,
1020 },
1021 .probe = zynq_gpio_probe,
1022 .remove = zynq_gpio_remove,
1023};
1024
1025/**
1026 * zynq_gpio_init - Initial driver registration call
1027 *
1028 * Return: value from platform_driver_register
1029 */
1030static int __init zynq_gpio_init(void)
1031{
1032 return platform_driver_register(&zynq_gpio_driver);
1033}
1034postcore_initcall(zynq_gpio_init);
1035
80d2bf55
MY		 1036static void __exit zynq_gpio_exit(void)
1037{
1038 platform_driver_unregister(&zynq_gpio_driver);
1039}
1040module_exit(zynq_gpio_exit);
1041
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HK		 1042MODULE_AUTHOR("Xilinx Inc.");
1043MODULE_DESCRIPTION("Zynq GPIO driver");
1044MODULE_LICENSE("GPL");
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