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Merge branch 'msm-fixes-3.19' of git://people.freedesktop.org/~robclark/linux into...
[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-zynq.c
CommitLineData
3242ba11
HK		 1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
9 * version.
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21
22#define DRIVER_NAME "zynq-gpio"
23
24/* Maximum banks */
25#define ZYNQ_GPIO_MAX_BANK 4
26
27#define ZYNQ_GPIO_BANK0_NGPIO 32
28#define ZYNQ_GPIO_BANK1_NGPIO 22
29#define ZYNQ_GPIO_BANK2_NGPIO 32
30#define ZYNQ_GPIO_BANK3_NGPIO 32
31
32#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
33 ZYNQ_GPIO_BANK1_NGPIO + \
34 ZYNQ_GPIO_BANK2_NGPIO + \
35 ZYNQ_GPIO_BANK3_NGPIO)
36
37#define ZYNQ_GPIO_BANK0_PIN_MIN 0
38#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
39 ZYNQ_GPIO_BANK0_NGPIO - 1)
40#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
41#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
42 ZYNQ_GPIO_BANK1_NGPIO - 1)
43#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
44#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
45 ZYNQ_GPIO_BANK2_NGPIO - 1)
46#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
47#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
48 ZYNQ_GPIO_BANK3_NGPIO - 1)
49
50
51/* Register offsets for the GPIO device */
52/* LSW Mask & Data -WO */
53#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
54/* MSW Mask & Data -WO */
55#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
56/* Data Register-RW */
57#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
58/* Direction mode reg-RW */
59#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
60/* Output enable reg-RW */
61#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
62/* Interrupt mask reg-RO */
63#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
64/* Interrupt enable reg-WO */
65#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
66/* Interrupt disable reg-WO */
67#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
68/* Interrupt status reg-RO */
69#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
70/* Interrupt type reg-RW */
71#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
72/* Interrupt polarity reg-RW */
73#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
74/* Interrupt on any, reg-RW */
75#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
76
77/* Disable all interrupts mask */
78#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
79
80/* Mid pin number of a bank */
81#define ZYNQ_GPIO_MID_PIN_NUM 16
82
83/* GPIO upper 16 bit mask */
84#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
85
86/**
87 * struct zynq_gpio - gpio device private data structure
88 * @chip: instance of the gpio_chip
89 * @base_addr: base address of the GPIO device
90 * @clk: clock resource for this controller
59e22114 91 * @irq: interrupt for the GPIO device
3242ba11
HK		 92 */
93struct zynq_gpio {
94 struct gpio_chip chip;
95 void __iomem *base_addr;
96 struct clk *clk;
59e22114 97 int irq;
3242ba11
HK		 98};
99
6dd85950
LPC		 100static struct irq_chip zynq_gpio_level_irqchip;
101static struct irq_chip zynq_gpio_edge_irqchip;
3242ba11
HK		 102/**
103 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
104 * for a given pin in the GPIO device
105 * @pin_num: gpio pin number within the device
106 * @bank_num: an output parameter used to return the bank number of the gpio
107 * pin
108 * @bank_pin_num: an output parameter used to return pin number within a bank
109 * for the given gpio pin
110 *
111 * Returns the bank number and pin offset within the bank.
112 */
113static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
114 unsigned int *bank_num,
115 unsigned int *bank_pin_num)
116{
117 switch (pin_num) {
118 case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
119 *bank_num = 0;
120 *bank_pin_num = pin_num;
121 break;
122 case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
123 *bank_num = 1;
124 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
125 break;
126 case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
127 *bank_num = 2;
128 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
129 break;
130 case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
131 *bank_num = 3;
132 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
133 break;
134 default:
135 WARN(true, "invalid GPIO pin number: %u", pin_num);
136 *bank_num = 0;
137 *bank_pin_num = 0;
138 break;
139 }
140}
141
016da144
LPC		 142static const unsigned int zynq_gpio_bank_offset[] = {
143 ZYNQ_GPIO_BANK0_PIN_MIN,
144 ZYNQ_GPIO_BANK1_PIN_MIN,
145 ZYNQ_GPIO_BANK2_PIN_MIN,
146 ZYNQ_GPIO_BANK3_PIN_MIN,
147};
148
3242ba11
HK		 149/**
150 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
151 * @chip: gpio_chip instance to be worked on
152 * @pin: gpio pin number within the device
153 *
154 * This function reads the state of the specified pin of the GPIO device.
155 *
156 * Return: 0 if the pin is low, 1 if pin is high.
157 */
158static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
159{
160 u32 data;
161 unsigned int bank_num, bank_pin_num;
162 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
163
164 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
165
166 data = readl_relaxed(gpio->base_addr +
167 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
168
169 return (data >> bank_pin_num) & 1;
170}
171
172/**
173 * zynq_gpio_set_value - Modify the state of the pin with specified value
174 * @chip: gpio_chip instance to be worked on
175 * @pin: gpio pin number within the device
176 * @state: value used to modify the state of the specified pin
177 *
178 * This function calculates the register offset (i.e to lower 16 bits or
179 * upper 16 bits) based on the given pin number and sets the state of a
180 * gpio pin to the specified value. The state is either 0 or non-zero.
181 */
182static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
183 int state)
184{
185 unsigned int reg_offset, bank_num, bank_pin_num;
186 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
187
188 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
189
190 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
191 /* only 16 data bits in bit maskable reg */
192 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
193 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
194 } else {
195 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
196 }
197
198 /*
199 * get the 32 bit value to be written to the mask/data register where
200 * the upper 16 bits is the mask and lower 16 bits is the data
201 */
202 state = !!state;
203 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
204 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
205
206 writel_relaxed(state, gpio->base_addr + reg_offset);
207}
208
209/**
210 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
211 * @chip: gpio_chip instance to be worked on
212 * @pin: gpio pin number within the device
213 *
214 * This function uses the read-modify-write sequence to set the direction of
215 * the gpio pin as input.
216 *
217 * Return: 0 always
218 */
219static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
220{
221 u32 reg;
222 unsigned int bank_num, bank_pin_num;
223 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
224
225 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
226
227 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
228 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
229 return -EINVAL;
230
231 /* clear the bit in direction mode reg to set the pin as input */
232 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
233 reg &= ~BIT(bank_pin_num);
234 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
235
236 return 0;
237}
238
239/**
240 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
241 * @chip: gpio_chip instance to be worked on
242 * @pin: gpio pin number within the device
243 * @state: value to be written to specified pin
244 *
245 * This function sets the direction of specified GPIO pin as output, configures
246 * the Output Enable register for the pin and uses zynq_gpio_set to set
247 * the state of the pin to the value specified.
248 *
249 * Return: 0 always
250 */
251static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
252 int state)
253{
254 u32 reg;
255 unsigned int bank_num, bank_pin_num;
256 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
257
258 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
259
260 /* set the GPIO pin as output */
261 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
262 reg |= BIT(bank_pin_num);
263 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
264
265 /* configure the output enable reg for the pin */
266 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
267 reg |= BIT(bank_pin_num);
268 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
269
270 /* set the state of the pin */
271 zynq_gpio_set_value(chip, pin, state);
272 return 0;
273}
274
275/**
276 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
277 * @irq_data: per irq and chip data passed down to chip functions
278 *
279 * This function calculates gpio pin number from irq number and sets the
280 * bit in the Interrupt Disable register of the corresponding bank to disable
281 * interrupts for that pin.
282 */
283static void zynq_gpio_irq_mask(struct irq_data *irq_data)
284{
285 unsigned int device_pin_num, bank_num, bank_pin_num;
286 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
287
288 device_pin_num = irq_data->hwirq;
289 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
290 writel_relaxed(BIT(bank_pin_num),
291 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
292}
293
294/**
295 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
296 * @irq_data: irq data containing irq number of gpio pin for the interrupt
297 * to enable
298 *
299 * This function calculates the gpio pin number from irq number and sets the
300 * bit in the Interrupt Enable register of the corresponding bank to enable
301 * interrupts for that pin.
302 */
303static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
304{
305 unsigned int device_pin_num, bank_num, bank_pin_num;
306 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
307
308 device_pin_num = irq_data->hwirq;
309 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
310 writel_relaxed(BIT(bank_pin_num),
311 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
312}
313
190dc2e6
LPC		 314/**
315 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
316 * @irq_data: irq data containing irq number of gpio pin for the interrupt
317 * to ack
318 *
319 * This function calculates gpio pin number from irq number and sets the bit
320 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
321 */
322static void zynq_gpio_irq_ack(struct irq_data *irq_data)
323{
324 unsigned int device_pin_num, bank_num, bank_pin_num;
325 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
326
327 device_pin_num = irq_data->hwirq;
328 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
329 writel_relaxed(BIT(bank_pin_num),
330 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
331}
332
333/**
334 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
335 * @irq_data: irq data containing irq number of gpio pin for the interrupt
336 * to enable
337 *
338 * Clears the INTSTS bit and unmasks the given interrrupt.
339 */
340static void zynq_gpio_irq_enable(struct irq_data *irq_data)
341{
342 /*
343 * The Zynq GPIO controller does not disable interrupt detection when
344 * the interrupt is masked and only disables the propagation of the
345 * interrupt. This means when the controller detects an interrupt
346 * condition while the interrupt is logically disabled it will propagate
347 * that interrupt event once the interrupt is enabled. This will cause
348 * the interrupt consumer to see spurious interrupts to prevent this
349 * first make sure that the interrupt is not asserted and then enable
350 * it.
351 */
352 zynq_gpio_irq_ack(irq_data);
353 zynq_gpio_irq_unmask(irq_data);
354}
355
3242ba11
HK		 356/**
357 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
358 * @irq_data: irq data containing irq number of gpio pin
359 * @type: interrupt type that is to be set for the gpio pin
360 *
361 * This function gets the gpio pin number and its bank from the gpio pin number
362 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
363 *
364 * Return: 0, negative error otherwise.
365 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
366 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
367 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
368 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
369 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
370 */
371static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
372{
373 u32 int_type, int_pol, int_any;
374 unsigned int device_pin_num, bank_num, bank_pin_num;
375 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
376
377 device_pin_num = irq_data->hwirq;
378 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
379
380 int_type = readl_relaxed(gpio->base_addr +
381 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
382 int_pol = readl_relaxed(gpio->base_addr +
383 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
384 int_any = readl_relaxed(gpio->base_addr +
385 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
386
387 /*
388 * based on the type requested, configure the INT_TYPE, INT_POLARITY
389 * and INT_ANY registers
390 */
391 switch (type) {
392 case IRQ_TYPE_EDGE_RISING:
393 int_type |= BIT(bank_pin_num);
394 int_pol |= BIT(bank_pin_num);
395 int_any &= ~BIT(bank_pin_num);
396 break;
397 case IRQ_TYPE_EDGE_FALLING:
398 int_type |= BIT(bank_pin_num);
399 int_pol &= ~BIT(bank_pin_num);
400 int_any &= ~BIT(bank_pin_num);
401 break;
402 case IRQ_TYPE_EDGE_BOTH:
403 int_type |= BIT(bank_pin_num);
404 int_any |= BIT(bank_pin_num);
405 break;
406 case IRQ_TYPE_LEVEL_HIGH:
407 int_type &= ~BIT(bank_pin_num);
408 int_pol |= BIT(bank_pin_num);
409 break;
410 case IRQ_TYPE_LEVEL_LOW:
411 int_type &= ~BIT(bank_pin_num);
412 int_pol &= ~BIT(bank_pin_num);
413 break;
414 default:
415 return -EINVAL;
416 }
417
418 writel_relaxed(int_type,
419 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
420 writel_relaxed(int_pol,
421 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
422 writel_relaxed(int_any,
423 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
6dd85950
LPC		 424
425 if (type & IRQ_TYPE_LEVEL_MASK) {
426 __irq_set_chip_handler_name_locked(irq_data->irq,
427 &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
428 } else {
429 __irq_set_chip_handler_name_locked(irq_data->irq,
430 &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
431 }
432
3242ba11
HK		 433 return 0;
434}
435
436static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
437{
59e22114
ES		 438 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(data);
439
440 irq_set_irq_wake(gpio->irq, on);
3242ba11
HK		 441
442 return 0;
443}
444
445/* irq chip descriptor */
6dd85950 446static struct irq_chip zynq_gpio_level_irqchip = {
3242ba11 447 .name = DRIVER_NAME,
190dc2e6 448 .irq_enable = zynq_gpio_irq_enable,
6dd85950
LPC		 449 .irq_eoi = zynq_gpio_irq_ack,
450 .irq_mask = zynq_gpio_irq_mask,
451 .irq_unmask = zynq_gpio_irq_unmask,
452 .irq_set_type = zynq_gpio_set_irq_type,
453 .irq_set_wake = zynq_gpio_set_wake,
a1946778
ES		 454 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
455 IRQCHIP_MASK_ON_SUSPEND,
6dd85950
LPC		 456};
457
458static struct irq_chip zynq_gpio_edge_irqchip = {
459 .name = DRIVER_NAME,
460 .irq_enable = zynq_gpio_irq_enable,
461 .irq_ack = zynq_gpio_irq_ack,
3242ba11
HK		 462 .irq_mask = zynq_gpio_irq_mask,
463 .irq_unmask = zynq_gpio_irq_unmask,
464 .irq_set_type = zynq_gpio_set_irq_type,
465 .irq_set_wake = zynq_gpio_set_wake,
a1946778 466 .flags = IRQCHIP_MASK_ON_SUSPEND,
3242ba11
HK		 467};
468
5a2533a7
LPC		 469static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
470 unsigned int bank_num,
471 unsigned long pending)
472{
016da144 473 unsigned int bank_offset = zynq_gpio_bank_offset[bank_num];
5a2533a7
LPC		 474 struct irq_domain *irqdomain = gpio->chip.irqdomain;
475 int offset;
476
477 if (!pending)
478 return;
479
480 for_each_set_bit(offset, &pending, 32) {
481 unsigned int gpio_irq;
482
016da144 483 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
5a2533a7
LPC		 484 generic_handle_irq(gpio_irq);
485 }
486}
487
3242ba11
HK		 488/**
489 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
490 * @irq: irq number of the gpio bank where interrupt has occurred
491 * @desc: irq descriptor instance of the 'irq'
492 *
493 * This function reads the Interrupt Status Register of each bank to get the
494 * gpio pin number which has triggered an interrupt. It then acks the triggered
495 * interrupt and calls the pin specific handler set by the higher layer
496 * application for that pin.
497 * Note: A bug is reported if no handler is set for the gpio pin.
498 */
499static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
500{
501 u32 int_sts, int_enb;
502 unsigned int bank_num;
503 struct zynq_gpio *gpio = irq_get_handler_data(irq);
504 struct irq_chip *irqchip = irq_desc_get_chip(desc);
505
506 chained_irq_enter(irqchip, desc);
507
508 for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) {
509 int_sts = readl_relaxed(gpio->base_addr +
510 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
511 int_enb = readl_relaxed(gpio->base_addr +
512 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
5a2533a7 513 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
3242ba11
HK		 514 }
515
516 chained_irq_exit(irqchip, desc);
517}
518
519static int __maybe_unused zynq_gpio_suspend(struct device *dev)
520{
59e22114
ES		 521 struct platform_device *pdev = to_platform_device(dev);
522 int irq = platform_get_irq(pdev, 0);
523 struct irq_data *data = irq_get_irq_data(irq);
524
525 if (!irqd_is_wakeup_set(data))
3242ba11
HK		 526 return pm_runtime_force_suspend(dev);
527
528 return 0;
529}
530
531static int __maybe_unused zynq_gpio_resume(struct device *dev)
532{
59e22114
ES		 533 struct platform_device *pdev = to_platform_device(dev);
534 int irq = platform_get_irq(pdev, 0);
535 struct irq_data *data = irq_get_irq_data(irq);
536
537 if (!irqd_is_wakeup_set(data))
3242ba11
HK		 538 return pm_runtime_force_resume(dev);
539
540 return 0;
541}
542
543static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
544{
545 struct platform_device *pdev = to_platform_device(dev);
546 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
547
548 clk_disable_unprepare(gpio->clk);
549
550 return 0;
551}
552
553static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
554{
555 struct platform_device *pdev = to_platform_device(dev);
556 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
557
558 return clk_prepare_enable(gpio->clk);
559}
560
561static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
562{
563 int ret;
564
565 ret = pm_runtime_get_sync(chip->dev);
566
567 /*
568 * If the device is already active pm_runtime_get() will return 1 on
569 * success, but gpio_request still needs to return 0.
570 */
571 return ret < 0 ? ret : 0;
572}
573
574static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
575{
576 pm_runtime_put(chip->dev);
577}
578
579static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
580 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
6ed23b80 581 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
3242ba11
HK		 582 zynq_gpio_runtime_resume, NULL)
583};
584
585/**
586 * zynq_gpio_probe - Initialization method for a zynq_gpio device
587 * @pdev: platform device instance
588 *
589 * This function allocates memory resources for the gpio device and registers
590 * all the banks of the device. It will also set up interrupts for the gpio
591 * pins.
592 * Note: Interrupts are disabled for all the banks during initialization.
593 *
594 * Return: 0 on success, negative error otherwise.
595 */
596static int zynq_gpio_probe(struct platform_device *pdev)
597{
59e22114 598 int ret, bank_num;
3242ba11
HK		 599 struct zynq_gpio *gpio;
600 struct gpio_chip *chip;
601 struct resource *res;
602
603 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
604 if (!gpio)
605 return -ENOMEM;
606
607 platform_set_drvdata(pdev, gpio);
608
609 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
610 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
611 if (IS_ERR(gpio->base_addr))
612 return PTR_ERR(gpio->base_addr);
613
59e22114
ES		 614 gpio->irq = platform_get_irq(pdev, 0);
615 if (gpio->irq < 0) {
3242ba11 616 dev_err(&pdev->dev, "invalid IRQ\n");
59e22114 617 return gpio->irq;
3242ba11
HK		 618 }
619
620 /* configure the gpio chip */
621 chip = &gpio->chip;
622 chip->label = "zynq_gpio";
623 chip->owner = THIS_MODULE;
624 chip->dev = &pdev->dev;
625 chip->get = zynq_gpio_get_value;
626 chip->set = zynq_gpio_set_value;
627 chip->request = zynq_gpio_request;
628 chip->free = zynq_gpio_free;
629 chip->direction_input = zynq_gpio_dir_in;
630 chip->direction_output = zynq_gpio_dir_out;
631 chip->base = -1;
632 chip->ngpio = ZYNQ_GPIO_NR_GPIOS;
633
634 /* Enable GPIO clock */
635 gpio->clk = devm_clk_get(&pdev->dev, NULL);
636 if (IS_ERR(gpio->clk)) {
637 dev_err(&pdev->dev, "input clock not found.\n");
638 return PTR_ERR(gpio->clk);
639 }
640 ret = clk_prepare_enable(gpio->clk);
641 if (ret) {
642 dev_err(&pdev->dev, "Unable to enable clock.\n");
643 return ret;
644 }
645
646 /* report a bug if gpio chip registration fails */
647 ret = gpiochip_add(chip);
648 if (ret) {
649 dev_err(&pdev->dev, "Failed to add gpio chip\n");
650 goto err_disable_clk;
651 }
652
653 /* disable interrupts for all banks */
654 for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++)
655 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
656 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
657
6dd85950
LPC		 658 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
659 handle_level_irq, IRQ_TYPE_NONE);
3242ba11
HK		 660 if (ret) {
661 dev_err(&pdev->dev, "Failed to add irq chip\n");
662 goto err_rm_gpiochip;
663 }
664
59e22114 665 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
3242ba11
HK		 666 zynq_gpio_irqhandler);
667
668 pm_runtime_set_active(&pdev->dev);
669 pm_runtime_enable(&pdev->dev);
670
3242ba11
HK		 671 return 0;
672
673err_rm_gpiochip:
88d5e520 674 gpiochip_remove(chip);
3242ba11
HK		 675err_disable_clk:
676 clk_disable_unprepare(gpio->clk);
677
678 return ret;
679}
680
681/**
682 * zynq_gpio_remove - Driver removal function
683 * @pdev: platform device instance
684 *
685 * Return: 0 always
686 */
687static int zynq_gpio_remove(struct platform_device *pdev)
688{
3242ba11
HK		 689 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
690
691 pm_runtime_get_sync(&pdev->dev);
da26d5d8 692 gpiochip_remove(&gpio->chip);
3242ba11
HK		 693 clk_disable_unprepare(gpio->clk);
694 device_set_wakeup_capable(&pdev->dev, 0);
695 return 0;
696}
697
698static struct of_device_id zynq_gpio_of_match[] = {
699 { .compatible = "xlnx,zynq-gpio-1.0", },
700 { /* end of table */ }
701};
702MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
703
704static struct platform_driver zynq_gpio_driver = {
705 .driver = {
706 .name = DRIVER_NAME,
3242ba11
HK		 707 .pm = &zynq_gpio_dev_pm_ops,
708 .of_match_table = zynq_gpio_of_match,
709 },
710 .probe = zynq_gpio_probe,
711 .remove = zynq_gpio_remove,
712};
713
714/**
715 * zynq_gpio_init - Initial driver registration call
716 *
717 * Return: value from platform_driver_register
718 */
719static int __init zynq_gpio_init(void)
720{
721 return platform_driver_register(&zynq_gpio_driver);
722}
723postcore_initcall(zynq_gpio_init);
724
725MODULE_AUTHOR("Xilinx Inc.");
726MODULE_DESCRIPTION("Zynq GPIO driver");
727MODULE_LICENSE("GPL");
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