]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpio/gpio-zynq.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gpio: zynq: Add support for suspend resume
[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-zynq.c
CommitLineData
3242ba11
HK		 1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
9 * version.
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
bdf7a4ae 21#include <linux/of.h>
3242ba11
HK		 22
23#define DRIVER_NAME "zynq-gpio"
24
25/* Maximum banks */
26#define ZYNQ_GPIO_MAX_BANK 4
bdf7a4ae 27#define ZYNQMP_GPIO_MAX_BANK 6
3242ba11
HK		 28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
bdf7a4ae
AKV		 34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
40
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
3242ba11
HK		 62
63
64/* Register offsets for the GPIO device */
65/* LSW Mask & Data -WO */
66#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
67/* MSW Mask & Data -WO */
68#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
69/* Data Register-RW */
70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */
72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
73/* Output enable reg-RW */
74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
75/* Interrupt mask reg-RO */
76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
77/* Interrupt enable reg-WO */
78#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
79/* Interrupt disable reg-WO */
80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
81/* Interrupt status reg-RO */
82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
83/* Interrupt type reg-RW */
84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
85/* Interrupt polarity reg-RW */
86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
87/* Interrupt on any, reg-RW */
88#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
89
90/* Disable all interrupts mask */
91#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
92
93/* Mid pin number of a bank */
94#define ZYNQ_GPIO_MID_PIN_NUM 16
95
96/* GPIO upper 16 bit mask */
97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
98
3638bd4a
SB		 99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
e3296f19 101
e11de4de
SD		 102struct gpio_regs {
103 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
104 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
105 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
106 u32 outen[ZYNQMP_GPIO_MAX_BANK];
107 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
108 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
109 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
110 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
111 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
112};
3242ba11
HK		 113/**
114 * struct zynq_gpio - gpio device private data structure
115 * @chip: instance of the gpio_chip
116 * @base_addr: base address of the GPIO device
117 * @clk: clock resource for this controller
59e22114 118 * @irq: interrupt for the GPIO device
bdf7a4ae 119 * @p_data: pointer to platform data
e11de4de 120 * @context: context registers
3242ba11
HK		 121 */
122struct zynq_gpio {
123 struct gpio_chip chip;
124 void __iomem *base_addr;
125 struct clk *clk;
59e22114 126 int irq;
bdf7a4ae 127 const struct zynq_platform_data *p_data;
e11de4de 128 struct gpio_regs context;
bdf7a4ae
AKV		 129};
130
131/**
132 * struct zynq_platform_data - zynq gpio platform data structure
133 * @label: string to store in gpio->label
134 * @ngpio: max number of gpio pins
135 * @max_bank: maximum number of gpio banks
136 * @bank_min: this array represents bank's min pin
137 * @bank_max: this array represents bank's max pin
138*/
139struct zynq_platform_data {
140 const char *label;
e3296f19 141 u32 quirks;
bdf7a4ae
AKV		 142 u16 ngpio;
143 int max_bank;
144 int bank_min[ZYNQMP_GPIO_MAX_BANK];
145 int bank_max[ZYNQMP_GPIO_MAX_BANK];
3242ba11
HK		 146};
147
6dd85950
LPC		 148static struct irq_chip zynq_gpio_level_irqchip;
149static struct irq_chip zynq_gpio_edge_irqchip;
fa9795d1 150
3638bd4a
SB		 151/**
152 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
153 * @gpio: Pointer to driver data struct
154 *
155 * Return: 0 if zynqmp, 1 if zynq.
156 */
157static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
158{
159 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
160}
161
3242ba11
HK		 162/**
163 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
164 * for a given pin in the GPIO device
165 * @pin_num: gpio pin number within the device
166 * @bank_num: an output parameter used to return the bank number of the gpio
167 * pin
168 * @bank_pin_num: an output parameter used to return pin number within a bank
169 * for the given gpio pin
170 *
171 * Returns the bank number and pin offset within the bank.
172 */
173static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
174 unsigned int *bank_num,
bdf7a4ae
AKV		 175 unsigned int *bank_pin_num,
176 struct zynq_gpio *gpio)
3242ba11 177{
bdf7a4ae
AKV		 178 int bank;
179
180 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
181 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
182 (pin_num <= gpio->p_data->bank_max[bank])) {
183 *bank_num = bank;
184 *bank_pin_num = pin_num -
185 gpio->p_data->bank_min[bank];
186 return;
187 }
3242ba11 188 }
3242ba11 189
bdf7a4ae
AKV		 190 /* default */
191 WARN(true, "invalid GPIO pin number: %u", pin_num);
192 *bank_num = 0;
193 *bank_pin_num = 0;
194}
016da144 195
3242ba11
HK		 196/**
197 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
198 * @chip: gpio_chip instance to be worked on
199 * @pin: gpio pin number within the device
200 *
201 * This function reads the state of the specified pin of the GPIO device.
202 *
203 * Return: 0 if the pin is low, 1 if pin is high.
204 */
205static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
206{
207 u32 data;
208 unsigned int bank_num, bank_pin_num;
31a89447 209 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 210
bdf7a4ae 211 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 212
213 data = readl_relaxed(gpio->base_addr +
214 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
215
216 return (data >> bank_pin_num) & 1;
217}
218
219/**
220 * zynq_gpio_set_value - Modify the state of the pin with specified value
221 * @chip: gpio_chip instance to be worked on
222 * @pin: gpio pin number within the device
223 * @state: value used to modify the state of the specified pin
224 *
225 * This function calculates the register offset (i.e to lower 16 bits or
226 * upper 16 bits) based on the given pin number and sets the state of a
227 * gpio pin to the specified value. The state is either 0 or non-zero.
228 */
229static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
230 int state)
231{
232 unsigned int reg_offset, bank_num, bank_pin_num;
31a89447 233 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 234
bdf7a4ae 235 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 236
237 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
238 /* only 16 data bits in bit maskable reg */
239 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
240 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
241 } else {
242 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
243 }
244
245 /*
246 * get the 32 bit value to be written to the mask/data register where
247 * the upper 16 bits is the mask and lower 16 bits is the data
248 */
249 state = !!state;
250 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
251 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
252
253 writel_relaxed(state, gpio->base_addr + reg_offset);
254}
255
256/**
257 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
258 * @chip: gpio_chip instance to be worked on
259 * @pin: gpio pin number within the device
260 *
261 * This function uses the read-modify-write sequence to set the direction of
262 * the gpio pin as input.
263 *
264 * Return: 0 always
265 */
266static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
267{
268 u32 reg;
269 unsigned int bank_num, bank_pin_num;
31a89447 270 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 271
bdf7a4ae 272 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11 273
e3296f19
NM		 274 /*
275 * On zynq bank 0 pins 7 and 8 are special and cannot be used
276 * as inputs.
277 */
3638bd4a 278 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
e3296f19 279 (bank_pin_num == 7 || bank_pin_num == 8))
3242ba11
HK		 280 return -EINVAL;
281
282 /* clear the bit in direction mode reg to set the pin as input */
283 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
284 reg &= ~BIT(bank_pin_num);
285 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
286
287 return 0;
288}
289
290/**
291 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
292 * @chip: gpio_chip instance to be worked on
293 * @pin: gpio pin number within the device
294 * @state: value to be written to specified pin
295 *
296 * This function sets the direction of specified GPIO pin as output, configures
297 * the Output Enable register for the pin and uses zynq_gpio_set to set
298 * the state of the pin to the value specified.
299 *
300 * Return: 0 always
301 */
302static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
303 int state)
304{
305 u32 reg;
306 unsigned int bank_num, bank_pin_num;
31a89447 307 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 308
bdf7a4ae 309 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 310
311 /* set the GPIO pin as output */
312 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
313 reg |= BIT(bank_pin_num);
314 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
315
316 /* configure the output enable reg for the pin */
317 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
318 reg |= BIT(bank_pin_num);
319 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
320
321 /* set the state of the pin */
322 zynq_gpio_set_value(chip, pin, state);
323 return 0;
324}
325
326/**
327 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
328 * @irq_data: per irq and chip data passed down to chip functions
329 *
330 * This function calculates gpio pin number from irq number and sets the
331 * bit in the Interrupt Disable register of the corresponding bank to disable
332 * interrupts for that pin.
333 */
334static void zynq_gpio_irq_mask(struct irq_data *irq_data)
335{
336 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 337 struct zynq_gpio *gpio =
31a89447 338 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 339
340 device_pin_num = irq_data->hwirq;
bdf7a4ae 341 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 342 writel_relaxed(BIT(bank_pin_num),
343 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
344}
345
346/**
347 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
348 * @irq_data: irq data containing irq number of gpio pin for the interrupt
349 * to enable
350 *
351 * This function calculates the gpio pin number from irq number and sets the
352 * bit in the Interrupt Enable register of the corresponding bank to enable
353 * interrupts for that pin.
354 */
355static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
356{
357 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 358 struct zynq_gpio *gpio =
31a89447 359 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 360
361 device_pin_num = irq_data->hwirq;
bdf7a4ae 362 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 363 writel_relaxed(BIT(bank_pin_num),
364 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
365}
366
190dc2e6
LPC		 367/**
368 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
369 * @irq_data: irq data containing irq number of gpio pin for the interrupt
370 * to ack
371 *
372 * This function calculates gpio pin number from irq number and sets the bit
373 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
374 */
375static void zynq_gpio_irq_ack(struct irq_data *irq_data)
376{
377 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 378 struct zynq_gpio *gpio =
31a89447 379 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
190dc2e6
LPC		 380
381 device_pin_num = irq_data->hwirq;
bdf7a4ae 382 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
190dc2e6
LPC		 383 writel_relaxed(BIT(bank_pin_num),
384 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
385}
386
387/**
388 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
389 * @irq_data: irq data containing irq number of gpio pin for the interrupt
390 * to enable
391 *
20a8a968 392 * Clears the INTSTS bit and unmasks the given interrupt.
190dc2e6
LPC		 393 */
394static void zynq_gpio_irq_enable(struct irq_data *irq_data)
395{
396 /*
397 * The Zynq GPIO controller does not disable interrupt detection when
398 * the interrupt is masked and only disables the propagation of the
399 * interrupt. This means when the controller detects an interrupt
400 * condition while the interrupt is logically disabled it will propagate
401 * that interrupt event once the interrupt is enabled. This will cause
402 * the interrupt consumer to see spurious interrupts to prevent this
403 * first make sure that the interrupt is not asserted and then enable
404 * it.
405 */
406 zynq_gpio_irq_ack(irq_data);
407 zynq_gpio_irq_unmask(irq_data);
408}
409
3242ba11
HK		 410/**
411 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
412 * @irq_data: irq data containing irq number of gpio pin
413 * @type: interrupt type that is to be set for the gpio pin
414 *
415 * This function gets the gpio pin number and its bank from the gpio pin number
416 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
417 *
418 * Return: 0, negative error otherwise.
419 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
420 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
421 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
422 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
423 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
424 */
425static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
426{
427 u32 int_type, int_pol, int_any;
428 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 429 struct zynq_gpio *gpio =
31a89447 430 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 431
432 device_pin_num = irq_data->hwirq;
bdf7a4ae 433 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 434
435 int_type = readl_relaxed(gpio->base_addr +
436 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
437 int_pol = readl_relaxed(gpio->base_addr +
438 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
439 int_any = readl_relaxed(gpio->base_addr +
440 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
441
442 /*
443 * based on the type requested, configure the INT_TYPE, INT_POLARITY
444 * and INT_ANY registers
445 */
446 switch (type) {
447 case IRQ_TYPE_EDGE_RISING:
448 int_type |= BIT(bank_pin_num);
449 int_pol |= BIT(bank_pin_num);
450 int_any &= ~BIT(bank_pin_num);
451 break;
452 case IRQ_TYPE_EDGE_FALLING:
453 int_type |= BIT(bank_pin_num);
454 int_pol &= ~BIT(bank_pin_num);
455 int_any &= ~BIT(bank_pin_num);
456 break;
457 case IRQ_TYPE_EDGE_BOTH:
458 int_type |= BIT(bank_pin_num);
459 int_any |= BIT(bank_pin_num);
460 break;
461 case IRQ_TYPE_LEVEL_HIGH:
462 int_type &= ~BIT(bank_pin_num);
463 int_pol |= BIT(bank_pin_num);
464 break;
465 case IRQ_TYPE_LEVEL_LOW:
466 int_type &= ~BIT(bank_pin_num);
467 int_pol &= ~BIT(bank_pin_num);
468 break;
469 default:
470 return -EINVAL;
471 }
472
473 writel_relaxed(int_type,
474 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
475 writel_relaxed(int_pol,
476 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
477 writel_relaxed(int_any,
478 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
6dd85950
LPC		 479
480 if (type & IRQ_TYPE_LEVEL_MASK) {
47c08462 481 irq_set_chip_handler_name_locked(irq_data,
6dd85950
LPC		 482 &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
483 } else {
47c08462 484 irq_set_chip_handler_name_locked(irq_data,
6dd85950
LPC		 485 &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
486 }
487
3242ba11
HK		 488 return 0;
489}
490
491static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
492{
fa9795d1 493 struct zynq_gpio *gpio =
31a89447 494 gpiochip_get_data(irq_data_get_irq_chip_data(data));
59e22114
ES		 495
496 irq_set_irq_wake(gpio->irq, on);
3242ba11
HK		 497
498 return 0;
499}
500
501/* irq chip descriptor */
6dd85950 502static struct irq_chip zynq_gpio_level_irqchip = {
3242ba11 503 .name = DRIVER_NAME,
190dc2e6 504 .irq_enable = zynq_gpio_irq_enable,
6dd85950
LPC		 505 .irq_eoi = zynq_gpio_irq_ack,
506 .irq_mask = zynq_gpio_irq_mask,
507 .irq_unmask = zynq_gpio_irq_unmask,
508 .irq_set_type = zynq_gpio_set_irq_type,
509 .irq_set_wake = zynq_gpio_set_wake,
a1946778
ES		 510 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
511 IRQCHIP_MASK_ON_SUSPEND,
6dd85950
LPC		 512};
513
514static struct irq_chip zynq_gpio_edge_irqchip = {
515 .name = DRIVER_NAME,
516 .irq_enable = zynq_gpio_irq_enable,
517 .irq_ack = zynq_gpio_irq_ack,
3242ba11
HK		 518 .irq_mask = zynq_gpio_irq_mask,
519 .irq_unmask = zynq_gpio_irq_unmask,
520 .irq_set_type = zynq_gpio_set_irq_type,
521 .irq_set_wake = zynq_gpio_set_wake,
a1946778 522 .flags = IRQCHIP_MASK_ON_SUSPEND,
3242ba11
HK		 523};
524
5a2533a7
LPC		 525static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
526 unsigned int bank_num,
527 unsigned long pending)
528{
bdf7a4ae 529 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
5a2533a7
LPC		 530 struct irq_domain *irqdomain = gpio->chip.irqdomain;
531 int offset;
532
533 if (!pending)
534 return;
535
536 for_each_set_bit(offset, &pending, 32) {
537 unsigned int gpio_irq;
538
016da144 539 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
5a2533a7
LPC		 540 generic_handle_irq(gpio_irq);
541 }
542}
543
3242ba11
HK		 544/**
545 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
546 * @irq: irq number of the gpio bank where interrupt has occurred
547 * @desc: irq descriptor instance of the 'irq'
548 *
549 * This function reads the Interrupt Status Register of each bank to get the
550 * gpio pin number which has triggered an interrupt. It then acks the triggered
551 * interrupt and calls the pin specific handler set by the higher layer
552 * application for that pin.
553 * Note: A bug is reported if no handler is set for the gpio pin.
554 */
bd0b9ac4 555static void zynq_gpio_irqhandler(struct irq_desc *desc)
3242ba11
HK		 556{
557 u32 int_sts, int_enb;
558 unsigned int bank_num;
fa9795d1 559 struct zynq_gpio *gpio =
31a89447 560 gpiochip_get_data(irq_desc_get_handler_data(desc));
3242ba11
HK		 561 struct irq_chip *irqchip = irq_desc_get_chip(desc);
562
563 chained_irq_enter(irqchip, desc);
564
bdf7a4ae 565 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
3242ba11
HK		 566 int_sts = readl_relaxed(gpio->base_addr +
567 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
568 int_enb = readl_relaxed(gpio->base_addr +
569 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
5a2533a7 570 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
3242ba11
HK		 571 }
572
573 chained_irq_exit(irqchip, desc);
574}
575
e11de4de
SD		 576static void zynq_gpio_save_context(struct zynq_gpio *gpio)
577{
578 unsigned int bank_num;
579
580 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
581 gpio->context.datalsw[bank_num] =
582 readl_relaxed(gpio->base_addr +
583 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
584 gpio->context.datamsw[bank_num] =
585 readl_relaxed(gpio->base_addr +
586 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
587 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
588 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
589 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
590 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
591 gpio->context.int_type[bank_num] =
592 readl_relaxed(gpio->base_addr +
593 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
594 gpio->context.int_polarity[bank_num] =
595 readl_relaxed(gpio->base_addr +
596 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
597 gpio->context.int_any[bank_num] =
598 readl_relaxed(gpio->base_addr +
599 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
600 }
601}
602
603static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
604{
605 unsigned int bank_num;
606
607 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
608 writel_relaxed(gpio->context.datalsw[bank_num],
609 gpio->base_addr +
610 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
611 writel_relaxed(gpio->context.datamsw[bank_num],
612 gpio->base_addr +
613 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
614 writel_relaxed(gpio->context.dirm[bank_num],
615 gpio->base_addr +
616 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
617 writel_relaxed(gpio->context.int_en[bank_num],
618 gpio->base_addr +
619 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
620 writel_relaxed(gpio->context.int_type[bank_num],
621 gpio->base_addr +
622 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
623 writel_relaxed(gpio->context.int_polarity[bank_num],
624 gpio->base_addr +
625 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
626 writel_relaxed(gpio->context.int_any[bank_num],
627 gpio->base_addr +
628 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
629 }
630}
3242ba11
HK		 631static int __maybe_unused zynq_gpio_suspend(struct device *dev)
632{
59e22114
ES		 633 struct platform_device *pdev = to_platform_device(dev);
634 int irq = platform_get_irq(pdev, 0);
635 struct irq_data *data = irq_get_irq_data(irq);
e11de4de 636 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
59e22114 637
e11de4de
SD		 638 if (!irqd_is_wakeup_set(data)) {
639 zynq_gpio_save_context(gpio);
3242ba11 640 return pm_runtime_force_suspend(dev);
e11de4de 641 }
3242ba11
HK		 642
643 return 0;
644}
645
646static int __maybe_unused zynq_gpio_resume(struct device *dev)
647{
59e22114
ES		 648 struct platform_device *pdev = to_platform_device(dev);
649 int irq = platform_get_irq(pdev, 0);
650 struct irq_data *data = irq_get_irq_data(irq);
e11de4de
SD		 651 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
652 int ret;
59e22114 653
e11de4de
SD		 654 if (!irqd_is_wakeup_set(data)) {
655 ret = pm_runtime_force_resume(dev);
656 zynq_gpio_restore_context(gpio);
657 return ret;
658 }
3242ba11
HK		 659
660 return 0;
661}
662
663static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
664{
665 struct platform_device *pdev = to_platform_device(dev);
666 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
667
668 clk_disable_unprepare(gpio->clk);
669
670 return 0;
671}
672
673static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
674{
675 struct platform_device *pdev = to_platform_device(dev);
676 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
677
678 return clk_prepare_enable(gpio->clk);
679}
680
681static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
682{
683 int ret;
684
58383c78 685 ret = pm_runtime_get_sync(chip->parent);
3242ba11
HK		 686
687 /*
688 * If the device is already active pm_runtime_get() will return 1 on
689 * success, but gpio_request still needs to return 0.
690 */
691 return ret < 0 ? ret : 0;
692}
693
694static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
695{
58383c78 696 pm_runtime_put(chip->parent);
3242ba11
HK		 697}
698
699static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
700 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
6ed23b80 701 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
3242ba11
HK		 702 zynq_gpio_runtime_resume, NULL)
703};
704
bdf7a4ae
AKV		 705static const struct zynq_platform_data zynqmp_gpio_def = {
706 .label = "zynqmp_gpio",
707 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
708 .max_bank = ZYNQMP_GPIO_MAX_BANK,
709 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
710 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
711 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
712 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
713 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
714 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
715 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
716 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
717 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
718 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
719 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
720 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
721};
722
723static const struct zynq_platform_data zynq_gpio_def = {
724 .label = "zynq_gpio",
3638bd4a 725 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ,
bdf7a4ae
AKV		 726 .ngpio = ZYNQ_GPIO_NR_GPIOS,
727 .max_bank = ZYNQ_GPIO_MAX_BANK,
728 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
729 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
730 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
731 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
732 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
733 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
734 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
735 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
736};
737
738static const struct of_device_id zynq_gpio_of_match[] = {
7808c42b
MY		 739 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
740 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
bdf7a4ae
AKV		 741 { /* end of table */ }
742};
743MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
744
3242ba11
HK		 745/**
746 * zynq_gpio_probe - Initialization method for a zynq_gpio device
747 * @pdev: platform device instance
748 *
749 * This function allocates memory resources for the gpio device and registers
750 * all the banks of the device. It will also set up interrupts for the gpio
751 * pins.
752 * Note: Interrupts are disabled for all the banks during initialization.
753 *
754 * Return: 0 on success, negative error otherwise.
755 */
756static int zynq_gpio_probe(struct platform_device *pdev)
757{
59e22114 758 int ret, bank_num;
3242ba11
HK		 759 struct zynq_gpio *gpio;
760 struct gpio_chip *chip;
761 struct resource *res;
bdf7a4ae 762 const struct of_device_id *match;
3242ba11
HK		 763
764 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
765 if (!gpio)
766 return -ENOMEM;
767
bdf7a4ae
AKV		 768 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
769 if (!match) {
770 dev_err(&pdev->dev, "of_match_node() failed\n");
771 return -EINVAL;
772 }
773 gpio->p_data = match->data;
3242ba11
HK		 774 platform_set_drvdata(pdev, gpio);
775
776 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
777 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
778 if (IS_ERR(gpio->base_addr))
779 return PTR_ERR(gpio->base_addr);
780
59e22114
ES		 781 gpio->irq = platform_get_irq(pdev, 0);
782 if (gpio->irq < 0) {
3242ba11 783 dev_err(&pdev->dev, "invalid IRQ\n");
59e22114 784 return gpio->irq;
3242ba11
HK		 785 }
786
787 /* configure the gpio chip */
788 chip = &gpio->chip;
bdf7a4ae 789 chip->label = gpio->p_data->label;
3242ba11 790 chip->owner = THIS_MODULE;
58383c78 791 chip->parent = &pdev->dev;
3242ba11
HK		 792 chip->get = zynq_gpio_get_value;
793 chip->set = zynq_gpio_set_value;
794 chip->request = zynq_gpio_request;
795 chip->free = zynq_gpio_free;
796 chip->direction_input = zynq_gpio_dir_in;
797 chip->direction_output = zynq_gpio_dir_out;
798 chip->base = -1;
bdf7a4ae 799 chip->ngpio = gpio->p_data->ngpio;
3242ba11 800
3773c195 801 /* Retrieve GPIO clock */
3242ba11
HK		 802 gpio->clk = devm_clk_get(&pdev->dev, NULL);
803 if (IS_ERR(gpio->clk)) {
804 dev_err(&pdev->dev, "input clock not found.\n");
805 return PTR_ERR(gpio->clk);
806 }
0f84f29f
HG		 807 ret = clk_prepare_enable(gpio->clk);
808 if (ret) {
809 dev_err(&pdev->dev, "Unable to enable clock.\n");
810 return ret;
811 }
3773c195 812
0f84f29f 813 pm_runtime_set_active(&pdev->dev);
3773c195
MS		 814 pm_runtime_enable(&pdev->dev);
815 ret = pm_runtime_get_sync(&pdev->dev);
816 if (ret < 0)
615d23f8 817 goto err_pm_dis;
3242ba11
HK		 818
819 /* report a bug if gpio chip registration fails */
31a89447 820 ret = gpiochip_add_data(chip, gpio);
3242ba11
HK		 821 if (ret) {
822 dev_err(&pdev->dev, "Failed to add gpio chip\n");
3773c195 823 goto err_pm_put;
3242ba11
HK		 824 }
825
826 /* disable interrupts for all banks */
bdf7a4ae 827 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
3242ba11
HK		 828 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
829 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
830
6dd85950
LPC		 831 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
832 handle_level_irq, IRQ_TYPE_NONE);
3242ba11
HK		 833 if (ret) {
834 dev_err(&pdev->dev, "Failed to add irq chip\n");
835 goto err_rm_gpiochip;
836 }
837
59e22114 838 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
3242ba11
HK		 839 zynq_gpio_irqhandler);
840
3773c195 841 pm_runtime_put(&pdev->dev);
3242ba11 842
3242ba11
HK		 843 return 0;
844
845err_rm_gpiochip:
88d5e520 846 gpiochip_remove(chip);
3773c195
MS		 847err_pm_put:
848 pm_runtime_put(&pdev->dev);
615d23f8
SD		 849err_pm_dis:
850 pm_runtime_disable(&pdev->dev);
0f84f29f 851 clk_disable_unprepare(gpio->clk);
3242ba11
HK		 852
853 return ret;
854}
855
856/**
857 * zynq_gpio_remove - Driver removal function
858 * @pdev: platform device instance
859 *
860 * Return: 0 always
861 */
862static int zynq_gpio_remove(struct platform_device *pdev)
863{
3242ba11
HK		 864 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
865
866 pm_runtime_get_sync(&pdev->dev);
da26d5d8 867 gpiochip_remove(&gpio->chip);
3242ba11
HK		 868 clk_disable_unprepare(gpio->clk);
869 device_set_wakeup_capable(&pdev->dev, 0);
6b956af0 870 pm_runtime_disable(&pdev->dev);
3242ba11
HK		 871 return 0;
872}
873
3242ba11
HK		 874static struct platform_driver zynq_gpio_driver = {
875 .driver = {
876 .name = DRIVER_NAME,
3242ba11
HK		 877 .pm = &zynq_gpio_dev_pm_ops,
878 .of_match_table = zynq_gpio_of_match,
879 },
880 .probe = zynq_gpio_probe,
881 .remove = zynq_gpio_remove,
882};
883
884/**
885 * zynq_gpio_init - Initial driver registration call
886 *
887 * Return: value from platform_driver_register
888 */
889static int __init zynq_gpio_init(void)
890{
891 return platform_driver_register(&zynq_gpio_driver);
892}
893postcore_initcall(zynq_gpio_init);
894
80d2bf55
MY		 895static void __exit zynq_gpio_exit(void)
896{
897 platform_driver_unregister(&zynq_gpio_driver);
898}
899module_exit(zynq_gpio_exit);
900
3242ba11
HK		 901MODULE_AUTHOR("Xilinx Inc.");
902MODULE_DESCRIPTION("Zynq GPIO driver");
903MODULE_LICENSE("GPL");
ubuntu-bionic-kernel mirror