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drm/amdgpu/atomfirmware: use proper index for querying vram type (v3)
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
8290268f
CK		 31#include "amdgpu_ctx.h"
32
97b2e202
AD		 33#include <linux/atomic.h>
34#include <linux/wait.h>
35#include <linux/list.h>
36#include <linux/kref.h>
a9f87f64 37#include <linux/rbtree.h>
97b2e202 38#include <linux/hashtable.h>
f54d1867 39#include <linux/dma-fence.h>
97b2e202 40
248a1d6f
MY		 41#include <drm/ttm/ttm_bo_api.h>
42#include <drm/ttm/ttm_bo_driver.h>
43#include <drm/ttm/ttm_placement.h>
44#include <drm/ttm/ttm_module.h>
45#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 46
7e5a547f 47#include <drm/amdgpu_drm.h>
f867723b
SR		 48#include <drm/drm_gem.h>
49#include <drm/drm_ioctl.h>
1b1f42d8 50#include <drm/gpu_scheduler.h>
97b2e202 51
78c16834 52#include <kgd_kfd_interface.h>
c79563a3
RZ		 53#include "dm_pp_interface.h"
54#include "kgd_pp_interface.h"
78c16834 55
5fc3aeeb 56#include "amd_shared.h"
97b2e202
AD		 57#include "amdgpu_mode.h"
58#include "amdgpu_ih.h"
59#include "amdgpu_irq.h"
60#include "amdgpu_ucode.h"
c632d799 61#include "amdgpu_ttm.h"
0e5ca0d1 62#include "amdgpu_psp.h"
97b2e202 63#include "amdgpu_gds.h"
56113504 64#include "amdgpu_sync.h"
78023016 65#include "amdgpu_ring.h"
073440d2 66#include "amdgpu_vm.h"
cf097881 67#include "amdgpu_dpm.h"
a8fe58ce 68#include "amdgpu_acp.h"
4df654d2 69#include "amdgpu_uvd.h"
5e568178 70#include "amdgpu_vce.h"
95aa13f6 71#include "amdgpu_vcn.h"
9a189996 72#include "amdgpu_mn.h"
770d13b1 73#include "amdgpu_gmc.h"
448fe192 74#include "amdgpu_gfx.h"
bb7743bc 75#include "amdgpu_sdma.h"
bebc0762 76#include "amdgpu_nbio.h"
4562236b 77#include "amdgpu_dm.h"
ceeb50ed 78#include "amdgpu_virt.h"
7946340f 79#include "amdgpu_csa.h"
3490bdb5 80#include "amdgpu_gart.h"
75758255 81#include "amdgpu_debugfs.h"
050d9d43 82#include "amdgpu_job.h"
4a8c21a1 83#include "amdgpu_bo_list.h"
2cddc50e 84#include "amdgpu_gem.h"
cde577bd 85#include "amdgpu_doorbell.h"
611736d8 86#include "amdgpu_amdkfd.h"
137d63ab 87#include "amdgpu_smu.h"
f39f5bb1 88#include "amdgpu_discovery.h"
a538bbe7 89#include "amdgpu_mes.h"
9e585a52 90#include "amdgpu_umc.h"
3d093da0 91#include "amdgpu_mmhub.h"
c79563a3 92
62d73fbc
EQ		 93#define MAX_GPU_INSTANCE 16
94
95struct amdgpu_gpu_instance
96{
97 struct amdgpu_device *adev;
98 int mgpu_fan_enabled;
99};
100
101struct amdgpu_mgpu_info
102{
103 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
104 struct mutex mutex;
105 uint32_t num_gpu;
106 uint32_t num_dgpu;
107 uint32_t num_apu;
108};
109
97b2e202
AD		 110/*
111 * Modules parameters.
112 */
113extern int amdgpu_modeset;
114extern int amdgpu_vram_limit;
218b5dcd 115extern int amdgpu_vis_vram_limit;
83e74db6 116extern int amdgpu_gart_size;
36d38372 117extern int amdgpu_gtt_size;
95844d20 118extern int amdgpu_moverate;
97b2e202
AD		 119extern int amdgpu_benchmarking;
120extern int amdgpu_testing;
121extern int amdgpu_audio;
122extern int amdgpu_disp_priority;
123extern int amdgpu_hw_i2c;
124extern int amdgpu_pcie_gen2;
125extern int amdgpu_msi;
97b2e202 126extern int amdgpu_dpm;
e635ee07 127extern int amdgpu_fw_load_type;
97b2e202
AD		 128extern int amdgpu_aspm;
129extern int amdgpu_runtime_pm;
0b693f0b 130extern uint amdgpu_ip_block_mask;
97b2e202
AD		 131extern int amdgpu_bapm;
132extern int amdgpu_deep_color;
133extern int amdgpu_vm_size;
134extern int amdgpu_vm_block_size;
d07f14be 135extern int amdgpu_vm_fragment_size;
d9c13156 136extern int amdgpu_vm_fault_stop;
b495bd3a 137extern int amdgpu_vm_debug;
9a4b7d4c 138extern int amdgpu_vm_update_mode;
4562236b 139extern int amdgpu_dc;
1333f723 140extern int amdgpu_sched_jobs;
4afcb303 141extern int amdgpu_sched_hw_submission;
0b693f0b
RZ		 142extern uint amdgpu_pcie_gen_cap;
143extern uint amdgpu_pcie_lane_cap;
144extern uint amdgpu_cg_mask;
145extern uint amdgpu_pg_mask;
146extern uint amdgpu_sdma_phase_quantum;
6f8941a2 147extern char *amdgpu_disable_cu;
9accf2fd 148extern char *amdgpu_virtual_display;
0b693f0b 149extern uint amdgpu_pp_feature_mask;
bce23e00
AD		 150extern int amdgpu_ngg;
151extern int amdgpu_prim_buf_per_se;
152extern int amdgpu_pos_buf_per_se;
153extern int amdgpu_cntl_sb_buf_per_se;
154extern int amdgpu_param_buf_per_se;
65781c78 155extern int amdgpu_job_hang_limit;
e8835e0e 156extern int amdgpu_lbpw;
4a75aefe 157extern int amdgpu_compute_multipipe;
dcebf026 158extern int amdgpu_gpu_recovery;
bfca0289 159extern int amdgpu_emu_mode;
7951e376 160extern uint amdgpu_smu_memory_pool_size;
7875a226 161extern uint amdgpu_dc_feature_mask;
ad4de27f 162extern uint amdgpu_dm_abm_level;
62d73fbc 163extern struct amdgpu_mgpu_info mgpu_info;
1218252f 164extern int amdgpu_ras_enable;
165extern uint amdgpu_ras_mask;
51bcce46 166extern int amdgpu_async_gfx_ring;
b239c017 167extern int amdgpu_mcbp;
a190d1c7 168extern int amdgpu_discovery;
38487284 169extern int amdgpu_mes;
75ee6487 170extern int amdgpu_noretry;
4e66d7d2 171extern int amdgpu_force_asic_type;
8c9f69bc 172#ifdef CONFIG_HSA_AMD
aa978594 173extern int sched_policy;
a35ad98b
S		 174#else
175static const int sched_policy = KFD_SCHED_POLICY_HWS;
8c9f69bc 176#endif
97b2e202 177
6dd13096
FK		 178#ifdef CONFIG_DRM_AMDGPU_SI
179extern int amdgpu_si_support;
180#endif
7df28986
FK		 181#ifdef CONFIG_DRM_AMDGPU_CIK
182extern int amdgpu_cik_support;
183#endif
97b2e202 184
08d1bdd4 185#define AMDGPU_VM_MAX_NUM_CTX 4096
6c8d74ca 186#define AMDGPU_SG_THRESHOLD (256*1024*1024)
55ed8caf 187#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 188#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202 189#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
8c5e13ec 190#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
97b2e202
AD		 191/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
192#define AMDGPU_IB_POOL_SIZE 16
193#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
194#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 195#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 196
97b2e202
AD		 197/* hard reset data */
198#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
199
200/* reset flags */
201#define AMDGPU_RESET_GFX (1 << 0)
202#define AMDGPU_RESET_COMPUTE (1 << 1)
203#define AMDGPU_RESET_DMA (1 << 2)
204#define AMDGPU_RESET_CP (1 << 3)
205#define AMDGPU_RESET_GRBM (1 << 4)
206#define AMDGPU_RESET_DMA1 (1 << 5)
207#define AMDGPU_RESET_RLC (1 << 6)
208#define AMDGPU_RESET_SEM (1 << 7)
209#define AMDGPU_RESET_IH (1 << 8)
210#define AMDGPU_RESET_VMC (1 << 9)
211#define AMDGPU_RESET_MC (1 << 10)
212#define AMDGPU_RESET_DISPLAY (1 << 11)
213#define AMDGPU_RESET_UVD (1 << 12)
214#define AMDGPU_RESET_VCE (1 << 13)
215#define AMDGPU_RESET_VCE1 (1 << 14)
216
97b2e202
AD		 217/* max cursor sizes (in pixels) */
218#define CIK_CURSOR_WIDTH 128
219#define CIK_CURSOR_HEIGHT 128
220
221struct amdgpu_device;
97b2e202 222struct amdgpu_ib;
97b2e202 223struct amdgpu_cs_parser;
bb977d37 224struct amdgpu_job;
97b2e202 225struct amdgpu_irq_src;
0b492a4c 226struct amdgpu_fpriv;
9cca0b8e 227struct amdgpu_bo_va_mapping;
102c16a0 228struct amdgpu_atif;
992af942 229struct kfd_vm_fault_info;
97b2e202
AD		 230
231enum amdgpu_cp_irq {
53b2fe41
HZ		 232 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
233 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
97b2e202
AD		 234 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
235 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
236 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
237 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
238 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
239 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
240 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
241 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
242
243 AMDGPU_CP_IRQ_LAST
244};
245
97b2e202
AD		 246enum amdgpu_thermal_irq {
247 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
248 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
249
250 AMDGPU_THERMAL_IRQ_LAST
251};
252
4e638ae9
XY		 253enum amdgpu_kiq_irq {
254 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
255 AMDGPU_CP_KIQ_IRQ_LAST
256};
257
3890d111
ED		 258#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
259#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
4944af67 260#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
3890d111 261
43fa561f 262int amdgpu_device_ip_set_clockgating_state(void *dev,
2990a1fc
AD		 263 enum amd_ip_block_type block_type,
264 enum amd_clockgating_state state);
43fa561f 265int amdgpu_device_ip_set_powergating_state(void *dev,
2990a1fc
AD		 266 enum amd_ip_block_type block_type,
267 enum amd_powergating_state state);
268void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
269 u32 *flags);
270int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
271 enum amd_ip_block_type block_type);
272bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
273 enum amd_ip_block_type block_type);
97b2e202 274
a1255107
AD		 275#define AMDGPU_MAX_IP_NUM 16
276
277struct amdgpu_ip_block_status {
278 bool valid;
279 bool sw;
280 bool hw;
281 bool late_initialized;
282 bool hang;
283};
284
97b2e202 285struct amdgpu_ip_block_version {
a1255107
AD		 286 const enum amd_ip_block_type type;
287 const u32 major;
288 const u32 minor;
289 const u32 rev;
5fc3aeeb 290 const struct amd_ip_funcs *funcs;
97b2e202
AD		 291};
292
a1255107
AD		 293struct amdgpu_ip_block {
294 struct amdgpu_ip_block_status status;
295 const struct amdgpu_ip_block_version *version;
296};
297
2990a1fc
AD		 298int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
299 enum amd_ip_block_type type,
300 u32 major, u32 minor);
97b2e202 301
2990a1fc
AD		 302struct amdgpu_ip_block *
303amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
304 enum amd_ip_block_type type);
a1255107 305
2990a1fc
AD		 306int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
307 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202 308
97b2e202
AD		 309/*
310 * BIOS.
311 */
312bool amdgpu_get_bios(struct amdgpu_device *adev);
313bool amdgpu_read_bios(struct amdgpu_device *adev);
314
97b2e202
AD		 315/*
316 * Clocks
317 */
318
319#define AMDGPU_MAX_PPLL 3
320
321struct amdgpu_clock {
322 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
323 struct amdgpu_pll spll;
324 struct amdgpu_pll mpll;
325 /* 10 Khz units */
326 uint32_t default_mclk;
327 uint32_t default_sclk;
328 uint32_t default_dispclk;
329 uint32_t current_dispclk;
330 uint32_t dp_extclk;
331 uint32_t max_pixel_clock;
332};
333
97b2e202
AD		 334/* sub-allocation manager, it has to be protected by another lock.
335 * By conception this is an helper for other part of the driver
336 * like the indirect buffer or semaphore, which both have their
337 * locking.
338 *
339 * Principe is simple, we keep a list of sub allocation in offset
340 * order (first entry has offset == 0, last entry has the highest
341 * offset).
342 *
343 * When allocating new object we first check if there is room at
344 * the end total_size - (last_object_offset + last_object_size) >=
345 * alloc_size. If so we allocate new object there.
346 *
347 * When there is not enough room at the end, we start waiting for
348 * each sub object until we reach object_offset+object_size >=
349 * alloc_size, this object then become the sub object we return.
350 *
351 * Alignment can't be bigger than page size.
352 *
353 * Hole are not considered for allocation to keep things simple.
354 * Assumption is that there won't be hole (all object on same
355 * alignment).
356 */
6ba60b89
CK		 357
358#define AMDGPU_SA_NUM_FENCE_LISTS 32
359
97b2e202
AD		 360struct amdgpu_sa_manager {
361 wait_queue_head_t wq;
362 struct amdgpu_bo *bo;
363 struct list_head *hole;
6ba60b89 364 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 365 struct list_head olist;
366 unsigned size;
367 uint64_t gpu_addr;
368 void *cpu_ptr;
369 uint32_t domain;
370 uint32_t align;
371};
372
97b2e202
AD		 373/* sub-allocation buffer */
374struct amdgpu_sa_bo {
375 struct list_head olist;
376 struct list_head flist;
377 struct amdgpu_sa_manager *manager;
378 unsigned soffset;
379 unsigned eoffset;
f54d1867 380 struct dma_fence *fence;
97b2e202
AD		 381};
382
d573de2d
RZ		 383int amdgpu_fence_slab_init(void);
384void amdgpu_fence_slab_fini(void);
97b2e202 385
97b2e202
AD		 386/*
387 * IRQS.
388 */
389
390struct amdgpu_flip_work {
325cbba1 391 struct delayed_work flip_work;
97b2e202
AD		 392 struct work_struct unpin_work;
393 struct amdgpu_device *adev;
394 int crtc_id;
325cbba1 395 u32 target_vblank;
97b2e202
AD		 396 uint64_t base;
397 struct drm_pending_vblank_event *event;
765e7fbf 398 struct amdgpu_bo *old_abo;
f54d1867 399 struct dma_fence *excl;
1ffd2652 400 unsigned shared_count;
f54d1867
CW		 401 struct dma_fence **shared;
402 struct dma_fence_cb cb;
cb9e59d7 403 bool async;
97b2e202
AD		 404};
405
406
407/*
408 * CP & rings.
409 */
410
411struct amdgpu_ib {
412 struct amdgpu_sa_bo *sa_bo;
413 uint32_t length_dw;
414 uint64_t gpu_addr;
415 uint32_t *ptr;
de807f81 416 uint32_t flags;
97b2e202
AD		 417};
418
1b1f42d8 419extern const struct drm_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 420
97b2e202
AD		 421/*
422 * file private structure
423 */
424
425struct amdgpu_fpriv {
426 struct amdgpu_vm vm;
b85891bd 427 struct amdgpu_bo_va *prt_va;
0f4b3c68 428 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 429 struct mutex bo_list_lock;
430 struct idr bo_list_handles;
0b492a4c 431 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 432};
433
021830d2 434int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
912dfc84 435int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
021830d2 436
b07c60c0 437int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 438 unsigned size, struct amdgpu_ib *ib);
4d9c514d 439void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 440 struct dma_fence *f);
b07c60c0 441int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 442 struct amdgpu_ib *ibs, struct amdgpu_job *job,
443 struct dma_fence **f);
97b2e202
AD		 444int amdgpu_ib_pool_init(struct amdgpu_device *adev);
445void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
446int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 447
448/*
449 * CS.
450 */
451struct amdgpu_cs_chunk {
452 uint32_t chunk_id;
453 uint32_t length_dw;
758ac17f 454 void *kdata;
97b2e202
AD		 455};
456
2624dd15
CZ		 457struct amdgpu_cs_post_dep {
458 struct drm_syncobj *syncobj;
459 struct dma_fence_chain *chain;
460 u64 point;
461};
462
97b2e202
AD		 463struct amdgpu_cs_parser {
464 struct amdgpu_device *adev;
465 struct drm_file *filp;
3cb485f3 466 struct amdgpu_ctx *ctx;
c3cca41e 467
97b2e202
AD		 468 /* chunks */
469 unsigned nchunks;
470 struct amdgpu_cs_chunk *chunks;
97b2e202 471
50838c8c
CK		 472 /* scheduler job object */
473 struct amdgpu_job *job;
0d346a14 474 struct drm_sched_entity *entity;
97b2e202 475
c3cca41e
CK		 476 /* buffer objects */
477 struct ww_acquire_ctx ticket;
478 struct amdgpu_bo_list *bo_list;
3fe89771 479 struct amdgpu_mn *mn;
c3cca41e
CK		 480 struct amdgpu_bo_list_entry vm_pd;
481 struct list_head validated;
f54d1867 482 struct dma_fence *fence;
c3cca41e 483 uint64_t bytes_moved_threshold;
00f06b24 484 uint64_t bytes_moved_vis_threshold;
c3cca41e 485 uint64_t bytes_moved;
00f06b24 486 uint64_t bytes_moved_vis;
97b2e202
AD		 487
488 /* user fence */
91acbeb6 489 struct amdgpu_bo_list_entry uf_entry;
660e8558 490
2624dd15
CZ		 491 unsigned num_post_deps;
492 struct amdgpu_cs_post_dep *post_deps;
97b2e202
AD		 493};
494
7270f839
CK		 495static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
496 uint32_t ib_idx, int idx)
97b2e202 497{
50838c8c 498 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 499}
500
7270f839
CK		 501static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
502 uint32_t ib_idx, int idx,
503 uint32_t value)
504{
50838c8c 505 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 506}
507
97b2e202
AD		 508/*
509 * Writeback
510 */
73469585 511#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
97b2e202
AD		 512
513struct amdgpu_wb {
514 struct amdgpu_bo *wb_obj;
515 volatile uint32_t *wb;
516 uint64_t gpu_addr;
517 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
518 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
519};
520
131b4b36
AD		 521int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
522void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
97b2e202 523
97b2e202
AD		 524/*
525 * Benchmarking
526 */
527void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
528
529
530/*
531 * Testing
532 */
533void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 534
97b2e202
AD		 535/*
536 * ASIC specific register table accessible by UMD
537 */
538struct amdgpu_allowed_register_entry {
539 uint32_t reg_offset;
97b2e202
AD		 540 bool grbm_indexed;
541};
542
0cf3c64f
AD		 543enum amd_reset_method {
544 AMD_RESET_METHOD_LEGACY = 0,
545 AMD_RESET_METHOD_MODE0,
546 AMD_RESET_METHOD_MODE1,
547 AMD_RESET_METHOD_MODE2,
548 AMD_RESET_METHOD_BACO
549};
550
97b2e202
AD		 551/*
552 * ASIC specific functions.
553 */
554struct amdgpu_asic_funcs {
555 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 556 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
557 u8 *bios, u32 length_bytes);
97b2e202
AD		 558 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
559 u32 sh_num, u32 reg_offset, u32 *value);
560 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
561 int (*reset)(struct amdgpu_device *adev);
0cf3c64f 562 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
97b2e202
AD		 563 /* get the reference clock */
564 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 565 /* MM block clocks */
566 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
567 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 568 /* static power management */
569 int (*get_pcie_lanes)(struct amdgpu_device *adev);
570 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 571 /* get config memsize register */
572 u32 (*get_config_memsize)(struct amdgpu_device *adev);
2df1b8b6 573 /* flush hdp write queue */
69882565 574 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
2df1b8b6 575 /* invalidate hdp read cache */
69882565
CK		 576 void (*invalidate_hdp)(struct amdgpu_device *adev,
577 struct amdgpu_ring *ring);
69070690
AD		 578 /* check if the asic needs a full reset of if soft reset will work */
579 bool (*need_full_reset)(struct amdgpu_device *adev);
5253163a
OZ		 580 /* initialize doorbell layout for specific asic*/
581 void (*init_doorbell_index)(struct amdgpu_device *adev);
b45e18ac
KR		 582 /* PCIe bandwidth usage */
583 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
584 uint64_t *count1);
44401889
AD		 585 /* do we need to reset the asic at init time (e.g., kexec) */
586 bool (*need_reset_on_init)(struct amdgpu_device *adev);
dcea6e65
KR		 587 /* PCIe replay counter */
588 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
97b2e202
AD		 589};
590
591/*
592 * IOCTL.
593 */
97b2e202
AD		 594int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
595 struct drm_file *filp);
596
97b2e202 597int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 598int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
599 struct drm_file *filp);
97b2e202 600int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 601int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
602 struct drm_file *filp);
97b2e202 603
97b2e202
AD		 604/* VRAM scratch page for HDP bug, default vram page */
605struct amdgpu_vram_scratch {
606 struct amdgpu_bo *robj;
607 volatile uint32_t *ptr;
608 u64 gpu_addr;
609};
610
611/*
612 * ACPI
613 */
97b2e202
AD		 614struct amdgpu_atcs_functions {
615 bool get_ext_state;
616 bool pcie_perf_req;
617 bool pcie_dev_rdy;
618 bool pcie_bus_width;
619};
620
621struct amdgpu_atcs {
622 struct amdgpu_atcs_functions functions;
623};
624
a05502e5
HC		 625/*
626 * Firmware VRAM reservation
627 */
628struct amdgpu_fw_vram_usage {
629 u64 start_offset;
630 u64 size;
631 struct amdgpu_bo *reserved_bo;
632 void *va;
633};
634
d03846af
CZ		 635/*
636 * CGS
637 */
110e6f26
DA		 638struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
639void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 640
97b2e202
AD		 641/*
642 * Core structure, functions and helpers.
643 */
644typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
645typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
646
4fa1c6a6
TZ		 647typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
648typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
649
97b2e202
AD		 650typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
651typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
652
88807dc8
OZ		 653struct amdgpu_mmio_remap {
654 u32 reg_offset;
655 resource_size_t bus_addr;
656};
657
634c96e3 658struct amdgpu_df_funcs {
e4cf4bf5 659 void (*sw_init)(struct amdgpu_device *adev);
f1d59e00 660 void (*sw_fini)(struct amdgpu_device *adev);
634c96e3
HZ		 661 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
662 bool enable);
663 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
664 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
665 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
666 bool enable);
667 void (*get_clockgating_state)(struct amdgpu_device *adev,
668 u32 *flags);
8f9b2e50
AD		 669 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
670 bool enable);
992af942
JK		 671 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
672 int is_enable);
673 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
674 int is_disable);
675 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
676 uint64_t *count);
64671c0f
JK		 677 uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
678 void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
679 uint32_t ficadl_val, uint32_t ficadh_val);
634c96e3 680};
4522824c
SL		 681/* Define the HW IP blocks will be used in driver , add more if necessary */
682enum amd_hw_ip_block_type {
683 GC_HWIP = 1,
684 HDP_HWIP,
685 SDMA0_HWIP,
686 SDMA1_HWIP,
fa5d2e6f
LM		 687 SDMA2_HWIP,
688 SDMA3_HWIP,
689 SDMA4_HWIP,
690 SDMA5_HWIP,
691 SDMA6_HWIP,
692 SDMA7_HWIP,
4522824c
SL		 693 MMHUB_HWIP,
694 ATHUB_HWIP,
695 NBIO_HWIP,
696 MP0_HWIP,
e6636ae1 697 MP1_HWIP,
4522824c
SL		 698 UVD_HWIP,
699 VCN_HWIP = UVD_HWIP,
700 VCE_HWIP,
701 DF_HWIP,
702 DCE_HWIP,
703 OSSSYS_HWIP,
704 SMUIO_HWIP,
705 PWR_HWIP,
706 NBIF_HWIP,
e6636ae1 707 THM_HWIP,
73b19174 708 CLK_HWIP,
6501a771
HZ		 709 UMC_HWIP,
710 RSMU_HWIP,
4522824c
SL		 711 MAX_HWIP
712};
713
113b47e7 714#define HWIP_MAX_INSTANCE 8
4522824c 715
11dc9364 716struct amd_powerplay {
11dc9364 717 void *pp_handle;
11dc9364
RZ		 718 const struct amd_pm_funcs *pp_funcs;
719};
720
0c49e0b8 721#define AMDGPU_RESET_MAGIC_NUM 64
e4cf4bf5 722#define AMDGPU_MAX_DF_PERFMONS 4
97b2e202
AD		 723struct amdgpu_device {
724 struct device *dev;
725 struct drm_device *ddev;
726 struct pci_dev *pdev;
97b2e202 727
a8fe58ce
MB		 728#ifdef CONFIG_DRM_AMD_ACP
729 struct amdgpu_acp acp;
730#endif
731
97b2e202 732 /* ASIC */
2f7d10b3 733 enum amd_asic_type asic_type;
97b2e202
AD		 734 uint32_t family;
735 uint32_t rev_id;
736 uint32_t external_rev_id;
737 unsigned long flags;
738 int usec_timeout;
739 const struct amdgpu_asic_funcs *asic_funcs;
740 bool shutdown;
fd5fd480 741 bool need_swiotlb;
97b2e202 742 bool accel_working;
97b2e202
AD		 743 struct notifier_block acpi_nb;
744 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
745 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 746 unsigned debugfs_count;
97b2e202 747#if defined(CONFIG_DEBUG_FS)
6698a3d0 748 struct dentry *debugfs_preempt;
adcec288 749 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202 750#endif
102c16a0 751 struct amdgpu_atif *atif;
97b2e202
AD		 752 struct amdgpu_atcs atcs;
753 struct mutex srbm_mutex;
754 /* GRBM index mutex. Protects concurrent access to GRBM index */
755 struct mutex grbm_idx_mutex;
756 struct dev_pm_domain vga_pm_domain;
757 bool have_disp_power_ref;
bae17d2a 758 bool have_atomics_support;
97b2e202
AD		 759
760 /* BIOS */
0cdd5005 761 bool is_atom_fw;
97b2e202 762 uint8_t *bios;
a9f5db9c 763 uint32_t bios_size;
5af2c10d 764 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 765 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 766 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
767
768 /* Register/doorbell mmio */
769 resource_size_t rmmio_base;
770 resource_size_t rmmio_size;
771 void __iomem *rmmio;
772 /* protects concurrent MM_INDEX/DATA based register access */
773 spinlock_t mmio_idx_lock;
88807dc8 774 struct amdgpu_mmio_remap rmmio_remap;
97b2e202
AD		 775 /* protects concurrent SMC based register access */
776 spinlock_t smc_idx_lock;
777 amdgpu_rreg_t smc_rreg;
778 amdgpu_wreg_t smc_wreg;
779 /* protects concurrent PCIE register access */
780 spinlock_t pcie_idx_lock;
781 amdgpu_rreg_t pcie_rreg;
782 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 783 amdgpu_rreg_t pciep_rreg;
784 amdgpu_wreg_t pciep_wreg;
4fa1c6a6
TZ		 785 amdgpu_rreg64_t pcie_rreg64;
786 amdgpu_wreg64_t pcie_wreg64;
97b2e202
AD		 787 /* protects concurrent UVD register access */
788 spinlock_t uvd_ctx_idx_lock;
789 amdgpu_rreg_t uvd_ctx_rreg;
790 amdgpu_wreg_t uvd_ctx_wreg;
791 /* protects concurrent DIDT register access */
792 spinlock_t didt_idx_lock;
793 amdgpu_rreg_t didt_rreg;
794 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 795 /* protects concurrent gc_cac register access */
796 spinlock_t gc_cac_idx_lock;
797 amdgpu_rreg_t gc_cac_rreg;
798 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 799 /* protects concurrent se_cac register access */
800 spinlock_t se_cac_idx_lock;
801 amdgpu_rreg_t se_cac_rreg;
802 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 803 /* protects concurrent ENDPOINT (audio) register access */
804 spinlock_t audio_endpt_idx_lock;
805 amdgpu_block_rreg_t audio_endpt_rreg;
806 amdgpu_block_wreg_t audio_endpt_wreg;
807 void __iomem *rio_mem;
808 resource_size_t rio_mem_size;
809 struct amdgpu_doorbell doorbell;
810
811 /* clock/pll info */
812 struct amdgpu_clock clock;
813
814 /* MC */
770d13b1 815 struct amdgpu_gmc gmc;
97b2e202 816 struct amdgpu_gart gart;
92e71b06 817 dma_addr_t dummy_page_addr;
97b2e202 818 struct amdgpu_vm_manager vm_manager;
e60f8db5 819 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
1daa2bfa 820 unsigned num_vmhubs;
97b2e202
AD		 821
822 /* memory management */
823 struct amdgpu_mman mman;
97b2e202
AD		 824 struct amdgpu_vram_scratch vram_scratch;
825 struct amdgpu_wb wb;
97b2e202 826 atomic64_t num_bytes_moved;
dbd5ed60 827 atomic64_t num_evictions;
68e2c5ff 828 atomic64_t num_vram_cpu_page_faults;
d94aed5a 829 atomic_t gpu_reset_counter;
f1892138 830 atomic_t vram_lost_counter;
97b2e202 831
95844d20
MO		 832 /* data for buffer migration throttling */
833 struct {
834 spinlock_t lock;
835 s64 last_update_us;
836 s64 accum_us; /* accumulated microseconds */
00f06b24 837 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 838 u32 log2_max_MBps;
839 } mm_stats;
840
97b2e202 841 /* display */
9accf2fd 842 bool enable_virtual_display;
97b2e202 843 struct amdgpu_mode_info mode_info;
4562236b 844 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 845 struct work_struct hotplug_work;
846 struct amdgpu_irq_src crtc_irq;
d2574c33 847 struct amdgpu_irq_src vupdate_irq;
97b2e202
AD		 848 struct amdgpu_irq_src pageflip_irq;
849 struct amdgpu_irq_src hpd_irq;
850
851 /* rings */
76bf0db5 852 u64 fence_context;
97b2e202
AD		 853 unsigned num_rings;
854 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
855 bool ib_pool_ready;
856 struct amdgpu_sa_manager ring_tmp_bo;
857
858 /* interrupts */
859 struct amdgpu_irq irq;
860
1f7371b2
AD		 861 /* powerplay */
862 struct amd_powerplay powerplay;
f3898ea1 863 bool pp_force_state_enabled;
1f7371b2 864
137d63ab
HR		 865 /* smu */
866 struct smu_context smu;
867
97b2e202
AD		 868 /* dpm */
869 struct amdgpu_pm pm;
870 u32 cg_flags;
871 u32 pg_flags;
872
bebc0762
HZ		 873 /* nbio */
874 struct amdgpu_nbio nbio;
875
97b2e202
AD		 876 /* gfx */
877 struct amdgpu_gfx gfx;
878
879 /* sdma */
c113ea1c 880 struct amdgpu_sdma sdma;
97b2e202 881
b43aaee6
LL		 882 /* uvd */
883 struct amdgpu_uvd uvd;
884
885 /* vce */
886 struct amdgpu_vce vce;
887
888 /* vcn */
889 struct amdgpu_vcn vcn;
97b2e202
AD		 890
891 /* firmwares */
892 struct amdgpu_firmware firmware;
893
0e5ca0d1
HR		 894 /* PSP */
895 struct psp_context psp;
896
97b2e202
AD		 897 /* GDS */
898 struct amdgpu_gds gds;
899
611736d8
FK		 900 /* KFD */
901 struct amdgpu_kfd_dev kfd;
902
045c0216
TZ		 903 /* UMC */
904 struct amdgpu_umc umc;
905
4562236b
HW		 906 /* display related functionality */
907 struct amdgpu_display_manager dm;
908
f39f5bb1
XY		 909 /* discovery */
910 uint8_t *discovery;
911
a538bbe7
JX		 912 /* mes */
913 bool enable_mes;
914 struct amdgpu_mes mes;
915
a1255107 916 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 917 int num_ip_blocks;
97b2e202
AD		 918 struct mutex mn_lock;
919 DECLARE_HASHTABLE(mn_hash, 7);
920
921 /* tracking pinned memory */
a5ccfe5c
MD		 922 atomic64_t vram_pin_size;
923 atomic64_t visible_pin_size;
924 atomic64_t gart_pin_size;
130e0371 925
4522824c
SL		 926 /* soc15 register offset based on ip, instance and segment */
927 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
928
634c96e3 929 const struct amdgpu_df_funcs *df_funcs;
3d093da0 930 const struct amdgpu_mmhub_funcs *mmhub_funcs;
946a4d5b 931
2dc80b00 932 /* delayed work_func for deferring clockgating during resume */
beff74bc 933 struct delayed_work delayed_init_work;
2dc80b00 934
5a5099cb 935 struct amdgpu_virt virt;
a05502e5
HC		 936 /* firmware VRAM reservation */
937 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 938
939 /* link all shadow bo */
940 struct list_head shadow_list;
941 struct mutex shadow_list_lock;
795f2813
AR		 942 /* keep an lru list of rings by HW IP */
943 struct list_head ring_lru_list;
944 spinlock_t ring_lru_list_lock;
5c1354bd 945
c836fec5
JQ		 946 /* record hw reset is performed */
947 bool has_hw_reset;
0c49e0b8 948 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 949
44779b43
RZ		 950 /* s3/s4 mask */
951 bool in_suspend;
952
47ed4e1c
KW		 953 /* record last mm index being written through WREG32*/
954 unsigned long last_mm_index;
13a752e3 955 bool in_gpu_reset;
a3a09142 956 enum pp_mp1_state mp1_state;
13a752e3 957 struct mutex lock_reset;
409c5191 958 struct amdgpu_doorbell_index doorbell_index;
d4535e2c 959
26bc5340 960 int asic_reset_res;
d4535e2c 961 struct work_struct xgmi_reset_work;
9b638f97 962
0c5ccf14 963 bool in_baco_reset;
912dfc84
EQ		 964
965 long gfx_timeout;
966 long sdma_timeout;
967 long video_timeout;
968 long compute_timeout;
fb2dbfd2
KR		 969
970 uint64_t unique_id;
e4cf4bf5 971 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
97b2e202
AD		 972};
973
a7d64de6
CK		 974static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
975{
976 return container_of(bdev, struct amdgpu_device, mman.bdev);
977}
978
97b2e202
AD		 979int amdgpu_device_init(struct amdgpu_device *adev,
980 struct drm_device *ddev,
981 struct pci_dev *pdev,
982 uint32_t flags);
983void amdgpu_device_fini(struct amdgpu_device *adev);
984int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
985
986uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 987 uint32_t acc_flags);
97b2e202 988void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 989 uint32_t acc_flags);
421a2a30
ML		 990void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
991uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
992
97b2e202
AD		 993u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
994void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
995
4562236b
HW		 996bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
997bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
998
9475a943
SL		 999int emu_soc_asic_init(struct amdgpu_device *adev);
1000
97b2e202
AD		 1001/*
1002 * Registers read & write functions.
1003 */
15d72fd7
ML		 1004
1005#define AMDGPU_REGS_IDX (1<<0)
1006#define AMDGPU_REGS_NO_KIQ (1<<1)
1007
1008#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1009#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1010
421a2a30
ML		 1011#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1012#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1013
15d72fd7
ML		 1014#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1015#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1016#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1017#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1018#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1019#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1020#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1021#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1022#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1023#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1024#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
4fa1c6a6
TZ		 1025#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1026#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
97b2e202
AD		 1027#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1028#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1029#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1030#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1031#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1032#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1033#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1034#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1035#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1036#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1037#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1038#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1039#define WREG32_P(reg, val, mask) \
1040 do { \
1041 uint32_t tmp_ = RREG32(reg); \
1042 tmp_ &= (mask); \
1043 tmp_ |= ((val) & ~(mask)); \
1044 WREG32(reg, tmp_); \
1045 } while (0)
1046#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1047#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1048#define WREG32_PLL_P(reg, val, mask) \
1049 do { \
1050 uint32_t tmp_ = RREG32_PLL(reg); \
1051 tmp_ &= (mask); \
1052 tmp_ |= ((val) & ~(mask)); \
1053 WREG32_PLL(reg, tmp_); \
1054 } while (0)
1055#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1056#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1057#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1058
97b2e202
AD		 1059#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1060#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1061
1062#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1063 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1064 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1065
1066#define REG_GET_FIELD(value, reg, field) \
1067 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1068
1069#define WREG32_FIELD(reg, field, val) \
1070 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1071
ccaf3574
TSD		 1072#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1073 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1074
97b2e202
AD		 1075/*
1076 * BIOS helpers.
1077 */
1078#define RBIOS8(i) (adev->bios[i])
1079#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1080#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1081
97b2e202
AD		 1082/*
1083 * ASICs macro.
1084 */
1085#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1086#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
0cf3c64f 1087#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
97b2e202
AD		 1088#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1089#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1090#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1091#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1092#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1093#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1094#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1095#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1096#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1097#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
69882565
CK		 1098#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1099#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
69070690 1100#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
5253163a 1101#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
b45e18ac 1102#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
44401889 1103#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
dcea6e65 1104#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
e3526257 1105#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
97b2e202
AD		 1106
1107/* Common functions */
12938fad 1108bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
5f152b5e 1109int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
12938fad 1110 struct amdgpu_job* job);
8111c387 1111void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
39c640c0 1112bool amdgpu_device_need_post(struct amdgpu_device *adev);
d5fc5e82 1113
00f06b24
JB		 1114void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1115 u64 num_vis_bytes);
d6895ad3 1116int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
9c3f2b54 1117void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
97b2e202
AD		 1118 const u32 *registers,
1119 const u32 array_size);
1120
1121bool amdgpu_device_is_px(struct drm_device *dev);
992af942
JK		 1122bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1123 struct amdgpu_device *peer_adev);
1124
97b2e202
AD		 1125/* atpx handler */
1126#if defined(CONFIG_VGA_SWITCHEROO)
1127void amdgpu_register_atpx_handler(void);
1128void amdgpu_unregister_atpx_handler(void);
a78fe133 1129bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1130bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1131bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1132bool amdgpu_has_atpx(void);
97b2e202
AD		 1133#else
1134static inline void amdgpu_register_atpx_handler(void) {}
1135static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1136static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1137static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1138static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1139static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1140#endif
1141
24aeefcd
LP		 1142#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1143void *amdgpu_atpx_get_dhandle(void);
1144#else
1145static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1146#endif
1147
97b2e202
AD		 1148/*
1149 * KMS
1150 */
1151extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1152extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1153
1154int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1155void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1156void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1157int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1158void amdgpu_driver_postclose_kms(struct drm_device *dev,
1159 struct drm_file *file_priv);
cdd61df6 1160int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1161int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1162int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1163u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1164int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1165void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1166long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1167 unsigned long arg);
1168
97b2e202
AD		 1169/*
1170 * functions used by amdgpu_encoder.c
1171 */
1172struct amdgpu_afmt_acr {
1173 u32 clock;
1174
1175 int n_32khz;
1176 int cts_32khz;
1177
1178 int n_44_1khz;
1179 int cts_44_1khz;
1180
1181 int n_48khz;
1182 int cts_48khz;
1183
1184};
1185
1186struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1187
1188/* amdgpu_acpi.c */
1189#if defined(CONFIG_ACPI)
1190int amdgpu_acpi_init(struct amdgpu_device *adev);
1191void amdgpu_acpi_fini(struct amdgpu_device *adev);
1192bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1193int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1194 u8 perf_req, bool advertise);
1195int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
206bbafe
DF		 1196
1197void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1198 struct amdgpu_dm_backlight_caps *caps);
97b2e202
AD		 1199#else
1200static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1201static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1202#endif
1203
9cca0b8e
CK		 1204int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1205 uint64_t addr, struct amdgpu_bo **bo,
1206 struct amdgpu_bo_va_mapping **mapping);
97b2e202 1207
4562236b
HW		 1208#if defined(CONFIG_DRM_AMD_DC)
1209int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1210#else
1211static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1212#endif
1213
fdafb359
EQ		 1214
1215void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1216void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1217
97b2e202 1218#include "amdgpu_object.h"
e4cf4bf5
JK		 1219
1220/* used by df_v3_6.c and amdgpu_pmu.c */
1221#define AMDGPU_PMU_ATTR(_name, _object) \
1222static ssize_t \
1223_name##_show(struct device *dev, \
1224 struct device_attribute *attr, \
1225 char *page) \
1226{ \
1227 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1228 return sprintf(page, _object "\n"); \
1229} \
1230 \
1231static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1232
97b2e202 1233#endif
e4cf4bf5 1234
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