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Merge tag 'mmc-v4.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202 38
248a1d6f
MY		 39#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
78c16834
AR		 49#include <kgd_kfd_interface.h>
50
5fc3aeeb 51#include "amd_shared.h"
97b2e202
AD		 52#include "amdgpu_mode.h"
53#include "amdgpu_ih.h"
54#include "amdgpu_irq.h"
55#include "amdgpu_ucode.h"
c632d799 56#include "amdgpu_ttm.h"
0e5ca0d1 57#include "amdgpu_psp.h"
97b2e202 58#include "amdgpu_gds.h"
56113504 59#include "amdgpu_sync.h"
78023016 60#include "amdgpu_ring.h"
073440d2 61#include "amdgpu_vm.h"
1f7371b2 62#include "amd_powerplay.h"
cf097881 63#include "amdgpu_dpm.h"
a8fe58ce 64#include "amdgpu_acp.h"
4df654d2 65#include "amdgpu_uvd.h"
5e568178 66#include "amdgpu_vce.h"
95aa13f6 67#include "amdgpu_vcn.h"
9a189996 68#include "amdgpu_mn.h"
4562236b 69#include "amdgpu_dm.h"
97b2e202 70
b80d8475 71#include "gpu_scheduler.h"
ceeb50ed 72#include "amdgpu_virt.h"
3490bdb5 73#include "amdgpu_gart.h"
b80d8475 74
97b2e202
AD		 75/*
76 * Modules parameters.
77 */
78extern int amdgpu_modeset;
79extern int amdgpu_vram_limit;
218b5dcd 80extern int amdgpu_vis_vram_limit;
83e74db6 81extern int amdgpu_gart_size;
36d38372 82extern int amdgpu_gtt_size;
95844d20 83extern int amdgpu_moverate;
97b2e202
AD		 84extern int amdgpu_benchmarking;
85extern int amdgpu_testing;
86extern int amdgpu_audio;
87extern int amdgpu_disp_priority;
88extern int amdgpu_hw_i2c;
89extern int amdgpu_pcie_gen2;
90extern int amdgpu_msi;
91extern int amdgpu_lockup_timeout;
92extern int amdgpu_dpm;
e635ee07 93extern int amdgpu_fw_load_type;
97b2e202
AD		 94extern int amdgpu_aspm;
95extern int amdgpu_runtime_pm;
0b693f0b 96extern uint amdgpu_ip_block_mask;
97b2e202
AD		 97extern int amdgpu_bapm;
98extern int amdgpu_deep_color;
99extern int amdgpu_vm_size;
100extern int amdgpu_vm_block_size;
d07f14be 101extern int amdgpu_vm_fragment_size;
d9c13156 102extern int amdgpu_vm_fault_stop;
b495bd3a 103extern int amdgpu_vm_debug;
9a4b7d4c 104extern int amdgpu_vm_update_mode;
4562236b 105extern int amdgpu_dc;
02e749dc 106extern int amdgpu_dc_log;
1333f723 107extern int amdgpu_sched_jobs;
4afcb303 108extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 109extern int amdgpu_no_evict;
110extern int amdgpu_direct_gma_size;
0b693f0b
RZ		 111extern uint amdgpu_pcie_gen_cap;
112extern uint amdgpu_pcie_lane_cap;
113extern uint amdgpu_cg_mask;
114extern uint amdgpu_pg_mask;
115extern uint amdgpu_sdma_phase_quantum;
6f8941a2 116extern char *amdgpu_disable_cu;
9accf2fd 117extern char *amdgpu_virtual_display;
0b693f0b 118extern uint amdgpu_pp_feature_mask;
6a7f76e7 119extern int amdgpu_vram_page_split;
bce23e00
AD		 120extern int amdgpu_ngg;
121extern int amdgpu_prim_buf_per_se;
122extern int amdgpu_pos_buf_per_se;
123extern int amdgpu_cntl_sb_buf_per_se;
124extern int amdgpu_param_buf_per_se;
65781c78 125extern int amdgpu_job_hang_limit;
e8835e0e 126extern int amdgpu_lbpw;
4a75aefe 127extern int amdgpu_compute_multipipe;
97b2e202 128
6dd13096
FK		 129#ifdef CONFIG_DRM_AMDGPU_SI
130extern int amdgpu_si_support;
131#endif
7df28986
FK		 132#ifdef CONFIG_DRM_AMDGPU_CIK
133extern int amdgpu_cik_support;
134#endif
97b2e202 135
55ed8caf 136#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 137#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 138#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
139#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
140/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
141#define AMDGPU_IB_POOL_SIZE 16
142#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
143#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 144#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 145
36f523a7
JZ		 146/* max number of IP instances */
147#define AMDGPU_MAX_SDMA_INSTANCES 2
148
97b2e202
AD		 149/* hard reset data */
150#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
151
152/* reset flags */
153#define AMDGPU_RESET_GFX (1 << 0)
154#define AMDGPU_RESET_COMPUTE (1 << 1)
155#define AMDGPU_RESET_DMA (1 << 2)
156#define AMDGPU_RESET_CP (1 << 3)
157#define AMDGPU_RESET_GRBM (1 << 4)
158#define AMDGPU_RESET_DMA1 (1 << 5)
159#define AMDGPU_RESET_RLC (1 << 6)
160#define AMDGPU_RESET_SEM (1 << 7)
161#define AMDGPU_RESET_IH (1 << 8)
162#define AMDGPU_RESET_VMC (1 << 9)
163#define AMDGPU_RESET_MC (1 << 10)
164#define AMDGPU_RESET_DISPLAY (1 << 11)
165#define AMDGPU_RESET_UVD (1 << 12)
166#define AMDGPU_RESET_VCE (1 << 13)
167#define AMDGPU_RESET_VCE1 (1 << 14)
168
97b2e202
AD		 169/* GFX current status */
170#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
171#define AMDGPU_GFX_SAFE_MODE 0x00000001L
172#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
173#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
174#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
175
176/* max cursor sizes (in pixels) */
177#define CIK_CURSOR_WIDTH 128
178#define CIK_CURSOR_HEIGHT 128
179
180struct amdgpu_device;
97b2e202 181struct amdgpu_ib;
97b2e202 182struct amdgpu_cs_parser;
bb977d37 183struct amdgpu_job;
97b2e202 184struct amdgpu_irq_src;
0b492a4c 185struct amdgpu_fpriv;
9cca0b8e 186struct amdgpu_bo_va_mapping;
97b2e202
AD		 187
188enum amdgpu_cp_irq {
189 AMDGPU_CP_IRQ_GFX_EOP = 0,
190 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
193 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
194 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
198
199 AMDGPU_CP_IRQ_LAST
200};
201
202enum amdgpu_sdma_irq {
203 AMDGPU_SDMA_IRQ_TRAP0 = 0,
204 AMDGPU_SDMA_IRQ_TRAP1,
205
206 AMDGPU_SDMA_IRQ_LAST
207};
208
209enum amdgpu_thermal_irq {
210 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
211 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
212
213 AMDGPU_THERMAL_IRQ_LAST
214};
215
4e638ae9
XY		 216enum amdgpu_kiq_irq {
217 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
218 AMDGPU_CP_KIQ_IRQ_LAST
219};
220
97b2e202 221int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 222 enum amd_ip_block_type block_type,
223 enum amd_clockgating_state state);
97b2e202 224int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 225 enum amd_ip_block_type block_type,
226 enum amd_powergating_state state);
6cb2d4e4 227void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
5dbbb60b
AD		 228int amdgpu_wait_for_idle(struct amdgpu_device *adev,
229 enum amd_ip_block_type block_type);
230bool amdgpu_is_idle(struct amdgpu_device *adev,
231 enum amd_ip_block_type block_type);
97b2e202 232
a1255107
AD		 233#define AMDGPU_MAX_IP_NUM 16
234
235struct amdgpu_ip_block_status {
236 bool valid;
237 bool sw;
238 bool hw;
239 bool late_initialized;
240 bool hang;
241};
242
97b2e202 243struct amdgpu_ip_block_version {
a1255107
AD		 244 const enum amd_ip_block_type type;
245 const u32 major;
246 const u32 minor;
247 const u32 rev;
5fc3aeeb 248 const struct amd_ip_funcs *funcs;
97b2e202
AD		 249};
250
a1255107
AD		 251struct amdgpu_ip_block {
252 struct amdgpu_ip_block_status status;
253 const struct amdgpu_ip_block_version *version;
254};
255
97b2e202 256int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 257 enum amd_ip_block_type type,
97b2e202
AD		 258 u32 major, u32 minor);
259
a1255107
AD		 260struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
261 enum amd_ip_block_type type);
262
263int amdgpu_ip_block_add(struct amdgpu_device *adev,
264 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 265
266/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
267struct amdgpu_buffer_funcs {
268 /* maximum bytes in a single operation */
269 uint32_t copy_max_bytes;
270
271 /* number of dw to reserve per operation */
272 unsigned copy_num_dw;
273
274 /* used for buffer migration */
c7ae72c0 275 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 276 /* src addr in bytes */
277 uint64_t src_offset,
278 /* dst addr in bytes */
279 uint64_t dst_offset,
280 /* number of byte to transfer */
281 uint32_t byte_count);
282
283 /* maximum bytes in a single operation */
284 uint32_t fill_max_bytes;
285
286 /* number of dw to reserve per operation */
287 unsigned fill_num_dw;
288
289 /* used for buffer clearing */
6e7a3840 290 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 291 /* value to write to memory */
292 uint32_t src_data,
293 /* dst addr in bytes */
294 uint64_t dst_offset,
295 /* number of byte to fill */
296 uint32_t byte_count);
297};
298
299/* provided by hw blocks that can write ptes, e.g., sdma */
300struct amdgpu_vm_pte_funcs {
e6d92197
YZ		 301 /* number of dw to reserve per operation */
302 unsigned copy_pte_num_dw;
303
97b2e202
AD		 304 /* copy pte entries from GART */
305 void (*copy_pte)(struct amdgpu_ib *ib,
306 uint64_t pe, uint64_t src,
307 unsigned count);
e6d92197 308
97b2e202 309 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 310 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
311 uint64_t value, unsigned count,
312 uint32_t incr);
7bdc53f9
YZ		 313
314 /* maximum nums of PTEs/PDEs in a single operation */
315 uint32_t set_max_nums_pte_pde;
316
317 /* number of dw to reserve per operation */
318 unsigned set_pte_pde_num_dw;
319
97b2e202
AD		 320 /* for linear pte/pde updates without addr mapping */
321 void (*set_pte_pde)(struct amdgpu_ib *ib,
322 uint64_t pe,
323 uint64_t addr, unsigned count,
6b777607 324 uint32_t incr, uint64_t flags);
97b2e202
AD		 325};
326
327/* provided by the gmc block */
328struct amdgpu_gart_funcs {
329 /* flush the vm tlb via mmio */
330 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
331 uint32_t vmid);
332 /* write pte/pde updates using the cpu */
333 int (*set_pte_pde)(struct amdgpu_device *adev,
334 void *cpu_pt_addr, /* cpu addr of page table */
335 uint32_t gpu_page_idx, /* pte/pde to update */
336 uint64_t addr, /* addr to write into pte/pde */
6b777607 337 uint64_t flags); /* access flags */
284710fa
CK		 338 /* enable/disable PRT support */
339 void (*set_prt)(struct amdgpu_device *adev, bool enable);
5463545b
AX		 340 /* set pte flags based per asic */
341 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
342 uint32_t flags);
b1166325
CK		 343 /* get the pde for a given mc addr */
344 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
03f89feb 345 uint32_t (*get_invalidate_req)(unsigned int vm_id);
e60f8db5
AX		 346};
347
97b2e202
AD		 348/* provided by the ih block */
349struct amdgpu_ih_funcs {
350 /* ring read/write ptr handling, called from interrupt context */
351 u32 (*get_wptr)(struct amdgpu_device *adev);
00ecd8a2 352 bool (*prescreen_iv)(struct amdgpu_device *adev);
97b2e202
AD		 353 void (*decode_iv)(struct amdgpu_device *adev,
354 struct amdgpu_iv_entry *entry);
355 void (*set_rptr)(struct amdgpu_device *adev);
356};
357
97b2e202
AD		 358/*
359 * BIOS.
360 */
361bool amdgpu_get_bios(struct amdgpu_device *adev);
362bool amdgpu_read_bios(struct amdgpu_device *adev);
363
364/*
365 * Dummy page
366 */
367struct amdgpu_dummy_page {
368 struct page *page;
369 dma_addr_t addr;
370};
371int amdgpu_dummy_page_init(struct amdgpu_device *adev);
372void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
373
374
375/*
376 * Clocks
377 */
378
379#define AMDGPU_MAX_PPLL 3
380
381struct amdgpu_clock {
382 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
383 struct amdgpu_pll spll;
384 struct amdgpu_pll mpll;
385 /* 10 Khz units */
386 uint32_t default_mclk;
387 uint32_t default_sclk;
388 uint32_t default_dispclk;
389 uint32_t current_dispclk;
390 uint32_t dp_extclk;
391 uint32_t max_pixel_clock;
392};
393
97b2e202 394/*
9124a398 395 * GEM.
97b2e202 396 */
97b2e202 397
7e5a547f 398#define AMDGPU_GEM_DOMAIN_MAX 0x3
97b2e202
AD		 399#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
400
401void amdgpu_gem_object_free(struct drm_gem_object *obj);
402int amdgpu_gem_object_open(struct drm_gem_object *obj,
403 struct drm_file *file_priv);
404void amdgpu_gem_object_close(struct drm_gem_object *obj,
405 struct drm_file *file_priv);
406unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
407struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 408struct drm_gem_object *
409amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
410 struct dma_buf_attachment *attach,
411 struct sg_table *sg);
97b2e202
AD		 412struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
413 struct drm_gem_object *gobj,
414 int flags);
415int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
416void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
417struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
418void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
419void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
dfced2e4 420int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
97b2e202
AD		 421int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
422
423/* sub-allocation manager, it has to be protected by another lock.
424 * By conception this is an helper for other part of the driver
425 * like the indirect buffer or semaphore, which both have their
426 * locking.
427 *
428 * Principe is simple, we keep a list of sub allocation in offset
429 * order (first entry has offset == 0, last entry has the highest
430 * offset).
431 *
432 * When allocating new object we first check if there is room at
433 * the end total_size - (last_object_offset + last_object_size) >=
434 * alloc_size. If so we allocate new object there.
435 *
436 * When there is not enough room at the end, we start waiting for
437 * each sub object until we reach object_offset+object_size >=
438 * alloc_size, this object then become the sub object we return.
439 *
440 * Alignment can't be bigger than page size.
441 *
442 * Hole are not considered for allocation to keep things simple.
443 * Assumption is that there won't be hole (all object on same
444 * alignment).
445 */
6ba60b89
CK		 446
447#define AMDGPU_SA_NUM_FENCE_LISTS 32
448
97b2e202
AD		 449struct amdgpu_sa_manager {
450 wait_queue_head_t wq;
451 struct amdgpu_bo *bo;
452 struct list_head *hole;
6ba60b89 453 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 454 struct list_head olist;
455 unsigned size;
456 uint64_t gpu_addr;
457 void *cpu_ptr;
458 uint32_t domain;
459 uint32_t align;
460};
461
97b2e202
AD		 462/* sub-allocation buffer */
463struct amdgpu_sa_bo {
464 struct list_head olist;
465 struct list_head flist;
466 struct amdgpu_sa_manager *manager;
467 unsigned soffset;
468 unsigned eoffset;
f54d1867 469 struct dma_fence *fence;
97b2e202
AD		 470};
471
472/*
473 * GEM objects.
474 */
418aa0c2 475void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202 476int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
e1eb899b
CK		 477 int alignment, u32 initial_domain,
478 u64 flags, bool kernel,
479 struct reservation_object *resv,
480 struct drm_gem_object **obj);
97b2e202
AD		 481
482int amdgpu_mode_dumb_create(struct drm_file *file_priv,
483 struct drm_device *dev,
484 struct drm_mode_create_dumb *args);
485int amdgpu_mode_dumb_mmap(struct drm_file *filp,
486 struct drm_device *dev,
487 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 488int amdgpu_fence_slab_init(void);
489void amdgpu_fence_slab_fini(void);
97b2e202 490
e60f8db5
AX		 491/*
492 * VMHUB structures, functions & helpers
493 */
494struct amdgpu_vmhub {
495 uint32_t ctx0_ptb_addr_lo32;
496 uint32_t ctx0_ptb_addr_hi32;
497 uint32_t vm_inv_eng0_req;
498 uint32_t vm_inv_eng0_ack;
499 uint32_t vm_context0_cntl;
500 uint32_t vm_l2_pro_fault_status;
501 uint32_t vm_l2_pro_fault_cntl;
e60f8db5
AX		 502};
503
97b2e202
AD		 504/*
505 * GPU MC structures, functions & helpers
506 */
507struct amdgpu_mc {
508 resource_size_t aper_size;
509 resource_size_t aper_base;
510 resource_size_t agp_base;
511 /* for some chips with <= 32MB we need to lie
512 * about vram size near mc fb location */
513 u64 mc_vram_size;
514 u64 visible_vram_size;
6f02a696
CK		 515 u64 gart_size;
516 u64 gart_start;
517 u64 gart_end;
97b2e202
AD		 518 u64 vram_start;
519 u64 vram_end;
520 unsigned vram_width;
521 u64 real_vram_size;
522 int vram_mtrr;
97b2e202
AD		 523 u64 mc_mask;
524 const struct firmware *fw; /* MC firmware */
525 uint32_t fw_version;
526 struct amdgpu_irq_src vm_fault;
81c59f54 527 uint32_t vram_type;
50b0197a 528 uint32_t srbm_soft_reset;
f7c35abe 529 bool prt_warning;
916910ad 530 uint64_t stolen_size;
8fe73328
JZ		 531 /* apertures */
532 u64 shared_aperture_start;
533 u64 shared_aperture_end;
534 u64 private_aperture_start;
535 u64 private_aperture_end;
e60f8db5
AX		 536 /* protects concurrent invalidation */
537 spinlock_t invalidate_lock;
97b2e202
AD		 538};
539
540/*
541 * GPU doorbell structures, functions & helpers
542 */
543typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
544{
545 AMDGPU_DOORBELL_KIQ = 0x000,
546 AMDGPU_DOORBELL_HIQ = 0x001,
547 AMDGPU_DOORBELL_DIQ = 0x002,
548 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
549 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
550 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
551 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
552 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
553 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
554 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
555 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
556 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
557 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
558 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
559 AMDGPU_DOORBELL_IH = 0x1E8,
560 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
561 AMDGPU_DOORBELL_INVALID = 0xFFFF
562} AMDGPU_DOORBELL_ASSIGNMENT;
563
564struct amdgpu_doorbell {
565 /* doorbell mmio */
566 resource_size_t base;
567 resource_size_t size;
568 u32 __iomem *ptr;
569 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
570};
571
39807b93
KW		 572/*
573 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
574 */
575typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
576{
577 /*
578 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
579 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
580 * Compute related doorbells are allocated from 0x00 to 0x8a
581 */
582
583
584 /* kernel scheduling */
585 AMDGPU_DOORBELL64_KIQ = 0x00,
586
587 /* HSA interface queue and debug queue */
588 AMDGPU_DOORBELL64_HIQ = 0x01,
589 AMDGPU_DOORBELL64_DIQ = 0x02,
590
591 /* Compute engines */
592 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
593 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
594 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
595 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
596 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
597 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
598 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
599 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
600
601 /* User queue doorbell range (128 doorbells) */
602 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
603 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
604
605 /* Graphics engine */
606 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
607
608 /*
609 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
610 * Graphics voltage island aperture 1
611 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
612 */
613
614 /* sDMA engines */
615 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
616 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
617 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
618 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
619
620 /* Interrupt handler */
621 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
622 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
623 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
624
e6b3ecb4
ML		 625 /* VCN engine use 32 bits doorbell */
626 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
627 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
628 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
629 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
630
631 /* overlap the doorbell assignment with VCN as they are mutually exclusive
632 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
633 */
4ed11d79
FM		 634 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
635 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
636 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
637 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
638
639 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
640 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
641 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
642 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
39807b93
KW		 643
644 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
645 AMDGPU_DOORBELL64_INVALID = 0xFFFF
646} AMDGPU_DOORBELL64_ASSIGNMENT;
647
648
97b2e202
AD		 649void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
650 phys_addr_t *aperture_base,
651 size_t *aperture_size,
652 size_t *start_offset);
653
654/*
655 * IRQS.
656 */
657
658struct amdgpu_flip_work {
325cbba1 659 struct delayed_work flip_work;
97b2e202
AD		 660 struct work_struct unpin_work;
661 struct amdgpu_device *adev;
662 int crtc_id;
325cbba1 663 u32 target_vblank;
97b2e202
AD		 664 uint64_t base;
665 struct drm_pending_vblank_event *event;
765e7fbf 666 struct amdgpu_bo *old_abo;
f54d1867 667 struct dma_fence *excl;
1ffd2652 668 unsigned shared_count;
f54d1867
CW		 669 struct dma_fence **shared;
670 struct dma_fence_cb cb;
cb9e59d7 671 bool async;
97b2e202
AD		 672};
673
674
675/*
676 * CP & rings.
677 */
678
679struct amdgpu_ib {
680 struct amdgpu_sa_bo *sa_bo;
681 uint32_t length_dw;
682 uint64_t gpu_addr;
683 uint32_t *ptr;
de807f81 684 uint32_t flags;
97b2e202
AD		 685};
686
62250a91 687extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 688
50838c8c 689int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 690 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 691int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
692 struct amdgpu_job **job);
b6723c8d 693
a5fb4ec2 694void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 695void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 696int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa 697 struct amd_sched_entity *entity, void *owner,
f54d1867 698 struct dma_fence **f);
8b4fb00b 699
effd924d
AR		 700/*
701 * Queue manager
702 */
703struct amdgpu_queue_mapper {
704 int hw_ip;
705 struct mutex lock;
706 /* protected by lock */
707 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
708};
709
710struct amdgpu_queue_mgr {
711 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
712};
713
714int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
715 struct amdgpu_queue_mgr *mgr);
716int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
717 struct amdgpu_queue_mgr *mgr);
718int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
719 struct amdgpu_queue_mgr *mgr,
fa7c7939 720 u32 hw_ip, u32 instance, u32 ring,
effd924d
AR		 721 struct amdgpu_ring **out_ring);
722
97b2e202
AD		 723/*
724 * context related structures
725 */
726
21c16bf6 727struct amdgpu_ctx_ring {
91404fb2 728 uint64_t sequence;
f54d1867 729 struct dma_fence **fences;
91404fb2 730 struct amd_sched_entity entity;
21c16bf6
CK		 731};
732
97b2e202 733struct amdgpu_ctx {
0b492a4c 734 struct kref refcount;
9cb7e5a9 735 struct amdgpu_device *adev;
effd924d 736 struct amdgpu_queue_mgr queue_mgr;
0b492a4c 737 unsigned reset_counter;
e55f2b64 738 uint32_t vram_lost_counter;
21c16bf6 739 spinlock_t ring_lock;
f54d1867 740 struct dma_fence **fences;
21c16bf6 741 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
e55f2b64 742 bool preamble_presented;
c23be4ae
AR		 743 enum amd_sched_priority init_priority;
744 enum amd_sched_priority override_priority;
0ae94444 745 struct mutex lock;
97b2e202
AD		 746};
747
748struct amdgpu_ctx_mgr {
0b492a4c
AD		 749 struct amdgpu_device *adev;
750 struct mutex lock;
751 /* protected by lock */
752 struct idr ctx_handles;
97b2e202
AD		 753};
754
0b492a4c
AD		 755struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
756int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
757
eb01abc7
ML		 758int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
759 struct dma_fence *fence, uint64_t *seq);
f54d1867 760struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6 761 struct amdgpu_ring *ring, uint64_t seq);
c23be4ae
AR		 762void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
763 enum amd_sched_priority priority);
21c16bf6 764
0b492a4c
AD		 765int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
766 struct drm_file *filp);
767
0ae94444
AG		 768int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
769
efd4ccb5
CK		 770void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
771void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 772
0ae94444 773
97b2e202
AD		 774/*
775 * file private structure
776 */
777
778struct amdgpu_fpriv {
779 struct amdgpu_vm vm;
b85891bd 780 struct amdgpu_bo_va *prt_va;
0f4b3c68 781 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 782 struct mutex bo_list_lock;
783 struct idr bo_list_handles;
0b492a4c 784 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 785};
786
787/*
788 * residency list
789 */
9124a398
CK		 790struct amdgpu_bo_list_entry {
791 struct amdgpu_bo *robj;
792 struct ttm_validate_buffer tv;
793 struct amdgpu_bo_va *bo_va;
794 uint32_t priority;
795 struct page **user_pages;
796 int user_invalidated;
797};
97b2e202
AD		 798
799struct amdgpu_bo_list {
800 struct mutex lock;
5ac55629
AX		 801 struct rcu_head rhead;
802 struct kref refcount;
97b2e202
AD		 803 struct amdgpu_bo *gds_obj;
804 struct amdgpu_bo *gws_obj;
805 struct amdgpu_bo *oa_obj;
211dff55 806 unsigned first_userptr;
97b2e202
AD		 807 unsigned num_entries;
808 struct amdgpu_bo_list_entry *array;
809};
810
811struct amdgpu_bo_list *
812amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 813void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
814 struct list_head *validated);
97b2e202
AD		 815void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
816void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
817
818/*
819 * GFX stuff
820 */
821#include "clearstate_defs.h"
822
79e5412c
AD		 823struct amdgpu_rlc_funcs {
824 void (*enter_safe_mode)(struct amdgpu_device *adev);
825 void (*exit_safe_mode)(struct amdgpu_device *adev);
826};
827
97b2e202
AD		 828struct amdgpu_rlc {
829 /* for power gating */
830 struct amdgpu_bo *save_restore_obj;
831 uint64_t save_restore_gpu_addr;
832 volatile uint32_t *sr_ptr;
833 const u32 *reg_list;
834 u32 reg_list_size;
835 /* for clear state */
836 struct amdgpu_bo *clear_state_obj;
837 uint64_t clear_state_gpu_addr;
838 volatile uint32_t *cs_ptr;
839 const struct cs_section_def *cs_data;
840 u32 clear_state_size;
841 /* for cp tables */
842 struct amdgpu_bo *cp_table_obj;
843 uint64_t cp_table_gpu_addr;
844 volatile uint32_t *cp_table_ptr;
845 u32 cp_table_size;
79e5412c
AD		 846
847 /* safe mode for updating CG/PG state */
848 bool in_safe_mode;
849 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 850
851 /* for firmware data */
852 u32 save_and_restore_offset;
853 u32 clear_state_descriptor_offset;
854 u32 avail_scratch_ram_locations;
855 u32 reg_restore_list_size;
856 u32 reg_list_format_start;
857 u32 reg_list_format_separate_start;
858 u32 starting_offsets_start;
859 u32 reg_list_format_size_bytes;
860 u32 reg_list_size_bytes;
861
862 u32 *register_list_format;
863 u32 *register_restore;
97b2e202
AD		 864};
865
78c16834
AR		 866#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
867
97b2e202
AD		 868struct amdgpu_mec {
869 struct amdgpu_bo *hpd_eop_obj;
870 u64 hpd_eop_gpu_addr;
b1023571
KW		 871 struct amdgpu_bo *mec_fw_obj;
872 u64 mec_fw_gpu_addr;
97b2e202 873 u32 num_mec;
42794b27
AR		 874 u32 num_pipe_per_mec;
875 u32 num_queue_per_pipe;
59a82d7d 876 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
78c16834
AR		 877
878 /* These are the resources for which amdgpu takes ownership */
879 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 880};
881
4e638ae9
XY		 882struct amdgpu_kiq {
883 u64 eop_gpu_addr;
884 struct amdgpu_bo *eop_obj;
43ca8efa 885 spinlock_t ring_lock;
4e638ae9
XY		 886 struct amdgpu_ring ring;
887 struct amdgpu_irq_src irq;
888};
889
97b2e202
AD		 890/*
891 * GPU scratch registers structures, functions & helpers
892 */
893struct amdgpu_scratch {
894 unsigned num_reg;
895 uint32_t reg_base;
50261151 896 uint32_t free_mask;
97b2e202
AD		 897};
898
899/*
900 * GFX configurations
901 */
e3fa7630
AD		 902#define AMDGPU_GFX_MAX_SE 4
903#define AMDGPU_GFX_MAX_SH_PER_SE 2
904
905struct amdgpu_rb_config {
906 uint32_t rb_backend_disable;
907 uint32_t user_rb_backend_disable;
908 uint32_t raster_config;
909 uint32_t raster_config_1;
910};
911
d0e95758
AG		 912struct gb_addr_config {
913 uint16_t pipe_interleave_size;
914 uint8_t num_pipes;
915 uint8_t max_compress_frags;
916 uint8_t num_banks;
917 uint8_t num_se;
918 uint8_t num_rb_per_se;
919};
920
ea323f88 921struct amdgpu_gfx_config {
97b2e202
AD		 922 unsigned max_shader_engines;
923 unsigned max_tile_pipes;
924 unsigned max_cu_per_sh;
925 unsigned max_sh_per_se;
926 unsigned max_backends_per_se;
927 unsigned max_texture_channel_caches;
928 unsigned max_gprs;
929 unsigned max_gs_threads;
930 unsigned max_hw_contexts;
931 unsigned sc_prim_fifo_size_frontend;
932 unsigned sc_prim_fifo_size_backend;
933 unsigned sc_hiz_tile_fifo_size;
934 unsigned sc_earlyz_tile_fifo_size;
935
936 unsigned num_tile_pipes;
937 unsigned backend_enable_mask;
938 unsigned mem_max_burst_length_bytes;
939 unsigned mem_row_size_in_kb;
940 unsigned shader_engine_tile_size;
941 unsigned num_gpus;
942 unsigned multi_gpu_tile_size;
943 unsigned mc_arb_ramcfg;
944 unsigned gb_addr_config;
8f8e00c1 945 unsigned num_rbs;
408bfe7c
JZ		 946 unsigned gs_vgt_table_depth;
947 unsigned gs_prim_buffer_depth;
97b2e202
AD		 948
949 uint32_t tile_mode_array[32];
950 uint32_t macrotile_mode_array[16];
e3fa7630 951
d0e95758 952 struct gb_addr_config gb_addr_config_fields;
e3fa7630 953 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 954
955 /* gfx configure feature */
956 uint32_t double_offchip_lds_buf;
97b2e202
AD		 957};
958
7dae69a2 959struct amdgpu_cu_info {
51fd0370 960 uint32_t max_waves_per_simd;
408bfe7c 961 uint32_t wave_front_size;
51fd0370
HZ		 962 uint32_t max_scratch_slots_per_cu;
963 uint32_t lds_size;
dbfe85ea
FC		 964
965 /* total active CU number */
966 uint32_t number;
967 uint32_t ao_cu_mask;
968 uint32_t ao_cu_bitmap[4][4];
7dae69a2
AD		 969 uint32_t bitmap[4][4];
970};
971
b95e31fd
AD		 972struct amdgpu_gfx_funcs {
973 /* get the gpu clock counter */
974 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 975 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 976 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 977 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
978 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 979};
980
bce23e00
AD		 981struct amdgpu_ngg_buf {
982 struct amdgpu_bo *bo;
983 uint64_t gpu_addr;
984 uint32_t size;
985 uint32_t bo_size;
986};
987
988enum {
af8baf15
GR		 989 NGG_PRIM = 0,
990 NGG_POS,
991 NGG_CNTL,
992 NGG_PARAM,
bce23e00
AD		 993 NGG_BUF_MAX
994};
995
996struct amdgpu_ngg {
997 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
998 uint32_t gds_reserve_addr;
999 uint32_t gds_reserve_size;
1000 bool init;
1001};
1002
97b2e202
AD		 1003struct amdgpu_gfx {
1004 struct mutex gpu_clock_mutex;
ea323f88 1005 struct amdgpu_gfx_config config;
97b2e202
AD		 1006 struct amdgpu_rlc rlc;
1007 struct amdgpu_mec mec;
4e638ae9 1008 struct amdgpu_kiq kiq;
97b2e202
AD		 1009 struct amdgpu_scratch scratch;
1010 const struct firmware *me_fw; /* ME firmware */
1011 uint32_t me_fw_version;
1012 const struct firmware *pfp_fw; /* PFP firmware */
1013 uint32_t pfp_fw_version;
1014 const struct firmware *ce_fw; /* CE firmware */
1015 uint32_t ce_fw_version;
1016 const struct firmware *rlc_fw; /* RLC firmware */
1017 uint32_t rlc_fw_version;
1018 const struct firmware *mec_fw; /* MEC firmware */
1019 uint32_t mec_fw_version;
1020 const struct firmware *mec2_fw; /* MEC2 firmware */
1021 uint32_t mec2_fw_version;
02558a00
KW		 1022 uint32_t me_feature_version;
1023 uint32_t ce_feature_version;
1024 uint32_t pfp_feature_version;
351643d7
JZ		 1025 uint32_t rlc_feature_version;
1026 uint32_t mec_feature_version;
1027 uint32_t mec2_feature_version;
97b2e202
AD		 1028 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1029 unsigned num_gfx_rings;
1030 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1031 unsigned num_compute_rings;
1032 struct amdgpu_irq_src eop_irq;
1033 struct amdgpu_irq_src priv_reg_irq;
1034 struct amdgpu_irq_src priv_inst_irq;
1035 /* gfx status */
7dae69a2 1036 uint32_t gfx_current_status;
a101a899 1037 /* ce ram size*/
7dae69a2
AD		 1038 unsigned ce_ram_size;
1039 struct amdgpu_cu_info cu_info;
b95e31fd 1040 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1041
1042 /* reset mask */
1043 uint32_t grbm_soft_reset;
1044 uint32_t srbm_soft_reset;
b4e40676
DP		 1045 /* s3/s4 mask */
1046 bool in_suspend;
bce23e00
AD		 1047 /* NGG */
1048 struct amdgpu_ngg ngg;
b8866c26
AR		 1049
1050 /* pipe reservation */
1051 struct mutex pipe_reserve_mutex;
1052 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 1053};
1054
b07c60c0 1055int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1056 unsigned size, struct amdgpu_ib *ib);
4d9c514d 1057void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 1058 struct dma_fence *f);
b07c60c0 1059int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 1060 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1061 struct dma_fence **f);
97b2e202
AD		 1062int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1063void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1064int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 1065
1066/*
1067 * CS.
1068 */
1069struct amdgpu_cs_chunk {
1070 uint32_t chunk_id;
1071 uint32_t length_dw;
758ac17f 1072 void *kdata;
97b2e202
AD		 1073};
1074
1075struct amdgpu_cs_parser {
1076 struct amdgpu_device *adev;
1077 struct drm_file *filp;
3cb485f3 1078 struct amdgpu_ctx *ctx;
c3cca41e 1079
97b2e202
AD		 1080 /* chunks */
1081 unsigned nchunks;
1082 struct amdgpu_cs_chunk *chunks;
97b2e202 1083
50838c8c
CK		 1084 /* scheduler job object */
1085 struct amdgpu_job *job;
97b2e202 1086
c3cca41e
CK		 1087 /* buffer objects */
1088 struct ww_acquire_ctx ticket;
1089 struct amdgpu_bo_list *bo_list;
3fe89771 1090 struct amdgpu_mn *mn;
c3cca41e
CK		 1091 struct amdgpu_bo_list_entry vm_pd;
1092 struct list_head validated;
f54d1867 1093 struct dma_fence *fence;
c3cca41e 1094 uint64_t bytes_moved_threshold;
00f06b24 1095 uint64_t bytes_moved_vis_threshold;
c3cca41e 1096 uint64_t bytes_moved;
00f06b24 1097 uint64_t bytes_moved_vis;
662bfa61 1098 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1099
1100 /* user fence */
91acbeb6 1101 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 1102
1103 unsigned num_post_dep_syncobjs;
1104 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 1105};
1106
753ad49c
ML		 1107#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1108#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1109#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1110
bb977d37
CZ		 1111struct amdgpu_job {
1112 struct amd_sched_job base;
1113 struct amdgpu_device *adev;
edf600da 1114 struct amdgpu_vm *vm;
b07c60c0 1115 struct amdgpu_ring *ring;
e86f9cee 1116 struct amdgpu_sync sync;
a340c7bc 1117 struct amdgpu_sync dep_sync;
df83d1eb 1118 struct amdgpu_sync sched_sync;
bb977d37 1119 struct amdgpu_ib *ibs;
f54d1867 1120 struct dma_fence *fence; /* the hw fence */
753ad49c 1121 uint32_t preamble_status;
bb977d37 1122 uint32_t num_ibs;
e2840221 1123 void *owner;
3aecd24c 1124 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1125 bool vm_needs_flush;
d88bf583
CK		 1126 unsigned vm_id;
1127 uint64_t vm_pd_addr;
1128 uint32_t gds_base, gds_size;
1129 uint32_t gws_base, gws_size;
1130 uint32_t oa_base, oa_size;
14e47f93 1131 uint32_t vram_lost_counter;
758ac17f
CK		 1132
1133 /* user fence handling */
b5f5acbc 1134 uint64_t uf_addr;
758ac17f
CK		 1135 uint64_t uf_sequence;
1136
bb977d37 1137};
a6db8a33
JZ		 1138#define to_amdgpu_job(sched_job) \
1139 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1140
7270f839
CK		 1141static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1142 uint32_t ib_idx, int idx)
97b2e202 1143{
50838c8c 1144 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1145}
1146
7270f839
CK		 1147static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1148 uint32_t ib_idx, int idx,
1149 uint32_t value)
1150{
50838c8c 1151 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1152}
1153
97b2e202
AD		 1154/*
1155 * Writeback
1156 */
896a664c 1157#define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */
97b2e202
AD		 1158
1159struct amdgpu_wb {
1160 struct amdgpu_bo *wb_obj;
1161 volatile uint32_t *wb;
1162 uint64_t gpu_addr;
1163 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1164 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1165};
1166
1167int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1168void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1169
d0dd7f0c
AD		 1170void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1171
97b2e202
AD		 1172/*
1173 * SDMA
1174 */
c113ea1c 1175struct amdgpu_sdma_instance {
97b2e202
AD		 1176 /* SDMA firmware */
1177 const struct firmware *fw;
1178 uint32_t fw_version;
cfa2104f 1179 uint32_t feature_version;
97b2e202
AD		 1180
1181 struct amdgpu_ring ring;
18111de0 1182 bool burst_nop;
97b2e202
AD		 1183};
1184
c113ea1c
AD		 1185struct amdgpu_sdma {
1186 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1187#ifdef CONFIG_DRM_AMDGPU_SI
1188 //SI DMA has a difference trap irq number for the second engine
1189 struct amdgpu_irq_src trap_irq_1;
1190#endif
c113ea1c
AD		 1191 struct amdgpu_irq_src trap_irq;
1192 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1193 int num_instances;
e702a680 1194 uint32_t srbm_soft_reset;
c113ea1c
AD		 1195};
1196
97b2e202
AD		 1197/*
1198 * Firmware
1199 */
e635ee07
HR		 1200enum amdgpu_firmware_load_type {
1201 AMDGPU_FW_LOAD_DIRECT = 0,
1202 AMDGPU_FW_LOAD_SMU,
1203 AMDGPU_FW_LOAD_PSP,
1204};
1205
97b2e202
AD		 1206struct amdgpu_firmware {
1207 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1208 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1209 struct amdgpu_bo *fw_buf;
1210 unsigned int fw_size;
2445b227 1211 unsigned int max_ucodes;
0e5ca0d1
HR		 1212 /* firmwares are loaded by psp instead of smu from vega10 */
1213 const struct amdgpu_psp_funcs *funcs;
1214 struct amdgpu_bo *rbuf;
1215 struct mutex mutex;
ab4fe3e1
HR		 1216
1217 /* gpu info firmware data pointer */
1218 const struct firmware *gpu_info_fw;
d59c026b
ML		 1219
1220 void *fw_buf_ptr;
1221 uint64_t fw_buf_mc;
97b2e202
AD		 1222};
1223
1224/*
1225 * Benchmarking
1226 */
1227void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1228
1229
1230/*
1231 * Testing
1232 */
1233void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 1234
97b2e202
AD		 1235/*
1236 * Debugfs
1237 */
1238struct amdgpu_debugfs {
06ab6832 1239 const struct drm_info_list *files;
97b2e202
AD		 1240 unsigned num_files;
1241};
1242
1243int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1244 const struct drm_info_list *files,
97b2e202
AD		 1245 unsigned nfiles);
1246int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1247
1248#if defined(CONFIG_DEBUG_FS)
1249int amdgpu_debugfs_init(struct drm_minor *minor);
97b2e202
AD		 1250#endif
1251
50ab2533
HR		 1252int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1253
97b2e202
AD		 1254/*
1255 * amdgpu smumgr functions
1256 */
1257struct amdgpu_smumgr_funcs {
1258 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1259 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1260 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1261};
1262
1263/*
1264 * amdgpu smumgr
1265 */
1266struct amdgpu_smumgr {
1267 struct amdgpu_bo *toc_buf;
1268 struct amdgpu_bo *smu_buf;
1269 /* asic priv smu data */
1270 void *priv;
1271 spinlock_t smu_lock;
1272 /* smumgr functions */
1273 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1274 /* ucode loading complete flag */
1275 uint32_t fw_flags;
1276};
1277
1278/*
1279 * ASIC specific register table accessible by UMD
1280 */
1281struct amdgpu_allowed_register_entry {
1282 uint32_t reg_offset;
97b2e202
AD		 1283 bool grbm_indexed;
1284};
1285
97b2e202
AD		 1286/*
1287 * ASIC specific functions.
1288 */
1289struct amdgpu_asic_funcs {
1290 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1291 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1292 u8 *bios, u32 length_bytes);
97b2e202
AD		 1293 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1294 u32 sh_num, u32 reg_offset, u32 *value);
1295 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1296 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1297 /* get the reference clock */
1298 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1299 /* MM block clocks */
1300 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1301 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1302 /* static power management */
1303 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1304 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1305 /* get config memsize register */
1306 u32 (*get_config_memsize)(struct amdgpu_device *adev);
97b2e202
AD		 1307};
1308
1309/*
1310 * IOCTL.
1311 */
1312int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1313 struct drm_file *filp);
1314int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1315 struct drm_file *filp);
1316
1317int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1318 struct drm_file *filp);
1319int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1320 struct drm_file *filp);
1321int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1322 struct drm_file *filp);
1323int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1324 struct drm_file *filp);
1325int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1326 struct drm_file *filp);
1327int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1328 struct drm_file *filp);
1329int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 1330int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1331 struct drm_file *filp);
97b2e202 1332int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1333int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1334 struct drm_file *filp);
97b2e202
AD		 1335
1336int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1337 struct drm_file *filp);
1338
1339/* VRAM scratch page for HDP bug, default vram page */
1340struct amdgpu_vram_scratch {
1341 struct amdgpu_bo *robj;
1342 volatile uint32_t *ptr;
1343 u64 gpu_addr;
1344};
1345
1346/*
1347 * ACPI
1348 */
1349struct amdgpu_atif_notification_cfg {
1350 bool enabled;
1351 int command_code;
1352};
1353
1354struct amdgpu_atif_notifications {
1355 bool display_switch;
1356 bool expansion_mode_change;
1357 bool thermal_state;
1358 bool forced_power_state;
1359 bool system_power_state;
1360 bool display_conf_change;
1361 bool px_gfx_switch;
1362 bool brightness_change;
1363 bool dgpu_display_event;
1364};
1365
1366struct amdgpu_atif_functions {
1367 bool system_params;
1368 bool sbios_requests;
1369 bool select_active_disp;
1370 bool lid_state;
1371 bool get_tv_standard;
1372 bool set_tv_standard;
1373 bool get_panel_expansion_mode;
1374 bool set_panel_expansion_mode;
1375 bool temperature_change;
1376 bool graphics_device_types;
1377};
1378
1379struct amdgpu_atif {
1380 struct amdgpu_atif_notifications notifications;
1381 struct amdgpu_atif_functions functions;
1382 struct amdgpu_atif_notification_cfg notification_cfg;
1383 struct amdgpu_encoder *encoder_for_bl;
1384};
1385
1386struct amdgpu_atcs_functions {
1387 bool get_ext_state;
1388 bool pcie_perf_req;
1389 bool pcie_dev_rdy;
1390 bool pcie_bus_width;
1391};
1392
1393struct amdgpu_atcs {
1394 struct amdgpu_atcs_functions functions;
1395};
1396
a05502e5
HC		 1397/*
1398 * Firmware VRAM reservation
1399 */
1400struct amdgpu_fw_vram_usage {
1401 u64 start_offset;
1402 u64 size;
1403 struct amdgpu_bo *reserved_bo;
1404 void *va;
1405};
1406
1407int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
1408
d03846af
CZ		 1409/*
1410 * CGS
1411 */
110e6f26
DA		 1412struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1413void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1414
97b2e202
AD		 1415/*
1416 * Core structure, functions and helpers.
1417 */
1418typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1419typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1420
1421typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1422typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1423
0c49e0b8 1424#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 1425struct amdgpu_device {
1426 struct device *dev;
1427 struct drm_device *ddev;
1428 struct pci_dev *pdev;
97b2e202 1429
a8fe58ce
MB		 1430#ifdef CONFIG_DRM_AMD_ACP
1431 struct amdgpu_acp acp;
1432#endif
1433
97b2e202 1434 /* ASIC */
2f7d10b3 1435 enum amd_asic_type asic_type;
97b2e202
AD		 1436 uint32_t family;
1437 uint32_t rev_id;
1438 uint32_t external_rev_id;
1439 unsigned long flags;
1440 int usec_timeout;
1441 const struct amdgpu_asic_funcs *asic_funcs;
1442 bool shutdown;
97b2e202
AD		 1443 bool need_dma32;
1444 bool accel_working;
edf600da 1445 struct work_struct reset_work;
97b2e202
AD		 1446 struct notifier_block acpi_nb;
1447 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1448 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1449 unsigned debugfs_count;
97b2e202 1450#if defined(CONFIG_DEBUG_FS)
adcec288 1451 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1452#endif
1453 struct amdgpu_atif atif;
1454 struct amdgpu_atcs atcs;
1455 struct mutex srbm_mutex;
1456 /* GRBM index mutex. Protects concurrent access to GRBM index */
1457 struct mutex grbm_idx_mutex;
1458 struct dev_pm_domain vga_pm_domain;
1459 bool have_disp_power_ref;
1460
1461 /* BIOS */
0cdd5005 1462 bool is_atom_fw;
97b2e202 1463 uint8_t *bios;
a9f5db9c 1464 uint32_t bios_size;
5af2c10d 1465 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 1466 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1467 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1468
1469 /* Register/doorbell mmio */
1470 resource_size_t rmmio_base;
1471 resource_size_t rmmio_size;
1472 void __iomem *rmmio;
1473 /* protects concurrent MM_INDEX/DATA based register access */
1474 spinlock_t mmio_idx_lock;
1475 /* protects concurrent SMC based register access */
1476 spinlock_t smc_idx_lock;
1477 amdgpu_rreg_t smc_rreg;
1478 amdgpu_wreg_t smc_wreg;
1479 /* protects concurrent PCIE register access */
1480 spinlock_t pcie_idx_lock;
1481 amdgpu_rreg_t pcie_rreg;
1482 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1483 amdgpu_rreg_t pciep_rreg;
1484 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1485 /* protects concurrent UVD register access */
1486 spinlock_t uvd_ctx_idx_lock;
1487 amdgpu_rreg_t uvd_ctx_rreg;
1488 amdgpu_wreg_t uvd_ctx_wreg;
1489 /* protects concurrent DIDT register access */
1490 spinlock_t didt_idx_lock;
1491 amdgpu_rreg_t didt_rreg;
1492 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1493 /* protects concurrent gc_cac register access */
1494 spinlock_t gc_cac_idx_lock;
1495 amdgpu_rreg_t gc_cac_rreg;
1496 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 1497 /* protects concurrent se_cac register access */
1498 spinlock_t se_cac_idx_lock;
1499 amdgpu_rreg_t se_cac_rreg;
1500 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 1501 /* protects concurrent ENDPOINT (audio) register access */
1502 spinlock_t audio_endpt_idx_lock;
1503 amdgpu_block_rreg_t audio_endpt_rreg;
1504 amdgpu_block_wreg_t audio_endpt_wreg;
1505 void __iomem *rio_mem;
1506 resource_size_t rio_mem_size;
1507 struct amdgpu_doorbell doorbell;
1508
1509 /* clock/pll info */
1510 struct amdgpu_clock clock;
1511
1512 /* MC */
1513 struct amdgpu_mc mc;
1514 struct amdgpu_gart gart;
1515 struct amdgpu_dummy_page dummy_page;
1516 struct amdgpu_vm_manager vm_manager;
e60f8db5 1517 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1518
1519 /* memory management */
1520 struct amdgpu_mman mman;
97b2e202
AD		 1521 struct amdgpu_vram_scratch vram_scratch;
1522 struct amdgpu_wb wb;
97b2e202 1523 atomic64_t num_bytes_moved;
dbd5ed60 1524 atomic64_t num_evictions;
68e2c5ff 1525 atomic64_t num_vram_cpu_page_faults;
d94aed5a 1526 atomic_t gpu_reset_counter;
f1892138 1527 atomic_t vram_lost_counter;
97b2e202 1528
95844d20
MO		 1529 /* data for buffer migration throttling */
1530 struct {
1531 spinlock_t lock;
1532 s64 last_update_us;
1533 s64 accum_us; /* accumulated microseconds */
00f06b24 1534 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 1535 u32 log2_max_MBps;
1536 } mm_stats;
1537
97b2e202 1538 /* display */
9accf2fd 1539 bool enable_virtual_display;
97b2e202 1540 struct amdgpu_mode_info mode_info;
4562236b 1541 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 1542 struct work_struct hotplug_work;
1543 struct amdgpu_irq_src crtc_irq;
1544 struct amdgpu_irq_src pageflip_irq;
1545 struct amdgpu_irq_src hpd_irq;
1546
1547 /* rings */
76bf0db5 1548 u64 fence_context;
97b2e202
AD		 1549 unsigned num_rings;
1550 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1551 bool ib_pool_ready;
1552 struct amdgpu_sa_manager ring_tmp_bo;
1553
1554 /* interrupts */
1555 struct amdgpu_irq irq;
1556
1f7371b2
AD		 1557 /* powerplay */
1558 struct amd_powerplay powerplay;
f3898ea1 1559 bool pp_force_state_enabled;
1f7371b2 1560
97b2e202
AD		 1561 /* dpm */
1562 struct amdgpu_pm pm;
1563 u32 cg_flags;
1564 u32 pg_flags;
1565
1566 /* amdgpu smumgr */
1567 struct amdgpu_smumgr smu;
1568
1569 /* gfx */
1570 struct amdgpu_gfx gfx;
1571
1572 /* sdma */
c113ea1c 1573 struct amdgpu_sdma sdma;
97b2e202 1574
b43aaee6
LL		 1575 /* uvd */
1576 struct amdgpu_uvd uvd;
1577
1578 /* vce */
1579 struct amdgpu_vce vce;
1580
1581 /* vcn */
1582 struct amdgpu_vcn vcn;
97b2e202
AD		 1583
1584 /* firmwares */
1585 struct amdgpu_firmware firmware;
1586
0e5ca0d1
HR		 1587 /* PSP */
1588 struct psp_context psp;
1589
97b2e202
AD		 1590 /* GDS */
1591 struct amdgpu_gds gds;
1592
4562236b
HW		 1593 /* display related functionality */
1594 struct amdgpu_display_manager dm;
1595
a1255107 1596 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1597 int num_ip_blocks;
97b2e202
AD		 1598 struct mutex mn_lock;
1599 DECLARE_HASHTABLE(mn_hash, 7);
1600
1601 /* tracking pinned memory */
1602 u64 vram_pin_size;
e131b914 1603 u64 invisible_pin_size;
97b2e202 1604 u64 gart_pin_size;
130e0371
OG		 1605
1606 /* amdkfd interface */
1607 struct kfd_dev *kfd;
23ca0e4e 1608
2dc80b00
S		 1609 /* delayed work_func for deferring clockgating during resume */
1610 struct delayed_work late_init_work;
1611
5a5099cb 1612 struct amdgpu_virt virt;
a05502e5
HC		 1613 /* firmware VRAM reservation */
1614 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 1615
1616 /* link all shadow bo */
1617 struct list_head shadow_list;
1618 struct mutex shadow_list_lock;
5c1354bd
CZ		 1619 /* link all gtt */
1620 spinlock_t gtt_list_lock;
1621 struct list_head gtt_list;
795f2813
AR		 1622 /* keep an lru list of rings by HW IP */
1623 struct list_head ring_lru_list;
1624 spinlock_t ring_lru_list_lock;
5c1354bd 1625
c836fec5
JQ		 1626 /* record hw reset is performed */
1627 bool has_hw_reset;
0c49e0b8 1628 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 1629
47ed4e1c
KW		 1630 /* record last mm index being written through WREG32*/
1631 unsigned long last_mm_index;
3224a12b 1632 bool in_sriov_reset;
97b2e202
AD		 1633};
1634
a7d64de6
CK		 1635static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1636{
1637 return container_of(bdev, struct amdgpu_device, mman.bdev);
1638}
1639
97b2e202
AD		 1640int amdgpu_device_init(struct amdgpu_device *adev,
1641 struct drm_device *ddev,
1642 struct pci_dev *pdev,
1643 uint32_t flags);
1644void amdgpu_device_fini(struct amdgpu_device *adev);
1645int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1646
1647uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1648 uint32_t acc_flags);
97b2e202 1649void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1650 uint32_t acc_flags);
97b2e202
AD		 1651u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1652void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1653
1654u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1655void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1656u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1657void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1658
4562236b
HW		 1659bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1660bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1661
97b2e202
AD		 1662/*
1663 * Registers read & write functions.
1664 */
15d72fd7
ML		 1665
1666#define AMDGPU_REGS_IDX (1<<0)
1667#define AMDGPU_REGS_NO_KIQ (1<<1)
1668
1669#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1670#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1671
1672#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1673#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1674#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1675#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1676#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1677#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1678#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1679#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1680#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1681#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1682#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1683#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1684#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1685#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1686#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1687#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1688#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1689#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1690#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1691#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1692#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1693#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1694#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1695#define WREG32_P(reg, val, mask) \
1696 do { \
1697 uint32_t tmp_ = RREG32(reg); \
1698 tmp_ &= (mask); \
1699 tmp_ |= ((val) & ~(mask)); \
1700 WREG32(reg, tmp_); \
1701 } while (0)
1702#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1703#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1704#define WREG32_PLL_P(reg, val, mask) \
1705 do { \
1706 uint32_t tmp_ = RREG32_PLL(reg); \
1707 tmp_ &= (mask); \
1708 tmp_ |= ((val) & ~(mask)); \
1709 WREG32_PLL(reg, tmp_); \
1710 } while (0)
1711#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1712#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1713#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1714
1715#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1716#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1717#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1718#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1719
1720#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1721#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1722
1723#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1724 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1725 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1726
1727#define REG_GET_FIELD(value, reg, field) \
1728 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1729
1730#define WREG32_FIELD(reg, field, val) \
1731 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1732
ccaf3574
TSD		 1733#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1734 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1735
97b2e202
AD		 1736/*
1737 * BIOS helpers.
1738 */
1739#define RBIOS8(i) (adev->bios[i])
1740#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1741#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1742
c113ea1c
AD		 1743static inline struct amdgpu_sdma_instance *
1744amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1745{
1746 struct amdgpu_device *adev = ring->adev;
1747 int i;
1748
c113ea1c
AD		 1749 for (i = 0; i < adev->sdma.num_instances; i++)
1750 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1751 break;
1752
1753 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1754 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1755 else
1756 return NULL;
1757}
1758
97b2e202
AD		 1759/*
1760 * ASICs macro.
1761 */
1762#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1763#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1764#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1765#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1766#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1767#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1768#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1769#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1770#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1771#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1772#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1773#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
97b2e202
AD		 1774#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1775#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
b1166325 1776#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
97b2e202 1777#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1778#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1779#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
5463545b 1780#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
97b2e202
AD		 1781#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1782#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1783#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1784#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1785#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1786#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1787#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1788#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1789#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1790#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1791#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1792#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1793#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1794#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1795#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1796#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1797#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
3b4d68e9 1798#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
9e5d5309 1799#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1800#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1801#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202 1802#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
00ecd8a2 1803#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
97b2e202
AD		 1804#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1805#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
97b2e202
AD		 1806#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1807#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1808#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1809#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1810#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1811#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1812#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1813#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1814#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1815#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1816#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1817#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
c7ae72c0 1818#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1819#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1820#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1821#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1822#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1823#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1824
1825/* Common functions */
1826int amdgpu_gpu_reset(struct amdgpu_device *adev);
3ad81f16 1827bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202 1828void amdgpu_pci_config_reset(struct amdgpu_device *adev);
c836fec5 1829bool amdgpu_need_post(struct amdgpu_device *adev);
97b2e202 1830void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1831
00f06b24
JB		 1832void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1833 u64 num_vis_bytes);
765e7fbf 1834void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1835bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
97b2e202 1836void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
6f02a696 1837void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
97b2e202 1838void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1839int amdgpu_ttm_init(struct amdgpu_device *adev);
1840void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1841void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1842 const u32 *registers,
1843 const u32 array_size);
1844
1845bool amdgpu_device_is_px(struct drm_device *dev);
1846/* atpx handler */
1847#if defined(CONFIG_VGA_SWITCHEROO)
1848void amdgpu_register_atpx_handler(void);
1849void amdgpu_unregister_atpx_handler(void);
a78fe133 1850bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1851bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1852bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1853bool amdgpu_has_atpx(void);
97b2e202
AD		 1854#else
1855static inline void amdgpu_register_atpx_handler(void) {}
1856static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1857static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1858static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1859static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1860static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1861#endif
1862
1863/*
1864 * KMS
1865 */
1866extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1867extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1868
1869int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1870void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1871void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1872int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1873void amdgpu_driver_postclose_kms(struct drm_device *dev,
1874 struct drm_file *file_priv);
faefba95 1875int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1876int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1877int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1878u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1879int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1880void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1881long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1882 unsigned long arg);
1883
97b2e202
AD		 1884/*
1885 * functions used by amdgpu_encoder.c
1886 */
1887struct amdgpu_afmt_acr {
1888 u32 clock;
1889
1890 int n_32khz;
1891 int cts_32khz;
1892
1893 int n_44_1khz;
1894 int cts_44_1khz;
1895
1896 int n_48khz;
1897 int cts_48khz;
1898
1899};
1900
1901struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1902
1903/* amdgpu_acpi.c */
1904#if defined(CONFIG_ACPI)
1905int amdgpu_acpi_init(struct amdgpu_device *adev);
1906void amdgpu_acpi_fini(struct amdgpu_device *adev);
1907bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1908int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1909 u8 perf_req, bool advertise);
1910int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1911#else
1912static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1913static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1914#endif
1915
9cca0b8e
CK		 1916int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1917 uint64_t addr, struct amdgpu_bo **bo,
1918 struct amdgpu_bo_va_mapping **mapping);
97b2e202 1919
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HW		 1920#if defined(CONFIG_DRM_AMD_DC)
1921int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1922#else
1923static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1924#endif
1925
97b2e202 1926#include "amdgpu_object.h"
97b2e202 1927#endif
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