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97b2e202 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __AMDGPU_H__ | |
29 | #define __AMDGPU_H__ | |
30 | ||
31 | #include <linux/atomic.h> | |
32 | #include <linux/wait.h> | |
33 | #include <linux/list.h> | |
34 | #include <linux/kref.h> | |
35 | #include <linux/interval_tree.h> | |
36 | #include <linux/hashtable.h> | |
37 | #include <linux/fence.h> | |
38 | ||
39 | #include <ttm/ttm_bo_api.h> | |
40 | #include <ttm/ttm_bo_driver.h> | |
41 | #include <ttm/ttm_placement.h> | |
42 | #include <ttm/ttm_module.h> | |
43 | #include <ttm/ttm_execbuf_util.h> | |
44 | ||
d03846af | 45 | #include <drm/drmP.h> |
97b2e202 | 46 | #include <drm/drm_gem.h> |
7e5a547f | 47 | #include <drm/amdgpu_drm.h> |
97b2e202 | 48 | |
5fc3aeeb | 49 | #include "amd_shared.h" |
97b2e202 AD |
50 | #include "amdgpu_mode.h" |
51 | #include "amdgpu_ih.h" | |
52 | #include "amdgpu_irq.h" | |
53 | #include "amdgpu_ucode.h" | |
54 | #include "amdgpu_gds.h" | |
1f7371b2 | 55 | #include "amd_powerplay.h" |
97b2e202 | 56 | |
b80d8475 AD |
57 | #include "gpu_scheduler.h" |
58 | ||
97b2e202 AD |
59 | /* |
60 | * Modules parameters. | |
61 | */ | |
62 | extern int amdgpu_modeset; | |
63 | extern int amdgpu_vram_limit; | |
64 | extern int amdgpu_gart_size; | |
65 | extern int amdgpu_benchmarking; | |
66 | extern int amdgpu_testing; | |
67 | extern int amdgpu_audio; | |
68 | extern int amdgpu_disp_priority; | |
69 | extern int amdgpu_hw_i2c; | |
70 | extern int amdgpu_pcie_gen2; | |
71 | extern int amdgpu_msi; | |
72 | extern int amdgpu_lockup_timeout; | |
73 | extern int amdgpu_dpm; | |
74 | extern int amdgpu_smc_load_fw; | |
75 | extern int amdgpu_aspm; | |
76 | extern int amdgpu_runtime_pm; | |
77 | extern int amdgpu_hard_reset; | |
78 | extern unsigned amdgpu_ip_block_mask; | |
79 | extern int amdgpu_bapm; | |
80 | extern int amdgpu_deep_color; | |
81 | extern int amdgpu_vm_size; | |
82 | extern int amdgpu_vm_block_size; | |
d9c13156 | 83 | extern int amdgpu_vm_fault_stop; |
b495bd3a | 84 | extern int amdgpu_vm_debug; |
b80d8475 | 85 | extern int amdgpu_enable_scheduler; |
1333f723 | 86 | extern int amdgpu_sched_jobs; |
4afcb303 | 87 | extern int amdgpu_sched_hw_submission; |
3daea9e3 | 88 | extern int amdgpu_enable_semaphores; |
1f7371b2 | 89 | extern int amdgpu_powerplay; |
cd474ba0 AD |
90 | extern unsigned amdgpu_pcie_gen_cap; |
91 | extern unsigned amdgpu_pcie_lane_cap; | |
97b2e202 | 92 | |
4b559c90 | 93 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
97b2e202 AD |
94 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
95 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
96 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ | |
97 | #define AMDGPU_IB_POOL_SIZE 16 | |
98 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 | |
99 | #define AMDGPUFB_CONN_LIMIT 4 | |
100 | #define AMDGPU_BIOS_NUM_SCRATCH 8 | |
101 | ||
97b2e202 AD |
102 | /* max number of rings */ |
103 | #define AMDGPU_MAX_RINGS 16 | |
104 | #define AMDGPU_MAX_GFX_RINGS 1 | |
105 | #define AMDGPU_MAX_COMPUTE_RINGS 8 | |
106 | #define AMDGPU_MAX_VCE_RINGS 2 | |
107 | ||
36f523a7 JZ |
108 | /* max number of IP instances */ |
109 | #define AMDGPU_MAX_SDMA_INSTANCES 2 | |
110 | ||
97b2e202 AD |
111 | /* number of hw syncs before falling back on blocking */ |
112 | #define AMDGPU_NUM_SYNCS 4 | |
113 | ||
114 | /* hardcode that limit for now */ | |
115 | #define AMDGPU_VA_RESERVED_SIZE (8 << 20) | |
116 | ||
117 | /* hard reset data */ | |
118 | #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b | |
119 | ||
120 | /* reset flags */ | |
121 | #define AMDGPU_RESET_GFX (1 << 0) | |
122 | #define AMDGPU_RESET_COMPUTE (1 << 1) | |
123 | #define AMDGPU_RESET_DMA (1 << 2) | |
124 | #define AMDGPU_RESET_CP (1 << 3) | |
125 | #define AMDGPU_RESET_GRBM (1 << 4) | |
126 | #define AMDGPU_RESET_DMA1 (1 << 5) | |
127 | #define AMDGPU_RESET_RLC (1 << 6) | |
128 | #define AMDGPU_RESET_SEM (1 << 7) | |
129 | #define AMDGPU_RESET_IH (1 << 8) | |
130 | #define AMDGPU_RESET_VMC (1 << 9) | |
131 | #define AMDGPU_RESET_MC (1 << 10) | |
132 | #define AMDGPU_RESET_DISPLAY (1 << 11) | |
133 | #define AMDGPU_RESET_UVD (1 << 12) | |
134 | #define AMDGPU_RESET_VCE (1 << 13) | |
135 | #define AMDGPU_RESET_VCE1 (1 << 14) | |
136 | ||
97b2e202 AD |
137 | /* GFX current status */ |
138 | #define AMDGPU_GFX_NORMAL_MODE 0x00000000L | |
139 | #define AMDGPU_GFX_SAFE_MODE 0x00000001L | |
140 | #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L | |
141 | #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L | |
142 | #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L | |
143 | ||
144 | /* max cursor sizes (in pixels) */ | |
145 | #define CIK_CURSOR_WIDTH 128 | |
146 | #define CIK_CURSOR_HEIGHT 128 | |
147 | ||
148 | struct amdgpu_device; | |
149 | struct amdgpu_fence; | |
150 | struct amdgpu_ib; | |
151 | struct amdgpu_vm; | |
152 | struct amdgpu_ring; | |
153 | struct amdgpu_semaphore; | |
154 | struct amdgpu_cs_parser; | |
bb977d37 | 155 | struct amdgpu_job; |
97b2e202 | 156 | struct amdgpu_irq_src; |
0b492a4c | 157 | struct amdgpu_fpriv; |
97b2e202 AD |
158 | |
159 | enum amdgpu_cp_irq { | |
160 | AMDGPU_CP_IRQ_GFX_EOP = 0, | |
161 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, | |
162 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, | |
163 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, | |
164 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, | |
165 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, | |
166 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, | |
167 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, | |
168 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, | |
169 | ||
170 | AMDGPU_CP_IRQ_LAST | |
171 | }; | |
172 | ||
173 | enum amdgpu_sdma_irq { | |
174 | AMDGPU_SDMA_IRQ_TRAP0 = 0, | |
175 | AMDGPU_SDMA_IRQ_TRAP1, | |
176 | ||
177 | AMDGPU_SDMA_IRQ_LAST | |
178 | }; | |
179 | ||
180 | enum amdgpu_thermal_irq { | |
181 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, | |
182 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, | |
183 | ||
184 | AMDGPU_THERMAL_IRQ_LAST | |
185 | }; | |
186 | ||
97b2e202 | 187 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, |
5fc3aeeb | 188 | enum amd_ip_block_type block_type, |
189 | enum amd_clockgating_state state); | |
97b2e202 | 190 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, |
5fc3aeeb | 191 | enum amd_ip_block_type block_type, |
192 | enum amd_powergating_state state); | |
97b2e202 AD |
193 | |
194 | struct amdgpu_ip_block_version { | |
5fc3aeeb | 195 | enum amd_ip_block_type type; |
97b2e202 AD |
196 | u32 major; |
197 | u32 minor; | |
198 | u32 rev; | |
5fc3aeeb | 199 | const struct amd_ip_funcs *funcs; |
97b2e202 AD |
200 | }; |
201 | ||
202 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 203 | enum amd_ip_block_type type, |
97b2e202 AD |
204 | u32 major, u32 minor); |
205 | ||
206 | const struct amdgpu_ip_block_version * amdgpu_get_ip_block( | |
207 | struct amdgpu_device *adev, | |
5fc3aeeb | 208 | enum amd_ip_block_type type); |
97b2e202 AD |
209 | |
210 | /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ | |
211 | struct amdgpu_buffer_funcs { | |
212 | /* maximum bytes in a single operation */ | |
213 | uint32_t copy_max_bytes; | |
214 | ||
215 | /* number of dw to reserve per operation */ | |
216 | unsigned copy_num_dw; | |
217 | ||
218 | /* used for buffer migration */ | |
c7ae72c0 | 219 | void (*emit_copy_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
220 | /* src addr in bytes */ |
221 | uint64_t src_offset, | |
222 | /* dst addr in bytes */ | |
223 | uint64_t dst_offset, | |
224 | /* number of byte to transfer */ | |
225 | uint32_t byte_count); | |
226 | ||
227 | /* maximum bytes in a single operation */ | |
228 | uint32_t fill_max_bytes; | |
229 | ||
230 | /* number of dw to reserve per operation */ | |
231 | unsigned fill_num_dw; | |
232 | ||
233 | /* used for buffer clearing */ | |
6e7a3840 | 234 | void (*emit_fill_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
235 | /* value to write to memory */ |
236 | uint32_t src_data, | |
237 | /* dst addr in bytes */ | |
238 | uint64_t dst_offset, | |
239 | /* number of byte to fill */ | |
240 | uint32_t byte_count); | |
241 | }; | |
242 | ||
243 | /* provided by hw blocks that can write ptes, e.g., sdma */ | |
244 | struct amdgpu_vm_pte_funcs { | |
245 | /* copy pte entries from GART */ | |
246 | void (*copy_pte)(struct amdgpu_ib *ib, | |
247 | uint64_t pe, uint64_t src, | |
248 | unsigned count); | |
249 | /* write pte one entry at a time with addr mapping */ | |
250 | void (*write_pte)(struct amdgpu_ib *ib, | |
251 | uint64_t pe, | |
252 | uint64_t addr, unsigned count, | |
253 | uint32_t incr, uint32_t flags); | |
254 | /* for linear pte/pde updates without addr mapping */ | |
255 | void (*set_pte_pde)(struct amdgpu_ib *ib, | |
256 | uint64_t pe, | |
257 | uint64_t addr, unsigned count, | |
258 | uint32_t incr, uint32_t flags); | |
259 | /* pad the indirect buffer to the necessary number of dw */ | |
260 | void (*pad_ib)(struct amdgpu_ib *ib); | |
261 | }; | |
262 | ||
263 | /* provided by the gmc block */ | |
264 | struct amdgpu_gart_funcs { | |
265 | /* flush the vm tlb via mmio */ | |
266 | void (*flush_gpu_tlb)(struct amdgpu_device *adev, | |
267 | uint32_t vmid); | |
268 | /* write pte/pde updates using the cpu */ | |
269 | int (*set_pte_pde)(struct amdgpu_device *adev, | |
270 | void *cpu_pt_addr, /* cpu addr of page table */ | |
271 | uint32_t gpu_page_idx, /* pte/pde to update */ | |
272 | uint64_t addr, /* addr to write into pte/pde */ | |
273 | uint32_t flags); /* access flags */ | |
274 | }; | |
275 | ||
276 | /* provided by the ih block */ | |
277 | struct amdgpu_ih_funcs { | |
278 | /* ring read/write ptr handling, called from interrupt context */ | |
279 | u32 (*get_wptr)(struct amdgpu_device *adev); | |
280 | void (*decode_iv)(struct amdgpu_device *adev, | |
281 | struct amdgpu_iv_entry *entry); | |
282 | void (*set_rptr)(struct amdgpu_device *adev); | |
283 | }; | |
284 | ||
285 | /* provided by hw blocks that expose a ring buffer for commands */ | |
286 | struct amdgpu_ring_funcs { | |
287 | /* ring read/write ptr handling */ | |
288 | u32 (*get_rptr)(struct amdgpu_ring *ring); | |
289 | u32 (*get_wptr)(struct amdgpu_ring *ring); | |
290 | void (*set_wptr)(struct amdgpu_ring *ring); | |
291 | /* validating and patching of IBs */ | |
292 | int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); | |
293 | /* command emit functions */ | |
294 | void (*emit_ib)(struct amdgpu_ring *ring, | |
295 | struct amdgpu_ib *ib); | |
296 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, | |
890ee23f | 297 | uint64_t seq, unsigned flags); |
97b2e202 AD |
298 | bool (*emit_semaphore)(struct amdgpu_ring *ring, |
299 | struct amdgpu_semaphore *semaphore, | |
300 | bool emit_wait); | |
301 | void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, | |
302 | uint64_t pd_addr); | |
d2edb07b | 303 | void (*emit_hdp_flush)(struct amdgpu_ring *ring); |
97b2e202 AD |
304 | void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, |
305 | uint32_t gds_base, uint32_t gds_size, | |
306 | uint32_t gws_base, uint32_t gws_size, | |
307 | uint32_t oa_base, uint32_t oa_size); | |
308 | /* testing functions */ | |
309 | int (*test_ring)(struct amdgpu_ring *ring); | |
310 | int (*test_ib)(struct amdgpu_ring *ring); | |
edff0e28 JZ |
311 | /* insert NOP packets */ |
312 | void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); | |
97b2e202 AD |
313 | }; |
314 | ||
315 | /* | |
316 | * BIOS. | |
317 | */ | |
318 | bool amdgpu_get_bios(struct amdgpu_device *adev); | |
319 | bool amdgpu_read_bios(struct amdgpu_device *adev); | |
320 | ||
321 | /* | |
322 | * Dummy page | |
323 | */ | |
324 | struct amdgpu_dummy_page { | |
325 | struct page *page; | |
326 | dma_addr_t addr; | |
327 | }; | |
328 | int amdgpu_dummy_page_init(struct amdgpu_device *adev); | |
329 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev); | |
330 | ||
331 | ||
332 | /* | |
333 | * Clocks | |
334 | */ | |
335 | ||
336 | #define AMDGPU_MAX_PPLL 3 | |
337 | ||
338 | struct amdgpu_clock { | |
339 | struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; | |
340 | struct amdgpu_pll spll; | |
341 | struct amdgpu_pll mpll; | |
342 | /* 10 Khz units */ | |
343 | uint32_t default_mclk; | |
344 | uint32_t default_sclk; | |
345 | uint32_t default_dispclk; | |
346 | uint32_t current_dispclk; | |
347 | uint32_t dp_extclk; | |
348 | uint32_t max_pixel_clock; | |
349 | }; | |
350 | ||
351 | /* | |
352 | * Fences. | |
353 | */ | |
354 | struct amdgpu_fence_driver { | |
97b2e202 AD |
355 | uint64_t gpu_addr; |
356 | volatile uint32_t *cpu_addr; | |
357 | /* sync_seq is protected by ring emission lock */ | |
358 | uint64_t sync_seq[AMDGPU_MAX_RINGS]; | |
359 | atomic64_t last_seq; | |
360 | bool initialized; | |
97b2e202 AD |
361 | struct amdgpu_irq_src *irq_src; |
362 | unsigned irq_type; | |
c2776afe | 363 | struct timer_list fallback_timer; |
7f06c236 | 364 | wait_queue_head_t fence_queue; |
97b2e202 AD |
365 | }; |
366 | ||
367 | /* some special values for the owner field */ | |
368 | #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) | |
369 | #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) | |
97b2e202 | 370 | |
890ee23f CZ |
371 | #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) |
372 | #define AMDGPU_FENCE_FLAG_INT (1 << 1) | |
373 | ||
97b2e202 AD |
374 | struct amdgpu_fence { |
375 | struct fence base; | |
4cef9267 | 376 | |
97b2e202 AD |
377 | /* RB, DMA, etc. */ |
378 | struct amdgpu_ring *ring; | |
379 | uint64_t seq; | |
380 | ||
381 | /* filp or special value for fence creator */ | |
382 | void *owner; | |
383 | ||
384 | wait_queue_t fence_wake; | |
385 | }; | |
386 | ||
387 | struct amdgpu_user_fence { | |
388 | /* write-back bo */ | |
389 | struct amdgpu_bo *bo; | |
390 | /* write-back address offset to bo start */ | |
391 | uint32_t offset; | |
392 | }; | |
393 | ||
394 | int amdgpu_fence_driver_init(struct amdgpu_device *adev); | |
395 | void amdgpu_fence_driver_fini(struct amdgpu_device *adev); | |
396 | void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); | |
397 | ||
4f839a24 | 398 | int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); |
97b2e202 AD |
399 | int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, |
400 | struct amdgpu_irq_src *irq_src, | |
401 | unsigned irq_type); | |
5ceb54c6 AD |
402 | void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); |
403 | void amdgpu_fence_driver_resume(struct amdgpu_device *adev); | |
97b2e202 AD |
404 | int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, |
405 | struct amdgpu_fence **fence); | |
406 | void amdgpu_fence_process(struct amdgpu_ring *ring); | |
407 | int amdgpu_fence_wait_next(struct amdgpu_ring *ring); | |
408 | int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); | |
409 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); | |
410 | ||
97b2e202 AD |
411 | bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, |
412 | struct amdgpu_ring *ring); | |
413 | void amdgpu_fence_note_sync(struct amdgpu_fence *fence, | |
414 | struct amdgpu_ring *ring); | |
415 | ||
97b2e202 AD |
416 | /* |
417 | * TTM. | |
418 | */ | |
419 | struct amdgpu_mman { | |
420 | struct ttm_bo_global_ref bo_global_ref; | |
421 | struct drm_global_reference mem_global_ref; | |
422 | struct ttm_bo_device bdev; | |
423 | bool mem_global_referenced; | |
424 | bool initialized; | |
425 | ||
426 | #if defined(CONFIG_DEBUG_FS) | |
427 | struct dentry *vram; | |
428 | struct dentry *gtt; | |
429 | #endif | |
430 | ||
431 | /* buffer handling */ | |
432 | const struct amdgpu_buffer_funcs *buffer_funcs; | |
433 | struct amdgpu_ring *buffer_funcs_ring; | |
434 | }; | |
435 | ||
436 | int amdgpu_copy_buffer(struct amdgpu_ring *ring, | |
437 | uint64_t src_offset, | |
438 | uint64_t dst_offset, | |
439 | uint32_t byte_count, | |
440 | struct reservation_object *resv, | |
c7ae72c0 | 441 | struct fence **fence); |
97b2e202 AD |
442 | int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); |
443 | ||
444 | struct amdgpu_bo_list_entry { | |
445 | struct amdgpu_bo *robj; | |
446 | struct ttm_validate_buffer tv; | |
447 | struct amdgpu_bo_va *bo_va; | |
448 | unsigned prefered_domains; | |
449 | unsigned allowed_domains; | |
450 | uint32_t priority; | |
451 | }; | |
452 | ||
453 | struct amdgpu_bo_va_mapping { | |
454 | struct list_head list; | |
455 | struct interval_tree_node it; | |
456 | uint64_t offset; | |
457 | uint32_t flags; | |
458 | }; | |
459 | ||
460 | /* bo virtual addresses in a specific vm */ | |
461 | struct amdgpu_bo_va { | |
69b576a1 | 462 | struct mutex mutex; |
97b2e202 AD |
463 | /* protected by bo being reserved */ |
464 | struct list_head bo_list; | |
bb1e38a4 | 465 | struct fence *last_pt_update; |
97b2e202 AD |
466 | unsigned ref_count; |
467 | ||
7fc11959 | 468 | /* protected by vm mutex and spinlock */ |
97b2e202 AD |
469 | struct list_head vm_status; |
470 | ||
7fc11959 CK |
471 | /* mappings for this bo_va */ |
472 | struct list_head invalids; | |
473 | struct list_head valids; | |
474 | ||
97b2e202 AD |
475 | /* constant after initialization */ |
476 | struct amdgpu_vm *vm; | |
477 | struct amdgpu_bo *bo; | |
478 | }; | |
479 | ||
7e5a547f CZ |
480 | #define AMDGPU_GEM_DOMAIN_MAX 0x3 |
481 | ||
97b2e202 AD |
482 | struct amdgpu_bo { |
483 | /* Protected by gem.mutex */ | |
484 | struct list_head list; | |
485 | /* Protected by tbo.reserved */ | |
486 | u32 initial_domain; | |
7e5a547f | 487 | struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; |
97b2e202 AD |
488 | struct ttm_placement placement; |
489 | struct ttm_buffer_object tbo; | |
490 | struct ttm_bo_kmap_obj kmap; | |
491 | u64 flags; | |
492 | unsigned pin_count; | |
493 | void *kptr; | |
494 | u64 tiling_flags; | |
495 | u64 metadata_flags; | |
496 | void *metadata; | |
497 | u32 metadata_size; | |
498 | /* list of all virtual address to which this bo | |
499 | * is associated to | |
500 | */ | |
501 | struct list_head va; | |
502 | /* Constant after initialization */ | |
503 | struct amdgpu_device *adev; | |
504 | struct drm_gem_object gem_base; | |
82b9c55b | 505 | struct amdgpu_bo *parent; |
97b2e202 AD |
506 | |
507 | struct ttm_bo_kmap_obj dma_buf_vmap; | |
508 | pid_t pid; | |
509 | struct amdgpu_mn *mn; | |
510 | struct list_head mn_list; | |
511 | }; | |
512 | #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) | |
513 | ||
514 | void amdgpu_gem_object_free(struct drm_gem_object *obj); | |
515 | int amdgpu_gem_object_open(struct drm_gem_object *obj, | |
516 | struct drm_file *file_priv); | |
517 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
518 | struct drm_file *file_priv); | |
519 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); | |
520 | struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); | |
521 | struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, | |
522 | struct dma_buf_attachment *attach, | |
523 | struct sg_table *sg); | |
524 | struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, | |
525 | struct drm_gem_object *gobj, | |
526 | int flags); | |
527 | int amdgpu_gem_prime_pin(struct drm_gem_object *obj); | |
528 | void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); | |
529 | struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); | |
530 | void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); | |
531 | void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); | |
532 | int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); | |
533 | ||
534 | /* sub-allocation manager, it has to be protected by another lock. | |
535 | * By conception this is an helper for other part of the driver | |
536 | * like the indirect buffer or semaphore, which both have their | |
537 | * locking. | |
538 | * | |
539 | * Principe is simple, we keep a list of sub allocation in offset | |
540 | * order (first entry has offset == 0, last entry has the highest | |
541 | * offset). | |
542 | * | |
543 | * When allocating new object we first check if there is room at | |
544 | * the end total_size - (last_object_offset + last_object_size) >= | |
545 | * alloc_size. If so we allocate new object there. | |
546 | * | |
547 | * When there is not enough room at the end, we start waiting for | |
548 | * each sub object until we reach object_offset+object_size >= | |
549 | * alloc_size, this object then become the sub object we return. | |
550 | * | |
551 | * Alignment can't be bigger than page size. | |
552 | * | |
553 | * Hole are not considered for allocation to keep things simple. | |
554 | * Assumption is that there won't be hole (all object on same | |
555 | * alignment). | |
556 | */ | |
557 | struct amdgpu_sa_manager { | |
558 | wait_queue_head_t wq; | |
559 | struct amdgpu_bo *bo; | |
560 | struct list_head *hole; | |
561 | struct list_head flist[AMDGPU_MAX_RINGS]; | |
562 | struct list_head olist; | |
563 | unsigned size; | |
564 | uint64_t gpu_addr; | |
565 | void *cpu_ptr; | |
566 | uint32_t domain; | |
567 | uint32_t align; | |
568 | }; | |
569 | ||
97b2e202 AD |
570 | /* sub-allocation buffer */ |
571 | struct amdgpu_sa_bo { | |
572 | struct list_head olist; | |
573 | struct list_head flist; | |
574 | struct amdgpu_sa_manager *manager; | |
575 | unsigned soffset; | |
576 | unsigned eoffset; | |
4ce9891e | 577 | struct fence *fence; |
97b2e202 AD |
578 | }; |
579 | ||
580 | /* | |
581 | * GEM objects. | |
582 | */ | |
583 | struct amdgpu_gem { | |
584 | struct mutex mutex; | |
585 | struct list_head objects; | |
586 | }; | |
587 | ||
588 | int amdgpu_gem_init(struct amdgpu_device *adev); | |
589 | void amdgpu_gem_fini(struct amdgpu_device *adev); | |
590 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
591 | int alignment, u32 initial_domain, | |
592 | u64 flags, bool kernel, | |
593 | struct drm_gem_object **obj); | |
594 | ||
595 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
596 | struct drm_device *dev, | |
597 | struct drm_mode_create_dumb *args); | |
598 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
599 | struct drm_device *dev, | |
600 | uint32_t handle, uint64_t *offset_p); | |
601 | ||
602 | /* | |
603 | * Semaphores. | |
604 | */ | |
605 | struct amdgpu_semaphore { | |
606 | struct amdgpu_sa_bo *sa_bo; | |
607 | signed waiters; | |
608 | uint64_t gpu_addr; | |
609 | }; | |
610 | ||
611 | int amdgpu_semaphore_create(struct amdgpu_device *adev, | |
612 | struct amdgpu_semaphore **semaphore); | |
613 | bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, | |
614 | struct amdgpu_semaphore *semaphore); | |
615 | bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, | |
616 | struct amdgpu_semaphore *semaphore); | |
617 | void amdgpu_semaphore_free(struct amdgpu_device *adev, | |
618 | struct amdgpu_semaphore **semaphore, | |
4ce9891e | 619 | struct fence *fence); |
97b2e202 AD |
620 | |
621 | /* | |
622 | * Synchronization | |
623 | */ | |
624 | struct amdgpu_sync { | |
625 | struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; | |
16545c32 | 626 | struct fence *sync_to[AMDGPU_MAX_RINGS]; |
f91b3a69 | 627 | DECLARE_HASHTABLE(fences, 4); |
3c62338c | 628 | struct fence *last_vm_update; |
97b2e202 AD |
629 | }; |
630 | ||
631 | void amdgpu_sync_create(struct amdgpu_sync *sync); | |
91e1a520 CK |
632 | int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, |
633 | struct fence *f); | |
97b2e202 AD |
634 | int amdgpu_sync_resv(struct amdgpu_device *adev, |
635 | struct amdgpu_sync *sync, | |
636 | struct reservation_object *resv, | |
637 | void *owner); | |
638 | int amdgpu_sync_rings(struct amdgpu_sync *sync, | |
639 | struct amdgpu_ring *ring); | |
e61235db | 640 | struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); |
f91b3a69 | 641 | int amdgpu_sync_wait(struct amdgpu_sync *sync); |
97b2e202 | 642 | void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, |
4ce9891e | 643 | struct fence *fence); |
97b2e202 AD |
644 | |
645 | /* | |
646 | * GART structures, functions & helpers | |
647 | */ | |
648 | struct amdgpu_mc; | |
649 | ||
650 | #define AMDGPU_GPU_PAGE_SIZE 4096 | |
651 | #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) | |
652 | #define AMDGPU_GPU_PAGE_SHIFT 12 | |
653 | #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) | |
654 | ||
655 | struct amdgpu_gart { | |
656 | dma_addr_t table_addr; | |
657 | struct amdgpu_bo *robj; | |
658 | void *ptr; | |
659 | unsigned num_gpu_pages; | |
660 | unsigned num_cpu_pages; | |
661 | unsigned table_size; | |
662 | struct page **pages; | |
663 | dma_addr_t *pages_addr; | |
664 | bool ready; | |
665 | const struct amdgpu_gart_funcs *gart_funcs; | |
666 | }; | |
667 | ||
668 | int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); | |
669 | void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); | |
670 | int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); | |
671 | void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); | |
672 | int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); | |
673 | void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); | |
674 | int amdgpu_gart_init(struct amdgpu_device *adev); | |
675 | void amdgpu_gart_fini(struct amdgpu_device *adev); | |
676 | void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, | |
677 | int pages); | |
678 | int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, | |
679 | int pages, struct page **pagelist, | |
680 | dma_addr_t *dma_addr, uint32_t flags); | |
681 | ||
682 | /* | |
683 | * GPU MC structures, functions & helpers | |
684 | */ | |
685 | struct amdgpu_mc { | |
686 | resource_size_t aper_size; | |
687 | resource_size_t aper_base; | |
688 | resource_size_t agp_base; | |
689 | /* for some chips with <= 32MB we need to lie | |
690 | * about vram size near mc fb location */ | |
691 | u64 mc_vram_size; | |
692 | u64 visible_vram_size; | |
693 | u64 gtt_size; | |
694 | u64 gtt_start; | |
695 | u64 gtt_end; | |
696 | u64 vram_start; | |
697 | u64 vram_end; | |
698 | unsigned vram_width; | |
699 | u64 real_vram_size; | |
700 | int vram_mtrr; | |
701 | u64 gtt_base_align; | |
702 | u64 mc_mask; | |
703 | const struct firmware *fw; /* MC firmware */ | |
704 | uint32_t fw_version; | |
705 | struct amdgpu_irq_src vm_fault; | |
81c59f54 | 706 | uint32_t vram_type; |
97b2e202 AD |
707 | }; |
708 | ||
709 | /* | |
710 | * GPU doorbell structures, functions & helpers | |
711 | */ | |
712 | typedef enum _AMDGPU_DOORBELL_ASSIGNMENT | |
713 | { | |
714 | AMDGPU_DOORBELL_KIQ = 0x000, | |
715 | AMDGPU_DOORBELL_HIQ = 0x001, | |
716 | AMDGPU_DOORBELL_DIQ = 0x002, | |
717 | AMDGPU_DOORBELL_MEC_RING0 = 0x010, | |
718 | AMDGPU_DOORBELL_MEC_RING1 = 0x011, | |
719 | AMDGPU_DOORBELL_MEC_RING2 = 0x012, | |
720 | AMDGPU_DOORBELL_MEC_RING3 = 0x013, | |
721 | AMDGPU_DOORBELL_MEC_RING4 = 0x014, | |
722 | AMDGPU_DOORBELL_MEC_RING5 = 0x015, | |
723 | AMDGPU_DOORBELL_MEC_RING6 = 0x016, | |
724 | AMDGPU_DOORBELL_MEC_RING7 = 0x017, | |
725 | AMDGPU_DOORBELL_GFX_RING0 = 0x020, | |
726 | AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, | |
727 | AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, | |
728 | AMDGPU_DOORBELL_IH = 0x1E8, | |
729 | AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, | |
730 | AMDGPU_DOORBELL_INVALID = 0xFFFF | |
731 | } AMDGPU_DOORBELL_ASSIGNMENT; | |
732 | ||
733 | struct amdgpu_doorbell { | |
734 | /* doorbell mmio */ | |
735 | resource_size_t base; | |
736 | resource_size_t size; | |
737 | u32 __iomem *ptr; | |
738 | u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ | |
739 | }; | |
740 | ||
741 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
742 | phys_addr_t *aperture_base, | |
743 | size_t *aperture_size, | |
744 | size_t *start_offset); | |
745 | ||
746 | /* | |
747 | * IRQS. | |
748 | */ | |
749 | ||
750 | struct amdgpu_flip_work { | |
751 | struct work_struct flip_work; | |
752 | struct work_struct unpin_work; | |
753 | struct amdgpu_device *adev; | |
754 | int crtc_id; | |
755 | uint64_t base; | |
756 | struct drm_pending_vblank_event *event; | |
757 | struct amdgpu_bo *old_rbo; | |
1ffd2652 CK |
758 | struct fence *excl; |
759 | unsigned shared_count; | |
760 | struct fence **shared; | |
97b2e202 AD |
761 | }; |
762 | ||
763 | ||
764 | /* | |
765 | * CP & rings. | |
766 | */ | |
767 | ||
768 | struct amdgpu_ib { | |
769 | struct amdgpu_sa_bo *sa_bo; | |
770 | uint32_t length_dw; | |
771 | uint64_t gpu_addr; | |
772 | uint32_t *ptr; | |
773 | struct amdgpu_ring *ring; | |
774 | struct amdgpu_fence *fence; | |
775 | struct amdgpu_user_fence *user; | |
776 | struct amdgpu_vm *vm; | |
3cb485f3 | 777 | struct amdgpu_ctx *ctx; |
97b2e202 | 778 | struct amdgpu_sync sync; |
97b2e202 AD |
779 | uint32_t gds_base, gds_size; |
780 | uint32_t gws_base, gws_size; | |
781 | uint32_t oa_base, oa_size; | |
de807f81 | 782 | uint32_t flags; |
5430a3ff CK |
783 | /* resulting sequence number */ |
784 | uint64_t sequence; | |
97b2e202 AD |
785 | }; |
786 | ||
787 | enum amdgpu_ring_type { | |
788 | AMDGPU_RING_TYPE_GFX, | |
789 | AMDGPU_RING_TYPE_COMPUTE, | |
790 | AMDGPU_RING_TYPE_SDMA, | |
791 | AMDGPU_RING_TYPE_UVD, | |
792 | AMDGPU_RING_TYPE_VCE | |
793 | }; | |
794 | ||
c1b69ed0 CZ |
795 | extern struct amd_sched_backend_ops amdgpu_sched_ops; |
796 | ||
3c704e93 CZ |
797 | int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, |
798 | struct amdgpu_ring *ring, | |
799 | struct amdgpu_ib *ibs, | |
800 | unsigned num_ibs, | |
bb977d37 | 801 | int (*free_job)(struct amdgpu_job *), |
1763552e CZ |
802 | void *owner, |
803 | struct fence **fence); | |
3c704e93 | 804 | |
97b2e202 AD |
805 | struct amdgpu_ring { |
806 | struct amdgpu_device *adev; | |
807 | const struct amdgpu_ring_funcs *funcs; | |
808 | struct amdgpu_fence_driver fence_drv; | |
4f839a24 | 809 | struct amd_gpu_scheduler sched; |
97b2e202 | 810 | |
176e1ab1 | 811 | spinlock_t fence_lock; |
97b2e202 AD |
812 | struct mutex *ring_lock; |
813 | struct amdgpu_bo *ring_obj; | |
814 | volatile uint32_t *ring; | |
815 | unsigned rptr_offs; | |
816 | u64 next_rptr_gpu_addr; | |
817 | volatile u32 *next_rptr_cpu_addr; | |
818 | unsigned wptr; | |
819 | unsigned wptr_old; | |
820 | unsigned ring_size; | |
821 | unsigned ring_free_dw; | |
822 | int count_dw; | |
97b2e202 AD |
823 | uint64_t gpu_addr; |
824 | uint32_t align_mask; | |
825 | uint32_t ptr_mask; | |
826 | bool ready; | |
827 | u32 nop; | |
828 | u32 idx; | |
829 | u64 last_semaphore_signal_addr; | |
830 | u64 last_semaphore_wait_addr; | |
831 | u32 me; | |
832 | u32 pipe; | |
833 | u32 queue; | |
834 | struct amdgpu_bo *mqd_obj; | |
835 | u32 doorbell_index; | |
836 | bool use_doorbell; | |
837 | unsigned wptr_offs; | |
838 | unsigned next_rptr_offs; | |
839 | unsigned fence_offs; | |
3cb485f3 | 840 | struct amdgpu_ctx *current_ctx; |
97b2e202 AD |
841 | enum amdgpu_ring_type type; |
842 | char name[16]; | |
4274f5d4 | 843 | bool is_pte_ring; |
97b2e202 AD |
844 | }; |
845 | ||
846 | /* | |
847 | * VM | |
848 | */ | |
849 | ||
850 | /* maximum number of VMIDs */ | |
851 | #define AMDGPU_NUM_VM 16 | |
852 | ||
853 | /* number of entries in page table */ | |
854 | #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) | |
855 | ||
856 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ | |
857 | #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 | |
858 | #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) | |
859 | #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) | |
860 | ||
861 | #define AMDGPU_PTE_VALID (1 << 0) | |
862 | #define AMDGPU_PTE_SYSTEM (1 << 1) | |
863 | #define AMDGPU_PTE_SNOOPED (1 << 2) | |
864 | ||
865 | /* VI only */ | |
866 | #define AMDGPU_PTE_EXECUTABLE (1 << 4) | |
867 | ||
868 | #define AMDGPU_PTE_READABLE (1 << 5) | |
869 | #define AMDGPU_PTE_WRITEABLE (1 << 6) | |
870 | ||
871 | /* PTE (Page Table Entry) fragment field for different page sizes */ | |
872 | #define AMDGPU_PTE_FRAG_4KB (0 << 7) | |
873 | #define AMDGPU_PTE_FRAG_64KB (4 << 7) | |
874 | #define AMDGPU_LOG2_PAGES_PER_FRAG 4 | |
875 | ||
d9c13156 CK |
876 | /* How to programm VM fault handling */ |
877 | #define AMDGPU_VM_FAULT_STOP_NEVER 0 | |
878 | #define AMDGPU_VM_FAULT_STOP_FIRST 1 | |
879 | #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 | |
880 | ||
97b2e202 | 881 | struct amdgpu_vm_pt { |
ee1782c3 CK |
882 | struct amdgpu_bo_list_entry entry; |
883 | uint64_t addr; | |
97b2e202 AD |
884 | }; |
885 | ||
886 | struct amdgpu_vm_id { | |
887 | unsigned id; | |
888 | uint64_t pd_gpu_addr; | |
889 | /* last flushed PD/PT update */ | |
3c62338c | 890 | struct fence *flushed_updates; |
97b2e202 AD |
891 | }; |
892 | ||
893 | struct amdgpu_vm { | |
97b2e202 AD |
894 | struct rb_root va; |
895 | ||
7fc11959 | 896 | /* protecting invalidated */ |
97b2e202 AD |
897 | spinlock_t status_lock; |
898 | ||
899 | /* BOs moved, but not yet updated in the PT */ | |
900 | struct list_head invalidated; | |
901 | ||
7fc11959 CK |
902 | /* BOs cleared in the PT because of a move */ |
903 | struct list_head cleared; | |
904 | ||
905 | /* BO mappings freed, but not yet updated in the PT */ | |
97b2e202 AD |
906 | struct list_head freed; |
907 | ||
908 | /* contains the page directory */ | |
909 | struct amdgpu_bo *page_directory; | |
910 | unsigned max_pde_used; | |
05906dec | 911 | struct fence *page_directory_fence; |
97b2e202 AD |
912 | |
913 | /* array of page tables, one for each page directory entry */ | |
914 | struct amdgpu_vm_pt *page_tables; | |
915 | ||
916 | /* for id and flush management per ring */ | |
917 | struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; | |
c25867df CZ |
918 | /* for interval tree */ |
919 | spinlock_t it_lock; | |
81d75a30 | 920 | /* protecting freed */ |
921 | spinlock_t freed_lock; | |
97b2e202 AD |
922 | }; |
923 | ||
924 | struct amdgpu_vm_manager { | |
1c16c0a7 CK |
925 | struct { |
926 | struct fence *active; | |
927 | atomic_long_t owner; | |
928 | } ids[AMDGPU_NUM_VM]; | |
929 | ||
8b4fb00b | 930 | uint32_t max_pfn; |
97b2e202 | 931 | /* number of VMIDs */ |
8b4fb00b | 932 | unsigned nvm; |
97b2e202 | 933 | /* vram base address for page table entry */ |
8b4fb00b | 934 | u64 vram_base_offset; |
97b2e202 | 935 | /* is vm enabled? */ |
8b4fb00b | 936 | bool enabled; |
97b2e202 AD |
937 | /* vm pte handling */ |
938 | const struct amdgpu_vm_pte_funcs *vm_pte_funcs; | |
939 | struct amdgpu_ring *vm_pte_funcs_ring; | |
940 | }; | |
941 | ||
ea89f8c9 | 942 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev); |
8b4fb00b CK |
943 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
944 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); | |
56467ebf CK |
945 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
946 | struct list_head *validated, | |
947 | struct amdgpu_bo_list_entry *entry); | |
ee1782c3 | 948 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); |
eceb8a15 CK |
949 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, |
950 | struct amdgpu_vm *vm); | |
8b4fb00b CK |
951 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
952 | struct amdgpu_sync *sync); | |
953 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
954 | struct amdgpu_vm *vm, | |
955 | struct fence *updates); | |
956 | void amdgpu_vm_fence(struct amdgpu_device *adev, | |
957 | struct amdgpu_vm *vm, | |
958 | struct fence *fence); | |
959 | uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); | |
960 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
961 | struct amdgpu_vm *vm); | |
962 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
963 | struct amdgpu_vm *vm); | |
964 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
965 | struct amdgpu_sync *sync); | |
966 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
967 | struct amdgpu_bo_va *bo_va, | |
968 | struct ttm_mem_reg *mem); | |
969 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
970 | struct amdgpu_bo *bo); | |
971 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
972 | struct amdgpu_bo *bo); | |
973 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
974 | struct amdgpu_vm *vm, | |
975 | struct amdgpu_bo *bo); | |
976 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
977 | struct amdgpu_bo_va *bo_va, | |
978 | uint64_t addr, uint64_t offset, | |
979 | uint64_t size, uint32_t flags); | |
980 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
981 | struct amdgpu_bo_va *bo_va, | |
982 | uint64_t addr); | |
983 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
984 | struct amdgpu_bo_va *bo_va); | |
985 | int amdgpu_vm_free_job(struct amdgpu_job *job); | |
986 | ||
97b2e202 AD |
987 | /* |
988 | * context related structures | |
989 | */ | |
990 | ||
21c16bf6 | 991 | struct amdgpu_ctx_ring { |
91404fb2 | 992 | uint64_t sequence; |
37cd0ca2 | 993 | struct fence **fences; |
91404fb2 | 994 | struct amd_sched_entity entity; |
21c16bf6 CK |
995 | }; |
996 | ||
97b2e202 | 997 | struct amdgpu_ctx { |
0b492a4c | 998 | struct kref refcount; |
9cb7e5a9 | 999 | struct amdgpu_device *adev; |
0b492a4c | 1000 | unsigned reset_counter; |
21c16bf6 | 1001 | spinlock_t ring_lock; |
37cd0ca2 | 1002 | struct fence **fences; |
21c16bf6 | 1003 | struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; |
97b2e202 AD |
1004 | }; |
1005 | ||
1006 | struct amdgpu_ctx_mgr { | |
0b492a4c AD |
1007 | struct amdgpu_device *adev; |
1008 | struct mutex lock; | |
1009 | /* protected by lock */ | |
1010 | struct idr ctx_handles; | |
97b2e202 AD |
1011 | }; |
1012 | ||
d033a6de | 1013 | int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri, |
47f38501 CK |
1014 | struct amdgpu_ctx *ctx); |
1015 | void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); | |
0b492a4c | 1016 | |
0b492a4c AD |
1017 | struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); |
1018 | int amdgpu_ctx_put(struct amdgpu_ctx *ctx); | |
1019 | ||
21c16bf6 | 1020 | uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, |
ce882e6d | 1021 | struct fence *fence); |
21c16bf6 CK |
1022 | struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, |
1023 | struct amdgpu_ring *ring, uint64_t seq); | |
1024 | ||
0b492a4c AD |
1025 | int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, |
1026 | struct drm_file *filp); | |
1027 | ||
efd4ccb5 CK |
1028 | void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); |
1029 | void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); | |
0b492a4c | 1030 | |
97b2e202 AD |
1031 | /* |
1032 | * file private structure | |
1033 | */ | |
1034 | ||
1035 | struct amdgpu_fpriv { | |
1036 | struct amdgpu_vm vm; | |
1037 | struct mutex bo_list_lock; | |
1038 | struct idr bo_list_handles; | |
0b492a4c | 1039 | struct amdgpu_ctx_mgr ctx_mgr; |
97b2e202 AD |
1040 | }; |
1041 | ||
1042 | /* | |
1043 | * residency list | |
1044 | */ | |
1045 | ||
1046 | struct amdgpu_bo_list { | |
1047 | struct mutex lock; | |
1048 | struct amdgpu_bo *gds_obj; | |
1049 | struct amdgpu_bo *gws_obj; | |
1050 | struct amdgpu_bo *oa_obj; | |
1051 | bool has_userptr; | |
1052 | unsigned num_entries; | |
1053 | struct amdgpu_bo_list_entry *array; | |
1054 | }; | |
1055 | ||
1056 | struct amdgpu_bo_list * | |
1057 | amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); | |
1058 | void amdgpu_bo_list_put(struct amdgpu_bo_list *list); | |
1059 | void amdgpu_bo_list_free(struct amdgpu_bo_list *list); | |
1060 | ||
1061 | /* | |
1062 | * GFX stuff | |
1063 | */ | |
1064 | #include "clearstate_defs.h" | |
1065 | ||
1066 | struct amdgpu_rlc { | |
1067 | /* for power gating */ | |
1068 | struct amdgpu_bo *save_restore_obj; | |
1069 | uint64_t save_restore_gpu_addr; | |
1070 | volatile uint32_t *sr_ptr; | |
1071 | const u32 *reg_list; | |
1072 | u32 reg_list_size; | |
1073 | /* for clear state */ | |
1074 | struct amdgpu_bo *clear_state_obj; | |
1075 | uint64_t clear_state_gpu_addr; | |
1076 | volatile uint32_t *cs_ptr; | |
1077 | const struct cs_section_def *cs_data; | |
1078 | u32 clear_state_size; | |
1079 | /* for cp tables */ | |
1080 | struct amdgpu_bo *cp_table_obj; | |
1081 | uint64_t cp_table_gpu_addr; | |
1082 | volatile uint32_t *cp_table_ptr; | |
1083 | u32 cp_table_size; | |
1084 | }; | |
1085 | ||
1086 | struct amdgpu_mec { | |
1087 | struct amdgpu_bo *hpd_eop_obj; | |
1088 | u64 hpd_eop_gpu_addr; | |
1089 | u32 num_pipe; | |
1090 | u32 num_mec; | |
1091 | u32 num_queue; | |
1092 | }; | |
1093 | ||
1094 | /* | |
1095 | * GPU scratch registers structures, functions & helpers | |
1096 | */ | |
1097 | struct amdgpu_scratch { | |
1098 | unsigned num_reg; | |
1099 | uint32_t reg_base; | |
1100 | bool free[32]; | |
1101 | uint32_t reg[32]; | |
1102 | }; | |
1103 | ||
1104 | /* | |
1105 | * GFX configurations | |
1106 | */ | |
1107 | struct amdgpu_gca_config { | |
1108 | unsigned max_shader_engines; | |
1109 | unsigned max_tile_pipes; | |
1110 | unsigned max_cu_per_sh; | |
1111 | unsigned max_sh_per_se; | |
1112 | unsigned max_backends_per_se; | |
1113 | unsigned max_texture_channel_caches; | |
1114 | unsigned max_gprs; | |
1115 | unsigned max_gs_threads; | |
1116 | unsigned max_hw_contexts; | |
1117 | unsigned sc_prim_fifo_size_frontend; | |
1118 | unsigned sc_prim_fifo_size_backend; | |
1119 | unsigned sc_hiz_tile_fifo_size; | |
1120 | unsigned sc_earlyz_tile_fifo_size; | |
1121 | ||
1122 | unsigned num_tile_pipes; | |
1123 | unsigned backend_enable_mask; | |
1124 | unsigned mem_max_burst_length_bytes; | |
1125 | unsigned mem_row_size_in_kb; | |
1126 | unsigned shader_engine_tile_size; | |
1127 | unsigned num_gpus; | |
1128 | unsigned multi_gpu_tile_size; | |
1129 | unsigned mc_arb_ramcfg; | |
1130 | unsigned gb_addr_config; | |
1131 | ||
1132 | uint32_t tile_mode_array[32]; | |
1133 | uint32_t macrotile_mode_array[16]; | |
1134 | }; | |
1135 | ||
1136 | struct amdgpu_gfx { | |
1137 | struct mutex gpu_clock_mutex; | |
1138 | struct amdgpu_gca_config config; | |
1139 | struct amdgpu_rlc rlc; | |
1140 | struct amdgpu_mec mec; | |
1141 | struct amdgpu_scratch scratch; | |
1142 | const struct firmware *me_fw; /* ME firmware */ | |
1143 | uint32_t me_fw_version; | |
1144 | const struct firmware *pfp_fw; /* PFP firmware */ | |
1145 | uint32_t pfp_fw_version; | |
1146 | const struct firmware *ce_fw; /* CE firmware */ | |
1147 | uint32_t ce_fw_version; | |
1148 | const struct firmware *rlc_fw; /* RLC firmware */ | |
1149 | uint32_t rlc_fw_version; | |
1150 | const struct firmware *mec_fw; /* MEC firmware */ | |
1151 | uint32_t mec_fw_version; | |
1152 | const struct firmware *mec2_fw; /* MEC2 firmware */ | |
1153 | uint32_t mec2_fw_version; | |
02558a00 KW |
1154 | uint32_t me_feature_version; |
1155 | uint32_t ce_feature_version; | |
1156 | uint32_t pfp_feature_version; | |
351643d7 JZ |
1157 | uint32_t rlc_feature_version; |
1158 | uint32_t mec_feature_version; | |
1159 | uint32_t mec2_feature_version; | |
97b2e202 AD |
1160 | struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; |
1161 | unsigned num_gfx_rings; | |
1162 | struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; | |
1163 | unsigned num_compute_rings; | |
1164 | struct amdgpu_irq_src eop_irq; | |
1165 | struct amdgpu_irq_src priv_reg_irq; | |
1166 | struct amdgpu_irq_src priv_inst_irq; | |
1167 | /* gfx status */ | |
1168 | uint32_t gfx_current_status; | |
a101a899 KW |
1169 | /* ce ram size*/ |
1170 | unsigned ce_ram_size; | |
97b2e202 AD |
1171 | }; |
1172 | ||
1173 | int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, | |
1174 | unsigned size, struct amdgpu_ib *ib); | |
1175 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); | |
1176 | int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, | |
1177 | struct amdgpu_ib *ib, void *owner); | |
1178 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); | |
1179 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); | |
1180 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); | |
1181 | /* Ring access between begin & end cannot sleep */ | |
1182 | void amdgpu_ring_free_size(struct amdgpu_ring *ring); | |
1183 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); | |
1184 | int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); | |
edff0e28 | 1185 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); |
97b2e202 AD |
1186 | void amdgpu_ring_commit(struct amdgpu_ring *ring); |
1187 | void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); | |
1188 | void amdgpu_ring_undo(struct amdgpu_ring *ring); | |
1189 | void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); | |
97b2e202 AD |
1190 | unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, |
1191 | uint32_t **data); | |
1192 | int amdgpu_ring_restore(struct amdgpu_ring *ring, | |
1193 | unsigned size, uint32_t *data); | |
1194 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |
1195 | unsigned ring_size, u32 nop, u32 align_mask, | |
1196 | struct amdgpu_irq_src *irq_src, unsigned irq_type, | |
1197 | enum amdgpu_ring_type ring_type); | |
1198 | void amdgpu_ring_fini(struct amdgpu_ring *ring); | |
8120b61f | 1199 | struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f); |
97b2e202 AD |
1200 | |
1201 | /* | |
1202 | * CS. | |
1203 | */ | |
1204 | struct amdgpu_cs_chunk { | |
1205 | uint32_t chunk_id; | |
1206 | uint32_t length_dw; | |
1207 | uint32_t *kdata; | |
1208 | void __user *user_ptr; | |
1209 | }; | |
1210 | ||
1211 | struct amdgpu_cs_parser { | |
1212 | struct amdgpu_device *adev; | |
1213 | struct drm_file *filp; | |
3cb485f3 | 1214 | struct amdgpu_ctx *ctx; |
97b2e202 AD |
1215 | struct amdgpu_bo_list *bo_list; |
1216 | /* chunks */ | |
1217 | unsigned nchunks; | |
1218 | struct amdgpu_cs_chunk *chunks; | |
1219 | /* relocations */ | |
56467ebf | 1220 | struct amdgpu_bo_list_entry vm_pd; |
97b2e202 | 1221 | struct list_head validated; |
984810fc | 1222 | struct fence *fence; |
97b2e202 AD |
1223 | |
1224 | struct amdgpu_ib *ibs; | |
1225 | uint32_t num_ibs; | |
1226 | ||
1227 | struct ww_acquire_ctx ticket; | |
1228 | ||
1229 | /* user fence */ | |
91acbeb6 CK |
1230 | struct amdgpu_user_fence uf; |
1231 | struct amdgpu_bo_list_entry uf_entry; | |
97b2e202 AD |
1232 | }; |
1233 | ||
bb977d37 CZ |
1234 | struct amdgpu_job { |
1235 | struct amd_sched_job base; | |
1236 | struct amdgpu_device *adev; | |
bb977d37 CZ |
1237 | struct amdgpu_ib *ibs; |
1238 | uint32_t num_ibs; | |
e2840221 | 1239 | void *owner; |
bb977d37 | 1240 | struct amdgpu_user_fence uf; |
4c7eb91c | 1241 | int (*free_job)(struct amdgpu_job *job); |
bb977d37 | 1242 | }; |
a6db8a33 JZ |
1243 | #define to_amdgpu_job(sched_job) \ |
1244 | container_of((sched_job), struct amdgpu_job, base) | |
bb977d37 | 1245 | |
97b2e202 AD |
1246 | static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) |
1247 | { | |
1248 | return p->ibs[ib_idx].ptr[idx]; | |
1249 | } | |
1250 | ||
1251 | /* | |
1252 | * Writeback | |
1253 | */ | |
1254 | #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ | |
1255 | ||
1256 | struct amdgpu_wb { | |
1257 | struct amdgpu_bo *wb_obj; | |
1258 | volatile uint32_t *wb; | |
1259 | uint64_t gpu_addr; | |
1260 | u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ | |
1261 | unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; | |
1262 | }; | |
1263 | ||
1264 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); | |
1265 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); | |
1266 | ||
97b2e202 | 1267 | |
97b2e202 AD |
1268 | |
1269 | enum amdgpu_int_thermal_type { | |
1270 | THERMAL_TYPE_NONE, | |
1271 | THERMAL_TYPE_EXTERNAL, | |
1272 | THERMAL_TYPE_EXTERNAL_GPIO, | |
1273 | THERMAL_TYPE_RV6XX, | |
1274 | THERMAL_TYPE_RV770, | |
1275 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, | |
1276 | THERMAL_TYPE_EVERGREEN, | |
1277 | THERMAL_TYPE_SUMO, | |
1278 | THERMAL_TYPE_NI, | |
1279 | THERMAL_TYPE_SI, | |
1280 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, | |
1281 | THERMAL_TYPE_CI, | |
1282 | THERMAL_TYPE_KV, | |
1283 | }; | |
1284 | ||
1285 | enum amdgpu_dpm_auto_throttle_src { | |
1286 | AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, | |
1287 | AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL | |
1288 | }; | |
1289 | ||
1290 | enum amdgpu_dpm_event_src { | |
1291 | AMDGPU_DPM_EVENT_SRC_ANALOG = 0, | |
1292 | AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, | |
1293 | AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, | |
1294 | AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, | |
1295 | AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 | |
1296 | }; | |
1297 | ||
1298 | #define AMDGPU_MAX_VCE_LEVELS 6 | |
1299 | ||
1300 | enum amdgpu_vce_level { | |
1301 | AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ | |
1302 | AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ | |
1303 | AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ | |
1304 | AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ | |
1305 | AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ | |
1306 | AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ | |
1307 | }; | |
1308 | ||
1309 | struct amdgpu_ps { | |
1310 | u32 caps; /* vbios flags */ | |
1311 | u32 class; /* vbios flags */ | |
1312 | u32 class2; /* vbios flags */ | |
1313 | /* UVD clocks */ | |
1314 | u32 vclk; | |
1315 | u32 dclk; | |
1316 | /* VCE clocks */ | |
1317 | u32 evclk; | |
1318 | u32 ecclk; | |
1319 | bool vce_active; | |
1320 | enum amdgpu_vce_level vce_level; | |
1321 | /* asic priv */ | |
1322 | void *ps_priv; | |
1323 | }; | |
1324 | ||
1325 | struct amdgpu_dpm_thermal { | |
1326 | /* thermal interrupt work */ | |
1327 | struct work_struct work; | |
1328 | /* low temperature threshold */ | |
1329 | int min_temp; | |
1330 | /* high temperature threshold */ | |
1331 | int max_temp; | |
1332 | /* was last interrupt low to high or high to low */ | |
1333 | bool high_to_low; | |
1334 | /* interrupt source */ | |
1335 | struct amdgpu_irq_src irq; | |
1336 | }; | |
1337 | ||
1338 | enum amdgpu_clk_action | |
1339 | { | |
1340 | AMDGPU_SCLK_UP = 1, | |
1341 | AMDGPU_SCLK_DOWN | |
1342 | }; | |
1343 | ||
1344 | struct amdgpu_blacklist_clocks | |
1345 | { | |
1346 | u32 sclk; | |
1347 | u32 mclk; | |
1348 | enum amdgpu_clk_action action; | |
1349 | }; | |
1350 | ||
1351 | struct amdgpu_clock_and_voltage_limits { | |
1352 | u32 sclk; | |
1353 | u32 mclk; | |
1354 | u16 vddc; | |
1355 | u16 vddci; | |
1356 | }; | |
1357 | ||
1358 | struct amdgpu_clock_array { | |
1359 | u32 count; | |
1360 | u32 *values; | |
1361 | }; | |
1362 | ||
1363 | struct amdgpu_clock_voltage_dependency_entry { | |
1364 | u32 clk; | |
1365 | u16 v; | |
1366 | }; | |
1367 | ||
1368 | struct amdgpu_clock_voltage_dependency_table { | |
1369 | u32 count; | |
1370 | struct amdgpu_clock_voltage_dependency_entry *entries; | |
1371 | }; | |
1372 | ||
1373 | union amdgpu_cac_leakage_entry { | |
1374 | struct { | |
1375 | u16 vddc; | |
1376 | u32 leakage; | |
1377 | }; | |
1378 | struct { | |
1379 | u16 vddc1; | |
1380 | u16 vddc2; | |
1381 | u16 vddc3; | |
1382 | }; | |
1383 | }; | |
1384 | ||
1385 | struct amdgpu_cac_leakage_table { | |
1386 | u32 count; | |
1387 | union amdgpu_cac_leakage_entry *entries; | |
1388 | }; | |
1389 | ||
1390 | struct amdgpu_phase_shedding_limits_entry { | |
1391 | u16 voltage; | |
1392 | u32 sclk; | |
1393 | u32 mclk; | |
1394 | }; | |
1395 | ||
1396 | struct amdgpu_phase_shedding_limits_table { | |
1397 | u32 count; | |
1398 | struct amdgpu_phase_shedding_limits_entry *entries; | |
1399 | }; | |
1400 | ||
1401 | struct amdgpu_uvd_clock_voltage_dependency_entry { | |
1402 | u32 vclk; | |
1403 | u32 dclk; | |
1404 | u16 v; | |
1405 | }; | |
1406 | ||
1407 | struct amdgpu_uvd_clock_voltage_dependency_table { | |
1408 | u8 count; | |
1409 | struct amdgpu_uvd_clock_voltage_dependency_entry *entries; | |
1410 | }; | |
1411 | ||
1412 | struct amdgpu_vce_clock_voltage_dependency_entry { | |
1413 | u32 ecclk; | |
1414 | u32 evclk; | |
1415 | u16 v; | |
1416 | }; | |
1417 | ||
1418 | struct amdgpu_vce_clock_voltage_dependency_table { | |
1419 | u8 count; | |
1420 | struct amdgpu_vce_clock_voltage_dependency_entry *entries; | |
1421 | }; | |
1422 | ||
1423 | struct amdgpu_ppm_table { | |
1424 | u8 ppm_design; | |
1425 | u16 cpu_core_number; | |
1426 | u32 platform_tdp; | |
1427 | u32 small_ac_platform_tdp; | |
1428 | u32 platform_tdc; | |
1429 | u32 small_ac_platform_tdc; | |
1430 | u32 apu_tdp; | |
1431 | u32 dgpu_tdp; | |
1432 | u32 dgpu_ulv_power; | |
1433 | u32 tj_max; | |
1434 | }; | |
1435 | ||
1436 | struct amdgpu_cac_tdp_table { | |
1437 | u16 tdp; | |
1438 | u16 configurable_tdp; | |
1439 | u16 tdc; | |
1440 | u16 battery_power_limit; | |
1441 | u16 small_power_limit; | |
1442 | u16 low_cac_leakage; | |
1443 | u16 high_cac_leakage; | |
1444 | u16 maximum_power_delivery_limit; | |
1445 | }; | |
1446 | ||
1447 | struct amdgpu_dpm_dynamic_state { | |
1448 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; | |
1449 | struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; | |
1450 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; | |
1451 | struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; | |
1452 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; | |
1453 | struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; | |
1454 | struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; | |
1455 | struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; | |
1456 | struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; | |
1457 | struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; | |
1458 | struct amdgpu_clock_array valid_sclk_values; | |
1459 | struct amdgpu_clock_array valid_mclk_values; | |
1460 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; | |
1461 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; | |
1462 | u32 mclk_sclk_ratio; | |
1463 | u32 sclk_mclk_delta; | |
1464 | u16 vddc_vddci_delta; | |
1465 | u16 min_vddc_for_pcie_gen2; | |
1466 | struct amdgpu_cac_leakage_table cac_leakage_table; | |
1467 | struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; | |
1468 | struct amdgpu_ppm_table *ppm_table; | |
1469 | struct amdgpu_cac_tdp_table *cac_tdp_table; | |
1470 | }; | |
1471 | ||
1472 | struct amdgpu_dpm_fan { | |
1473 | u16 t_min; | |
1474 | u16 t_med; | |
1475 | u16 t_high; | |
1476 | u16 pwm_min; | |
1477 | u16 pwm_med; | |
1478 | u16 pwm_high; | |
1479 | u8 t_hyst; | |
1480 | u32 cycle_delay; | |
1481 | u16 t_max; | |
1482 | u8 control_mode; | |
1483 | u16 default_max_fan_pwm; | |
1484 | u16 default_fan_output_sensitivity; | |
1485 | u16 fan_output_sensitivity; | |
1486 | bool ucode_fan_control; | |
1487 | }; | |
1488 | ||
1489 | enum amdgpu_pcie_gen { | |
1490 | AMDGPU_PCIE_GEN1 = 0, | |
1491 | AMDGPU_PCIE_GEN2 = 1, | |
1492 | AMDGPU_PCIE_GEN3 = 2, | |
1493 | AMDGPU_PCIE_GEN_INVALID = 0xffff | |
1494 | }; | |
1495 | ||
1496 | enum amdgpu_dpm_forced_level { | |
1497 | AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, | |
1498 | AMDGPU_DPM_FORCED_LEVEL_LOW = 1, | |
1499 | AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, | |
1500 | }; | |
1501 | ||
1502 | struct amdgpu_vce_state { | |
1503 | /* vce clocks */ | |
1504 | u32 evclk; | |
1505 | u32 ecclk; | |
1506 | /* gpu clocks */ | |
1507 | u32 sclk; | |
1508 | u32 mclk; | |
1509 | u8 clk_idx; | |
1510 | u8 pstate; | |
1511 | }; | |
1512 | ||
1513 | struct amdgpu_dpm_funcs { | |
1514 | int (*get_temperature)(struct amdgpu_device *adev); | |
1515 | int (*pre_set_power_state)(struct amdgpu_device *adev); | |
1516 | int (*set_power_state)(struct amdgpu_device *adev); | |
1517 | void (*post_set_power_state)(struct amdgpu_device *adev); | |
1518 | void (*display_configuration_changed)(struct amdgpu_device *adev); | |
1519 | u32 (*get_sclk)(struct amdgpu_device *adev, bool low); | |
1520 | u32 (*get_mclk)(struct amdgpu_device *adev, bool low); | |
1521 | void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); | |
1522 | void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); | |
1523 | int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); | |
1524 | bool (*vblank_too_short)(struct amdgpu_device *adev); | |
1525 | void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); | |
b7a07769 | 1526 | void (*powergate_vce)(struct amdgpu_device *adev, bool gate); |
97b2e202 AD |
1527 | void (*enable_bapm)(struct amdgpu_device *adev, bool enable); |
1528 | void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); | |
1529 | u32 (*get_fan_control_mode)(struct amdgpu_device *adev); | |
1530 | int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); | |
1531 | int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); | |
1532 | }; | |
1533 | ||
1534 | struct amdgpu_dpm { | |
1535 | struct amdgpu_ps *ps; | |
1536 | /* number of valid power states */ | |
1537 | int num_ps; | |
1538 | /* current power state that is active */ | |
1539 | struct amdgpu_ps *current_ps; | |
1540 | /* requested power state */ | |
1541 | struct amdgpu_ps *requested_ps; | |
1542 | /* boot up power state */ | |
1543 | struct amdgpu_ps *boot_ps; | |
1544 | /* default uvd power state */ | |
1545 | struct amdgpu_ps *uvd_ps; | |
1546 | /* vce requirements */ | |
1547 | struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; | |
1548 | enum amdgpu_vce_level vce_level; | |
3a2c788d RZ |
1549 | enum amd_pm_state_type state; |
1550 | enum amd_pm_state_type user_state; | |
97b2e202 AD |
1551 | u32 platform_caps; |
1552 | u32 voltage_response_time; | |
1553 | u32 backbias_response_time; | |
1554 | void *priv; | |
1555 | u32 new_active_crtcs; | |
1556 | int new_active_crtc_count; | |
1557 | u32 current_active_crtcs; | |
1558 | int current_active_crtc_count; | |
1559 | struct amdgpu_dpm_dynamic_state dyn_state; | |
1560 | struct amdgpu_dpm_fan fan; | |
1561 | u32 tdp_limit; | |
1562 | u32 near_tdp_limit; | |
1563 | u32 near_tdp_limit_adjusted; | |
1564 | u32 sq_ramping_threshold; | |
1565 | u32 cac_leakage; | |
1566 | u16 tdp_od_limit; | |
1567 | u32 tdp_adjustment; | |
1568 | u16 load_line_slope; | |
1569 | bool power_control; | |
1570 | bool ac_power; | |
1571 | /* special states active */ | |
1572 | bool thermal_active; | |
1573 | bool uvd_active; | |
1574 | bool vce_active; | |
1575 | /* thermal handling */ | |
1576 | struct amdgpu_dpm_thermal thermal; | |
1577 | /* forced levels */ | |
1578 | enum amdgpu_dpm_forced_level forced_level; | |
1579 | }; | |
1580 | ||
1581 | struct amdgpu_pm { | |
1582 | struct mutex mutex; | |
97b2e202 AD |
1583 | u32 current_sclk; |
1584 | u32 current_mclk; | |
1585 | u32 default_sclk; | |
1586 | u32 default_mclk; | |
1587 | struct amdgpu_i2c_chan *i2c_bus; | |
1588 | /* internal thermal controller on rv6xx+ */ | |
1589 | enum amdgpu_int_thermal_type int_thermal_type; | |
1590 | struct device *int_hwmon_dev; | |
1591 | /* fan control parameters */ | |
1592 | bool no_fan; | |
1593 | u8 fan_pulses_per_revolution; | |
1594 | u8 fan_min_rpm; | |
1595 | u8 fan_max_rpm; | |
1596 | /* dpm */ | |
1597 | bool dpm_enabled; | |
c86f5ebf | 1598 | bool sysfs_initialized; |
97b2e202 AD |
1599 | struct amdgpu_dpm dpm; |
1600 | const struct firmware *fw; /* SMC firmware */ | |
1601 | uint32_t fw_version; | |
1602 | const struct amdgpu_dpm_funcs *funcs; | |
d0dd7f0c AD |
1603 | uint32_t pcie_gen_mask; |
1604 | uint32_t pcie_mlw_mask; | |
7fb72a1f | 1605 | struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ |
97b2e202 AD |
1606 | }; |
1607 | ||
d0dd7f0c AD |
1608 | void amdgpu_get_pcie_info(struct amdgpu_device *adev); |
1609 | ||
97b2e202 AD |
1610 | /* |
1611 | * UVD | |
1612 | */ | |
1613 | #define AMDGPU_MAX_UVD_HANDLES 10 | |
1614 | #define AMDGPU_UVD_STACK_SIZE (1024*1024) | |
1615 | #define AMDGPU_UVD_HEAP_SIZE (1024*1024) | |
1616 | #define AMDGPU_UVD_FIRMWARE_OFFSET 256 | |
1617 | ||
1618 | struct amdgpu_uvd { | |
1619 | struct amdgpu_bo *vcpu_bo; | |
1620 | void *cpu_addr; | |
1621 | uint64_t gpu_addr; | |
97b2e202 AD |
1622 | atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; |
1623 | struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; | |
1624 | struct delayed_work idle_work; | |
1625 | const struct firmware *fw; /* UVD firmware */ | |
1626 | struct amdgpu_ring ring; | |
1627 | struct amdgpu_irq_src irq; | |
1628 | bool address_64_bit; | |
1629 | }; | |
1630 | ||
1631 | /* | |
1632 | * VCE | |
1633 | */ | |
1634 | #define AMDGPU_MAX_VCE_HANDLES 16 | |
97b2e202 AD |
1635 | #define AMDGPU_VCE_FIRMWARE_OFFSET 256 |
1636 | ||
6a585777 AD |
1637 | #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) |
1638 | #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) | |
1639 | ||
97b2e202 AD |
1640 | struct amdgpu_vce { |
1641 | struct amdgpu_bo *vcpu_bo; | |
1642 | uint64_t gpu_addr; | |
1643 | unsigned fw_version; | |
1644 | unsigned fb_version; | |
1645 | atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; | |
1646 | struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; | |
f1689ec1 | 1647 | uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; |
97b2e202 AD |
1648 | struct delayed_work idle_work; |
1649 | const struct firmware *fw; /* VCE firmware */ | |
1650 | struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; | |
1651 | struct amdgpu_irq_src irq; | |
6a585777 | 1652 | unsigned harvest_config; |
97b2e202 AD |
1653 | }; |
1654 | ||
1655 | /* | |
1656 | * SDMA | |
1657 | */ | |
c113ea1c | 1658 | struct amdgpu_sdma_instance { |
97b2e202 AD |
1659 | /* SDMA firmware */ |
1660 | const struct firmware *fw; | |
1661 | uint32_t fw_version; | |
cfa2104f | 1662 | uint32_t feature_version; |
97b2e202 AD |
1663 | |
1664 | struct amdgpu_ring ring; | |
18111de0 | 1665 | bool burst_nop; |
97b2e202 AD |
1666 | }; |
1667 | ||
c113ea1c AD |
1668 | struct amdgpu_sdma { |
1669 | struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; | |
1670 | struct amdgpu_irq_src trap_irq; | |
1671 | struct amdgpu_irq_src illegal_inst_irq; | |
1672 | int num_instances; | |
1673 | }; | |
1674 | ||
97b2e202 AD |
1675 | /* |
1676 | * Firmware | |
1677 | */ | |
1678 | struct amdgpu_firmware { | |
1679 | struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; | |
1680 | bool smu_load; | |
1681 | struct amdgpu_bo *fw_buf; | |
1682 | unsigned int fw_size; | |
1683 | }; | |
1684 | ||
1685 | /* | |
1686 | * Benchmarking | |
1687 | */ | |
1688 | void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); | |
1689 | ||
1690 | ||
1691 | /* | |
1692 | * Testing | |
1693 | */ | |
1694 | void amdgpu_test_moves(struct amdgpu_device *adev); | |
1695 | void amdgpu_test_ring_sync(struct amdgpu_device *adev, | |
1696 | struct amdgpu_ring *cpA, | |
1697 | struct amdgpu_ring *cpB); | |
1698 | void amdgpu_test_syncing(struct amdgpu_device *adev); | |
1699 | ||
1700 | /* | |
1701 | * MMU Notifier | |
1702 | */ | |
1703 | #if defined(CONFIG_MMU_NOTIFIER) | |
1704 | int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); | |
1705 | void amdgpu_mn_unregister(struct amdgpu_bo *bo); | |
1706 | #else | |
1d1106b0 | 1707 | static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) |
97b2e202 AD |
1708 | { |
1709 | return -ENODEV; | |
1710 | } | |
1d1106b0 | 1711 | static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} |
97b2e202 AD |
1712 | #endif |
1713 | ||
1714 | /* | |
1715 | * Debugfs | |
1716 | */ | |
1717 | struct amdgpu_debugfs { | |
1718 | struct drm_info_list *files; | |
1719 | unsigned num_files; | |
1720 | }; | |
1721 | ||
1722 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
1723 | struct drm_info_list *files, | |
1724 | unsigned nfiles); | |
1725 | int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); | |
1726 | ||
1727 | #if defined(CONFIG_DEBUG_FS) | |
1728 | int amdgpu_debugfs_init(struct drm_minor *minor); | |
1729 | void amdgpu_debugfs_cleanup(struct drm_minor *minor); | |
1730 | #endif | |
1731 | ||
1732 | /* | |
1733 | * amdgpu smumgr functions | |
1734 | */ | |
1735 | struct amdgpu_smumgr_funcs { | |
1736 | int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); | |
1737 | int (*request_smu_load_fw)(struct amdgpu_device *adev); | |
1738 | int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); | |
1739 | }; | |
1740 | ||
1741 | /* | |
1742 | * amdgpu smumgr | |
1743 | */ | |
1744 | struct amdgpu_smumgr { | |
1745 | struct amdgpu_bo *toc_buf; | |
1746 | struct amdgpu_bo *smu_buf; | |
1747 | /* asic priv smu data */ | |
1748 | void *priv; | |
1749 | spinlock_t smu_lock; | |
1750 | /* smumgr functions */ | |
1751 | const struct amdgpu_smumgr_funcs *smumgr_funcs; | |
1752 | /* ucode loading complete flag */ | |
1753 | uint32_t fw_flags; | |
1754 | }; | |
1755 | ||
1756 | /* | |
1757 | * ASIC specific register table accessible by UMD | |
1758 | */ | |
1759 | struct amdgpu_allowed_register_entry { | |
1760 | uint32_t reg_offset; | |
1761 | bool untouched; | |
1762 | bool grbm_indexed; | |
1763 | }; | |
1764 | ||
1765 | struct amdgpu_cu_info { | |
1766 | uint32_t number; /* total active CU number */ | |
1767 | uint32_t ao_cu_mask; | |
1768 | uint32_t bitmap[4][4]; | |
1769 | }; | |
1770 | ||
1771 | ||
1772 | /* | |
1773 | * ASIC specific functions. | |
1774 | */ | |
1775 | struct amdgpu_asic_funcs { | |
1776 | bool (*read_disabled_bios)(struct amdgpu_device *adev); | |
7946b878 AD |
1777 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, |
1778 | u8 *bios, u32 length_bytes); | |
97b2e202 AD |
1779 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, |
1780 | u32 sh_num, u32 reg_offset, u32 *value); | |
1781 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); | |
1782 | int (*reset)(struct amdgpu_device *adev); | |
1783 | /* wait for mc_idle */ | |
1784 | int (*wait_for_mc_idle)(struct amdgpu_device *adev); | |
1785 | /* get the reference clock */ | |
1786 | u32 (*get_xclk)(struct amdgpu_device *adev); | |
1787 | /* get the gpu clock counter */ | |
1788 | uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); | |
1789 | int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); | |
1790 | /* MM block clocks */ | |
1791 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); | |
1792 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); | |
1793 | }; | |
1794 | ||
1795 | /* | |
1796 | * IOCTL. | |
1797 | */ | |
1798 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
1799 | struct drm_file *filp); | |
1800 | int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, | |
1801 | struct drm_file *filp); | |
1802 | ||
1803 | int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, | |
1804 | struct drm_file *filp); | |
1805 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
1806 | struct drm_file *filp); | |
1807 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1808 | struct drm_file *filp); | |
1809 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1810 | struct drm_file *filp); | |
1811 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, | |
1812 | struct drm_file *filp); | |
1813 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
1814 | struct drm_file *filp); | |
1815 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
1816 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
1817 | ||
1818 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
1819 | struct drm_file *filp); | |
1820 | ||
1821 | /* VRAM scratch page for HDP bug, default vram page */ | |
1822 | struct amdgpu_vram_scratch { | |
1823 | struct amdgpu_bo *robj; | |
1824 | volatile uint32_t *ptr; | |
1825 | u64 gpu_addr; | |
1826 | }; | |
1827 | ||
1828 | /* | |
1829 | * ACPI | |
1830 | */ | |
1831 | struct amdgpu_atif_notification_cfg { | |
1832 | bool enabled; | |
1833 | int command_code; | |
1834 | }; | |
1835 | ||
1836 | struct amdgpu_atif_notifications { | |
1837 | bool display_switch; | |
1838 | bool expansion_mode_change; | |
1839 | bool thermal_state; | |
1840 | bool forced_power_state; | |
1841 | bool system_power_state; | |
1842 | bool display_conf_change; | |
1843 | bool px_gfx_switch; | |
1844 | bool brightness_change; | |
1845 | bool dgpu_display_event; | |
1846 | }; | |
1847 | ||
1848 | struct amdgpu_atif_functions { | |
1849 | bool system_params; | |
1850 | bool sbios_requests; | |
1851 | bool select_active_disp; | |
1852 | bool lid_state; | |
1853 | bool get_tv_standard; | |
1854 | bool set_tv_standard; | |
1855 | bool get_panel_expansion_mode; | |
1856 | bool set_panel_expansion_mode; | |
1857 | bool temperature_change; | |
1858 | bool graphics_device_types; | |
1859 | }; | |
1860 | ||
1861 | struct amdgpu_atif { | |
1862 | struct amdgpu_atif_notifications notifications; | |
1863 | struct amdgpu_atif_functions functions; | |
1864 | struct amdgpu_atif_notification_cfg notification_cfg; | |
1865 | struct amdgpu_encoder *encoder_for_bl; | |
1866 | }; | |
1867 | ||
1868 | struct amdgpu_atcs_functions { | |
1869 | bool get_ext_state; | |
1870 | bool pcie_perf_req; | |
1871 | bool pcie_dev_rdy; | |
1872 | bool pcie_bus_width; | |
1873 | }; | |
1874 | ||
1875 | struct amdgpu_atcs { | |
1876 | struct amdgpu_atcs_functions functions; | |
1877 | }; | |
1878 | ||
d03846af CZ |
1879 | /* |
1880 | * CGS | |
1881 | */ | |
1882 | void *amdgpu_cgs_create_device(struct amdgpu_device *adev); | |
1883 | void amdgpu_cgs_destroy_device(void *cgs_device); | |
1884 | ||
1885 | ||
97b2e202 AD |
1886 | /* |
1887 | * Core structure, functions and helpers. | |
1888 | */ | |
1889 | typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); | |
1890 | typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1891 | ||
1892 | typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1893 | typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); | |
1894 | ||
8faf0e08 AD |
1895 | struct amdgpu_ip_block_status { |
1896 | bool valid; | |
1897 | bool sw; | |
1898 | bool hw; | |
1899 | }; | |
1900 | ||
97b2e202 AD |
1901 | struct amdgpu_device { |
1902 | struct device *dev; | |
1903 | struct drm_device *ddev; | |
1904 | struct pci_dev *pdev; | |
97b2e202 AD |
1905 | |
1906 | /* ASIC */ | |
2f7d10b3 | 1907 | enum amd_asic_type asic_type; |
97b2e202 AD |
1908 | uint32_t family; |
1909 | uint32_t rev_id; | |
1910 | uint32_t external_rev_id; | |
1911 | unsigned long flags; | |
1912 | int usec_timeout; | |
1913 | const struct amdgpu_asic_funcs *asic_funcs; | |
1914 | bool shutdown; | |
1915 | bool suspend; | |
1916 | bool need_dma32; | |
1917 | bool accel_working; | |
97b2e202 AD |
1918 | struct work_struct reset_work; |
1919 | struct notifier_block acpi_nb; | |
1920 | struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; | |
1921 | struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; | |
1922 | unsigned debugfs_count; | |
1923 | #if defined(CONFIG_DEBUG_FS) | |
1924 | struct dentry *debugfs_regs; | |
1925 | #endif | |
1926 | struct amdgpu_atif atif; | |
1927 | struct amdgpu_atcs atcs; | |
1928 | struct mutex srbm_mutex; | |
1929 | /* GRBM index mutex. Protects concurrent access to GRBM index */ | |
1930 | struct mutex grbm_idx_mutex; | |
1931 | struct dev_pm_domain vga_pm_domain; | |
1932 | bool have_disp_power_ref; | |
1933 | ||
1934 | /* BIOS */ | |
1935 | uint8_t *bios; | |
1936 | bool is_atom_bios; | |
1937 | uint16_t bios_header_start; | |
1938 | struct amdgpu_bo *stollen_vga_memory; | |
1939 | uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; | |
1940 | ||
1941 | /* Register/doorbell mmio */ | |
1942 | resource_size_t rmmio_base; | |
1943 | resource_size_t rmmio_size; | |
1944 | void __iomem *rmmio; | |
1945 | /* protects concurrent MM_INDEX/DATA based register access */ | |
1946 | spinlock_t mmio_idx_lock; | |
1947 | /* protects concurrent SMC based register access */ | |
1948 | spinlock_t smc_idx_lock; | |
1949 | amdgpu_rreg_t smc_rreg; | |
1950 | amdgpu_wreg_t smc_wreg; | |
1951 | /* protects concurrent PCIE register access */ | |
1952 | spinlock_t pcie_idx_lock; | |
1953 | amdgpu_rreg_t pcie_rreg; | |
1954 | amdgpu_wreg_t pcie_wreg; | |
1955 | /* protects concurrent UVD register access */ | |
1956 | spinlock_t uvd_ctx_idx_lock; | |
1957 | amdgpu_rreg_t uvd_ctx_rreg; | |
1958 | amdgpu_wreg_t uvd_ctx_wreg; | |
1959 | /* protects concurrent DIDT register access */ | |
1960 | spinlock_t didt_idx_lock; | |
1961 | amdgpu_rreg_t didt_rreg; | |
1962 | amdgpu_wreg_t didt_wreg; | |
1963 | /* protects concurrent ENDPOINT (audio) register access */ | |
1964 | spinlock_t audio_endpt_idx_lock; | |
1965 | amdgpu_block_rreg_t audio_endpt_rreg; | |
1966 | amdgpu_block_wreg_t audio_endpt_wreg; | |
1967 | void __iomem *rio_mem; | |
1968 | resource_size_t rio_mem_size; | |
1969 | struct amdgpu_doorbell doorbell; | |
1970 | ||
1971 | /* clock/pll info */ | |
1972 | struct amdgpu_clock clock; | |
1973 | ||
1974 | /* MC */ | |
1975 | struct amdgpu_mc mc; | |
1976 | struct amdgpu_gart gart; | |
1977 | struct amdgpu_dummy_page dummy_page; | |
1978 | struct amdgpu_vm_manager vm_manager; | |
1979 | ||
1980 | /* memory management */ | |
1981 | struct amdgpu_mman mman; | |
1982 | struct amdgpu_gem gem; | |
1983 | struct amdgpu_vram_scratch vram_scratch; | |
1984 | struct amdgpu_wb wb; | |
1985 | atomic64_t vram_usage; | |
1986 | atomic64_t vram_vis_usage; | |
1987 | atomic64_t gtt_usage; | |
1988 | atomic64_t num_bytes_moved; | |
d94aed5a | 1989 | atomic_t gpu_reset_counter; |
97b2e202 AD |
1990 | |
1991 | /* display */ | |
1992 | struct amdgpu_mode_info mode_info; | |
1993 | struct work_struct hotplug_work; | |
1994 | struct amdgpu_irq_src crtc_irq; | |
1995 | struct amdgpu_irq_src pageflip_irq; | |
1996 | struct amdgpu_irq_src hpd_irq; | |
1997 | ||
1998 | /* rings */ | |
97b2e202 AD |
1999 | unsigned fence_context; |
2000 | struct mutex ring_lock; | |
2001 | unsigned num_rings; | |
2002 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; | |
2003 | bool ib_pool_ready; | |
2004 | struct amdgpu_sa_manager ring_tmp_bo; | |
2005 | ||
2006 | /* interrupts */ | |
2007 | struct amdgpu_irq irq; | |
2008 | ||
1f7371b2 AD |
2009 | /* powerplay */ |
2010 | struct amd_powerplay powerplay; | |
e61710c5 | 2011 | bool pp_enabled; |
1f7371b2 | 2012 | |
97b2e202 AD |
2013 | /* dpm */ |
2014 | struct amdgpu_pm pm; | |
2015 | u32 cg_flags; | |
2016 | u32 pg_flags; | |
2017 | ||
2018 | /* amdgpu smumgr */ | |
2019 | struct amdgpu_smumgr smu; | |
2020 | ||
2021 | /* gfx */ | |
2022 | struct amdgpu_gfx gfx; | |
2023 | ||
2024 | /* sdma */ | |
c113ea1c | 2025 | struct amdgpu_sdma sdma; |
97b2e202 AD |
2026 | |
2027 | /* uvd */ | |
2028 | bool has_uvd; | |
2029 | struct amdgpu_uvd uvd; | |
2030 | ||
2031 | /* vce */ | |
2032 | struct amdgpu_vce vce; | |
2033 | ||
2034 | /* firmwares */ | |
2035 | struct amdgpu_firmware firmware; | |
2036 | ||
2037 | /* GDS */ | |
2038 | struct amdgpu_gds gds; | |
2039 | ||
2040 | const struct amdgpu_ip_block_version *ip_blocks; | |
2041 | int num_ip_blocks; | |
8faf0e08 | 2042 | struct amdgpu_ip_block_status *ip_block_status; |
97b2e202 AD |
2043 | struct mutex mn_lock; |
2044 | DECLARE_HASHTABLE(mn_hash, 7); | |
2045 | ||
2046 | /* tracking pinned memory */ | |
2047 | u64 vram_pin_size; | |
2048 | u64 gart_pin_size; | |
130e0371 OG |
2049 | |
2050 | /* amdkfd interface */ | |
2051 | struct kfd_dev *kfd; | |
23ca0e4e CZ |
2052 | |
2053 | /* kernel conext for IB submission */ | |
47f38501 | 2054 | struct amdgpu_ctx kernel_ctx; |
97b2e202 AD |
2055 | }; |
2056 | ||
2057 | bool amdgpu_device_is_px(struct drm_device *dev); | |
2058 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2059 | struct drm_device *ddev, | |
2060 | struct pci_dev *pdev, | |
2061 | uint32_t flags); | |
2062 | void amdgpu_device_fini(struct amdgpu_device *adev); | |
2063 | int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); | |
2064 | ||
2065 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
2066 | bool always_indirect); | |
2067 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
2068 | bool always_indirect); | |
2069 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); | |
2070 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); | |
2071 | ||
2072 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); | |
2073 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); | |
2074 | ||
2075 | /* | |
2076 | * Cast helper | |
2077 | */ | |
2078 | extern const struct fence_ops amdgpu_fence_ops; | |
2079 | static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) | |
2080 | { | |
2081 | struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); | |
2082 | ||
2083 | if (__f->base.ops == &amdgpu_fence_ops) | |
2084 | return __f; | |
2085 | ||
2086 | return NULL; | |
2087 | } | |
2088 | ||
2089 | /* | |
2090 | * Registers read & write functions. | |
2091 | */ | |
2092 | #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) | |
2093 | #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) | |
2094 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) | |
2095 | #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) | |
2096 | #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) | |
2097 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
2098 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
2099 | #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) | |
2100 | #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) | |
2101 | #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) | |
2102 | #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) | |
2103 | #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) | |
2104 | #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) | |
2105 | #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) | |
2106 | #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) | |
2107 | #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) | |
2108 | #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) | |
2109 | #define WREG32_P(reg, val, mask) \ | |
2110 | do { \ | |
2111 | uint32_t tmp_ = RREG32(reg); \ | |
2112 | tmp_ &= (mask); \ | |
2113 | tmp_ |= ((val) & ~(mask)); \ | |
2114 | WREG32(reg, tmp_); \ | |
2115 | } while (0) | |
2116 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) | |
2117 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) | |
2118 | #define WREG32_PLL_P(reg, val, mask) \ | |
2119 | do { \ | |
2120 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
2121 | tmp_ &= (mask); \ | |
2122 | tmp_ |= ((val) & ~(mask)); \ | |
2123 | WREG32_PLL(reg, tmp_); \ | |
2124 | } while (0) | |
2125 | #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) | |
2126 | #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) | |
2127 | #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) | |
2128 | ||
2129 | #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) | |
2130 | #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) | |
2131 | ||
2132 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT | |
2133 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK | |
2134 | ||
2135 | #define REG_SET_FIELD(orig_val, reg, field, field_val) \ | |
2136 | (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ | |
2137 | (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) | |
2138 | ||
2139 | #define REG_GET_FIELD(value, reg, field) \ | |
2140 | (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) | |
2141 | ||
2142 | /* | |
2143 | * BIOS helpers. | |
2144 | */ | |
2145 | #define RBIOS8(i) (adev->bios[i]) | |
2146 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
2147 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
2148 | ||
2149 | /* | |
2150 | * RING helpers. | |
2151 | */ | |
2152 | static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) | |
2153 | { | |
2154 | if (ring->count_dw <= 0) | |
86c2b790 | 2155 | DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); |
97b2e202 AD |
2156 | ring->ring[ring->wptr++] = v; |
2157 | ring->wptr &= ring->ptr_mask; | |
2158 | ring->count_dw--; | |
2159 | ring->ring_free_dw--; | |
2160 | } | |
2161 | ||
c113ea1c AD |
2162 | static inline struct amdgpu_sdma_instance * |
2163 | amdgpu_get_sdma_instance(struct amdgpu_ring *ring) | |
4b2f7e2c JZ |
2164 | { |
2165 | struct amdgpu_device *adev = ring->adev; | |
2166 | int i; | |
2167 | ||
c113ea1c AD |
2168 | for (i = 0; i < adev->sdma.num_instances; i++) |
2169 | if (&adev->sdma.instance[i].ring == ring) | |
4b2f7e2c JZ |
2170 | break; |
2171 | ||
2172 | if (i < AMDGPU_MAX_SDMA_INSTANCES) | |
c113ea1c | 2173 | return &adev->sdma.instance[i]; |
4b2f7e2c JZ |
2174 | else |
2175 | return NULL; | |
2176 | } | |
2177 | ||
97b2e202 AD |
2178 | /* |
2179 | * ASICs macro. | |
2180 | */ | |
2181 | #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) | |
2182 | #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) | |
2183 | #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) | |
2184 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) | |
2185 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) | |
2186 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) | |
2187 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) | |
2188 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) | |
7946b878 | 2189 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
97b2e202 AD |
2190 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
2191 | #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) | |
2192 | #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) | |
2193 | #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) | |
2194 | #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) | |
2195 | #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) | |
2196 | #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) | |
2197 | #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) | |
2198 | #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) | |
2199 | #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) | |
2200 | #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) | |
97b2e202 AD |
2201 | #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) |
2202 | #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) | |
2203 | #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) | |
2204 | #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) | |
2205 | #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) | |
890ee23f | 2206 | #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) |
97b2e202 AD |
2207 | #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) |
2208 | #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) | |
d2edb07b | 2209 | #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) |
97b2e202 AD |
2210 | #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) |
2211 | #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) | |
2212 | #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) | |
2213 | #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) | |
2214 | #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) | |
2215 | #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) | |
2216 | #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) | |
2217 | #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) | |
2218 | #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) | |
2219 | #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) | |
2220 | #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) | |
2221 | #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) | |
2222 | #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) | |
2223 | #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) | |
2224 | #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) | |
2225 | #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) | |
2226 | #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) | |
2227 | #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) | |
2228 | #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) | |
c7ae72c0 | 2229 | #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) |
6e7a3840 | 2230 | #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) |
97b2e202 AD |
2231 | #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) |
2232 | #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) | |
2233 | #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) | |
2234 | #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) | |
97b2e202 | 2235 | #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) |
97b2e202 | 2236 | #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) |
97b2e202 | 2237 | #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) |
3af76f23 RZ |
2238 | |
2239 | #define amdgpu_dpm_get_temperature(adev) \ | |
4b5ece24 | 2240 | ((adev)->pp_enabled ? \ |
e61710c5 | 2241 | (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ |
4b5ece24 | 2242 | (adev)->pm.funcs->get_temperature((adev))) |
3af76f23 RZ |
2243 | |
2244 | #define amdgpu_dpm_set_fan_control_mode(adev, m) \ | |
4b5ece24 | 2245 | ((adev)->pp_enabled ? \ |
e61710c5 | 2246 | (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ |
4b5ece24 | 2247 | (adev)->pm.funcs->set_fan_control_mode((adev), (m))) |
3af76f23 RZ |
2248 | |
2249 | #define amdgpu_dpm_get_fan_control_mode(adev) \ | |
4b5ece24 | 2250 | ((adev)->pp_enabled ? \ |
e61710c5 | 2251 | (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ |
4b5ece24 | 2252 | (adev)->pm.funcs->get_fan_control_mode((adev))) |
3af76f23 RZ |
2253 | |
2254 | #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ | |
4b5ece24 | 2255 | ((adev)->pp_enabled ? \ |
e61710c5 | 2256 | (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ |
4b5ece24 | 2257 | (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) |
3af76f23 RZ |
2258 | |
2259 | #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ | |
4b5ece24 | 2260 | ((adev)->pp_enabled ? \ |
e61710c5 | 2261 | (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ |
4b5ece24 | 2262 | (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) |
97b2e202 | 2263 | |
1b5708ff | 2264 | #define amdgpu_dpm_get_sclk(adev, l) \ |
4b5ece24 | 2265 | ((adev)->pp_enabled ? \ |
e61710c5 | 2266 | (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ |
4b5ece24 | 2267 | (adev)->pm.funcs->get_sclk((adev), (l))) |
1b5708ff RZ |
2268 | |
2269 | #define amdgpu_dpm_get_mclk(adev, l) \ | |
4b5ece24 | 2270 | ((adev)->pp_enabled ? \ |
e61710c5 | 2271 | (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ |
4b5ece24 | 2272 | (adev)->pm.funcs->get_mclk((adev), (l))) |
1b5708ff RZ |
2273 | |
2274 | ||
2275 | #define amdgpu_dpm_force_performance_level(adev, l) \ | |
4b5ece24 | 2276 | ((adev)->pp_enabled ? \ |
e61710c5 | 2277 | (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ |
4b5ece24 | 2278 | (adev)->pm.funcs->force_performance_level((adev), (l))) |
1b5708ff RZ |
2279 | |
2280 | #define amdgpu_dpm_powergate_uvd(adev, g) \ | |
4b5ece24 | 2281 | ((adev)->pp_enabled ? \ |
e61710c5 | 2282 | (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ |
4b5ece24 | 2283 | (adev)->pm.funcs->powergate_uvd((adev), (g))) |
1b5708ff RZ |
2284 | |
2285 | #define amdgpu_dpm_powergate_vce(adev, g) \ | |
4b5ece24 | 2286 | ((adev)->pp_enabled ? \ |
e61710c5 | 2287 | (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ |
4b5ece24 | 2288 | (adev)->pm.funcs->powergate_vce((adev), (g))) |
1b5708ff RZ |
2289 | |
2290 | #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ | |
4b5ece24 | 2291 | ((adev)->pp_enabled ? \ |
e61710c5 | 2292 | (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ |
4b5ece24 | 2293 | (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) |
1b5708ff RZ |
2294 | |
2295 | #define amdgpu_dpm_get_current_power_state(adev) \ | |
e61710c5 | 2296 | (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) |
1b5708ff RZ |
2297 | |
2298 | #define amdgpu_dpm_get_performance_level(adev) \ | |
e61710c5 | 2299 | (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) |
1b5708ff | 2300 | |
e61710c5 | 2301 | #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ |
1b5708ff | 2302 | (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) |
97b2e202 AD |
2303 | |
2304 | #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) | |
2305 | ||
2306 | /* Common functions */ | |
2307 | int amdgpu_gpu_reset(struct amdgpu_device *adev); | |
2308 | void amdgpu_pci_config_reset(struct amdgpu_device *adev); | |
2309 | bool amdgpu_card_posted(struct amdgpu_device *adev); | |
2310 | void amdgpu_update_display_priority(struct amdgpu_device *adev); | |
2311 | bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); | |
d5fc5e82 | 2312 | |
97b2e202 AD |
2313 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); |
2314 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, | |
2315 | u32 ip_instance, u32 ring, | |
2316 | struct amdgpu_ring **out_ring); | |
2317 | void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); | |
2318 | bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); | |
2319 | int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, | |
2320 | uint32_t flags); | |
2321 | bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); | |
cc1de6e8 CK |
2322 | bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, |
2323 | unsigned long end); | |
97b2e202 AD |
2324 | bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); |
2325 | uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, | |
2326 | struct ttm_mem_reg *mem); | |
2327 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); | |
2328 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); | |
2329 | void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); | |
2330 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
2331 | const u32 *registers, | |
2332 | const u32 array_size); | |
2333 | ||
2334 | bool amdgpu_device_is_px(struct drm_device *dev); | |
2335 | /* atpx handler */ | |
2336 | #if defined(CONFIG_VGA_SWITCHEROO) | |
2337 | void amdgpu_register_atpx_handler(void); | |
2338 | void amdgpu_unregister_atpx_handler(void); | |
2339 | #else | |
2340 | static inline void amdgpu_register_atpx_handler(void) {} | |
2341 | static inline void amdgpu_unregister_atpx_handler(void) {} | |
2342 | #endif | |
2343 | ||
2344 | /* | |
2345 | * KMS | |
2346 | */ | |
2347 | extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; | |
2348 | extern int amdgpu_max_kms_ioctl; | |
2349 | ||
2350 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
2351 | int amdgpu_driver_unload_kms(struct drm_device *dev); | |
2352 | void amdgpu_driver_lastclose_kms(struct drm_device *dev); | |
2353 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
2354 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
2355 | struct drm_file *file_priv); | |
2356 | void amdgpu_driver_preclose_kms(struct drm_device *dev, | |
2357 | struct drm_file *file_priv); | |
2358 | int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); | |
2359 | int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); | |
88e72717 TR |
2360 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); |
2361 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
2362 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
2363 | int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, | |
97b2e202 AD |
2364 | int *max_error, |
2365 | struct timeval *vblank_time, | |
2366 | unsigned flags); | |
2367 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, | |
2368 | unsigned long arg); | |
2369 | ||
97b2e202 AD |
2370 | /* |
2371 | * functions used by amdgpu_encoder.c | |
2372 | */ | |
2373 | struct amdgpu_afmt_acr { | |
2374 | u32 clock; | |
2375 | ||
2376 | int n_32khz; | |
2377 | int cts_32khz; | |
2378 | ||
2379 | int n_44_1khz; | |
2380 | int cts_44_1khz; | |
2381 | ||
2382 | int n_48khz; | |
2383 | int cts_48khz; | |
2384 | ||
2385 | }; | |
2386 | ||
2387 | struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); | |
2388 | ||
2389 | /* amdgpu_acpi.c */ | |
2390 | #if defined(CONFIG_ACPI) | |
2391 | int amdgpu_acpi_init(struct amdgpu_device *adev); | |
2392 | void amdgpu_acpi_fini(struct amdgpu_device *adev); | |
2393 | bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); | |
2394 | int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, | |
2395 | u8 perf_req, bool advertise); | |
2396 | int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); | |
2397 | #else | |
2398 | static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } | |
2399 | static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } | |
2400 | #endif | |
2401 | ||
2402 | struct amdgpu_bo_va_mapping * | |
2403 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
2404 | uint64_t addr, struct amdgpu_bo **bo); | |
2405 | ||
2406 | #include "amdgpu_object.h" | |
2407 | ||
2408 | #endif |