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drm/amdgpu: sync to the active user on reusing a VMID
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
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97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
a8fe58ce 56#include "amdgpu_acp.h"
97b2e202 57
b80d8475
AD		 58#include "gpu_scheduler.h"
59
97b2e202
AD		 60/*
61 * Modules parameters.
62 */
63extern int amdgpu_modeset;
64extern int amdgpu_vram_limit;
65extern int amdgpu_gart_size;
66extern int amdgpu_benchmarking;
67extern int amdgpu_testing;
68extern int amdgpu_audio;
69extern int amdgpu_disp_priority;
70extern int amdgpu_hw_i2c;
71extern int amdgpu_pcie_gen2;
72extern int amdgpu_msi;
73extern int amdgpu_lockup_timeout;
74extern int amdgpu_dpm;
75extern int amdgpu_smc_load_fw;
76extern int amdgpu_aspm;
77extern int amdgpu_runtime_pm;
97b2e202
AD		 78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
1333f723 85extern int amdgpu_sched_jobs;
4afcb303 86extern int amdgpu_sched_hw_submission;
1f7371b2 87extern int amdgpu_powerplay;
97b2e202 88
4b559c90 89#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 90#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93#define AMDGPU_IB_POOL_SIZE 16
94#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95#define AMDGPUFB_CONN_LIMIT 4
96#define AMDGPU_BIOS_NUM_SCRATCH 8
97
97b2e202
AD		 98/* max number of rings */
99#define AMDGPU_MAX_RINGS 16
100#define AMDGPU_MAX_GFX_RINGS 1
101#define AMDGPU_MAX_COMPUTE_RINGS 8
102#define AMDGPU_MAX_VCE_RINGS 2
103
36f523a7
JZ		 104/* max number of IP instances */
105#define AMDGPU_MAX_SDMA_INSTANCES 2
106
97b2e202
AD		 107/* hardcode that limit for now */
108#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
109
110/* hard reset data */
111#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
112
113/* reset flags */
114#define AMDGPU_RESET_GFX (1 << 0)
115#define AMDGPU_RESET_COMPUTE (1 << 1)
116#define AMDGPU_RESET_DMA (1 << 2)
117#define AMDGPU_RESET_CP (1 << 3)
118#define AMDGPU_RESET_GRBM (1 << 4)
119#define AMDGPU_RESET_DMA1 (1 << 5)
120#define AMDGPU_RESET_RLC (1 << 6)
121#define AMDGPU_RESET_SEM (1 << 7)
122#define AMDGPU_RESET_IH (1 << 8)
123#define AMDGPU_RESET_VMC (1 << 9)
124#define AMDGPU_RESET_MC (1 << 10)
125#define AMDGPU_RESET_DISPLAY (1 << 11)
126#define AMDGPU_RESET_UVD (1 << 12)
127#define AMDGPU_RESET_VCE (1 << 13)
128#define AMDGPU_RESET_VCE1 (1 << 14)
129
130/* CG block flags */
131#define AMDGPU_CG_BLOCK_GFX (1 << 0)
132#define AMDGPU_CG_BLOCK_MC (1 << 1)
133#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
134#define AMDGPU_CG_BLOCK_UVD (1 << 3)
135#define AMDGPU_CG_BLOCK_VCE (1 << 4)
136#define AMDGPU_CG_BLOCK_HDP (1 << 5)
137#define AMDGPU_CG_BLOCK_BIF (1 << 6)
138
139/* CG flags */
140#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
141#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
142#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
143#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
144#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
145#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
146#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
147#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
148#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
149#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
150#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
151#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
152#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
153#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
154#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
155#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
156#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
157
158/* PG flags */
159#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
160#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
161#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
162#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
163#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
164#define AMDGPU_PG_SUPPORT_CP (1 << 5)
165#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
166#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
167#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
168#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
169#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
170
171/* GFX current status */
172#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
173#define AMDGPU_GFX_SAFE_MODE 0x00000001L
174#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
175#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
176#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
177
178/* max cursor sizes (in pixels) */
179#define CIK_CURSOR_WIDTH 128
180#define CIK_CURSOR_HEIGHT 128
181
182struct amdgpu_device;
183struct amdgpu_fence;
184struct amdgpu_ib;
185struct amdgpu_vm;
186struct amdgpu_ring;
97b2e202 187struct amdgpu_cs_parser;
bb977d37 188struct amdgpu_job;
97b2e202 189struct amdgpu_irq_src;
0b492a4c 190struct amdgpu_fpriv;
97b2e202
AD		 191
192enum amdgpu_cp_irq {
193 AMDGPU_CP_IRQ_GFX_EOP = 0,
194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
202
203 AMDGPU_CP_IRQ_LAST
204};
205
206enum amdgpu_sdma_irq {
207 AMDGPU_SDMA_IRQ_TRAP0 = 0,
208 AMDGPU_SDMA_IRQ_TRAP1,
209
210 AMDGPU_SDMA_IRQ_LAST
211};
212
213enum amdgpu_thermal_irq {
214 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
215 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
216
217 AMDGPU_THERMAL_IRQ_LAST
218};
219
97b2e202 220int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 221 enum amd_ip_block_type block_type,
222 enum amd_clockgating_state state);
97b2e202 223int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 224 enum amd_ip_block_type block_type,
225 enum amd_powergating_state state);
97b2e202
AD		 226
227struct amdgpu_ip_block_version {
5fc3aeeb 228 enum amd_ip_block_type type;
97b2e202
AD		 229 u32 major;
230 u32 minor;
231 u32 rev;
5fc3aeeb 232 const struct amd_ip_funcs *funcs;
97b2e202
AD		 233};
234
235int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 236 enum amd_ip_block_type type,
97b2e202
AD		 237 u32 major, u32 minor);
238
239const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
240 struct amdgpu_device *adev,
5fc3aeeb 241 enum amd_ip_block_type type);
97b2e202
AD		 242
243/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
244struct amdgpu_buffer_funcs {
245 /* maximum bytes in a single operation */
246 uint32_t copy_max_bytes;
247
248 /* number of dw to reserve per operation */
249 unsigned copy_num_dw;
250
251 /* used for buffer migration */
c7ae72c0 252 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 253 /* src addr in bytes */
254 uint64_t src_offset,
255 /* dst addr in bytes */
256 uint64_t dst_offset,
257 /* number of byte to transfer */
258 uint32_t byte_count);
259
260 /* maximum bytes in a single operation */
261 uint32_t fill_max_bytes;
262
263 /* number of dw to reserve per operation */
264 unsigned fill_num_dw;
265
266 /* used for buffer clearing */
6e7a3840 267 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 268 /* value to write to memory */
269 uint32_t src_data,
270 /* dst addr in bytes */
271 uint64_t dst_offset,
272 /* number of byte to fill */
273 uint32_t byte_count);
274};
275
276/* provided by hw blocks that can write ptes, e.g., sdma */
277struct amdgpu_vm_pte_funcs {
278 /* copy pte entries from GART */
279 void (*copy_pte)(struct amdgpu_ib *ib,
280 uint64_t pe, uint64_t src,
281 unsigned count);
282 /* write pte one entry at a time with addr mapping */
283 void (*write_pte)(struct amdgpu_ib *ib,
b07c9d2a 284 const dma_addr_t *pages_addr, uint64_t pe,
97b2e202
AD		 285 uint64_t addr, unsigned count,
286 uint32_t incr, uint32_t flags);
287 /* for linear pte/pde updates without addr mapping */
288 void (*set_pte_pde)(struct amdgpu_ib *ib,
289 uint64_t pe,
290 uint64_t addr, unsigned count,
291 uint32_t incr, uint32_t flags);
97b2e202
AD		 292};
293
294/* provided by the gmc block */
295struct amdgpu_gart_funcs {
296 /* flush the vm tlb via mmio */
297 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
298 uint32_t vmid);
299 /* write pte/pde updates using the cpu */
300 int (*set_pte_pde)(struct amdgpu_device *adev,
301 void *cpu_pt_addr, /* cpu addr of page table */
302 uint32_t gpu_page_idx, /* pte/pde to update */
303 uint64_t addr, /* addr to write into pte/pde */
304 uint32_t flags); /* access flags */
305};
306
307/* provided by the ih block */
308struct amdgpu_ih_funcs {
309 /* ring read/write ptr handling, called from interrupt context */
310 u32 (*get_wptr)(struct amdgpu_device *adev);
311 void (*decode_iv)(struct amdgpu_device *adev,
312 struct amdgpu_iv_entry *entry);
313 void (*set_rptr)(struct amdgpu_device *adev);
314};
315
316/* provided by hw blocks that expose a ring buffer for commands */
317struct amdgpu_ring_funcs {
318 /* ring read/write ptr handling */
319 u32 (*get_rptr)(struct amdgpu_ring *ring);
320 u32 (*get_wptr)(struct amdgpu_ring *ring);
321 void (*set_wptr)(struct amdgpu_ring *ring);
322 /* validating and patching of IBs */
323 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
324 /* command emit functions */
325 void (*emit_ib)(struct amdgpu_ring *ring,
326 struct amdgpu_ib *ib);
327 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 328 uint64_t seq, unsigned flags);
97b2e202
AD		 329 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
330 uint64_t pd_addr);
d2edb07b 331 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
11afbde8 332 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
97b2e202
AD		 333 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
334 uint32_t gds_base, uint32_t gds_size,
335 uint32_t gws_base, uint32_t gws_size,
336 uint32_t oa_base, uint32_t oa_size);
337 /* testing functions */
338 int (*test_ring)(struct amdgpu_ring *ring);
339 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 340 /* insert NOP packets */
341 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
9e5d5309
CK		 342 /* pad the indirect buffer to the necessary number of dw */
343 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202
AD		 344};
345
346/*
347 * BIOS.
348 */
349bool amdgpu_get_bios(struct amdgpu_device *adev);
350bool amdgpu_read_bios(struct amdgpu_device *adev);
351
352/*
353 * Dummy page
354 */
355struct amdgpu_dummy_page {
356 struct page *page;
357 dma_addr_t addr;
358};
359int amdgpu_dummy_page_init(struct amdgpu_device *adev);
360void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
361
362
363/*
364 * Clocks
365 */
366
367#define AMDGPU_MAX_PPLL 3
368
369struct amdgpu_clock {
370 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
371 struct amdgpu_pll spll;
372 struct amdgpu_pll mpll;
373 /* 10 Khz units */
374 uint32_t default_mclk;
375 uint32_t default_sclk;
376 uint32_t default_dispclk;
377 uint32_t current_dispclk;
378 uint32_t dp_extclk;
379 uint32_t max_pixel_clock;
380};
381
382/*
383 * Fences.
384 */
385struct amdgpu_fence_driver {
97b2e202
AD		 386 uint64_t gpu_addr;
387 volatile uint32_t *cpu_addr;
388 /* sync_seq is protected by ring emission lock */
5907a0d8 389 uint64_t sync_seq;
97b2e202
AD		 390 atomic64_t last_seq;
391 bool initialized;
97b2e202
AD		 392 struct amdgpu_irq_src *irq_src;
393 unsigned irq_type;
c2776afe 394 struct timer_list fallback_timer;
7f06c236 395 wait_queue_head_t fence_queue;
97b2e202
AD		 396};
397
398/* some special values for the owner field */
399#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
400#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 401
890ee23f
CZ		 402#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
403#define AMDGPU_FENCE_FLAG_INT (1 << 1)
404
97b2e202
AD		 405struct amdgpu_fence {
406 struct fence base;
4cef9267 407
97b2e202
AD		 408 /* RB, DMA, etc. */
409 struct amdgpu_ring *ring;
410 uint64_t seq;
411
412 /* filp or special value for fence creator */
413 void *owner;
414
415 wait_queue_t fence_wake;
416};
417
418struct amdgpu_user_fence {
419 /* write-back bo */
420 struct amdgpu_bo *bo;
421 /* write-back address offset to bo start */
422 uint32_t offset;
423};
424
425int amdgpu_fence_driver_init(struct amdgpu_device *adev);
426void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
427void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
428
4f839a24 429int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 430int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
431 struct amdgpu_irq_src *irq_src,
432 unsigned irq_type);
5ceb54c6
AD		 433void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
434void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 435int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
436 struct amdgpu_fence **fence);
437void amdgpu_fence_process(struct amdgpu_ring *ring);
438int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
439int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
440unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
441
97b2e202
AD		 442/*
443 * TTM.
444 */
445struct amdgpu_mman {
446 struct ttm_bo_global_ref bo_global_ref;
447 struct drm_global_reference mem_global_ref;
448 struct ttm_bo_device bdev;
449 bool mem_global_referenced;
450 bool initialized;
451
452#if defined(CONFIG_DEBUG_FS)
453 struct dentry *vram;
454 struct dentry *gtt;
455#endif
456
457 /* buffer handling */
458 const struct amdgpu_buffer_funcs *buffer_funcs;
459 struct amdgpu_ring *buffer_funcs_ring;
703297c1
CK		 460 /* Scheduler entity for buffer moves */
461 struct amd_sched_entity entity;
97b2e202
AD		 462};
463
464int amdgpu_copy_buffer(struct amdgpu_ring *ring,
465 uint64_t src_offset,
466 uint64_t dst_offset,
467 uint32_t byte_count,
468 struct reservation_object *resv,
c7ae72c0 469 struct fence **fence);
97b2e202
AD		 470int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
471
472struct amdgpu_bo_list_entry {
473 struct amdgpu_bo *robj;
474 struct ttm_validate_buffer tv;
475 struct amdgpu_bo_va *bo_va;
97b2e202
AD		 476 uint32_t priority;
477};
478
479struct amdgpu_bo_va_mapping {
480 struct list_head list;
481 struct interval_tree_node it;
482 uint64_t offset;
483 uint32_t flags;
484};
485
486/* bo virtual addresses in a specific vm */
487struct amdgpu_bo_va {
69b576a1 488 struct mutex mutex;
97b2e202
AD		 489 /* protected by bo being reserved */
490 struct list_head bo_list;
bb1e38a4 491 struct fence *last_pt_update;
97b2e202
AD		 492 unsigned ref_count;
493
7fc11959 494 /* protected by vm mutex and spinlock */
97b2e202
AD		 495 struct list_head vm_status;
496
7fc11959
CK		 497 /* mappings for this bo_va */
498 struct list_head invalids;
499 struct list_head valids;
500
97b2e202
AD		 501 /* constant after initialization */
502 struct amdgpu_vm *vm;
503 struct amdgpu_bo *bo;
504};
505
7e5a547f
CZ		 506#define AMDGPU_GEM_DOMAIN_MAX 0x3
507
97b2e202
AD		 508struct amdgpu_bo {
509 /* Protected by gem.mutex */
510 struct list_head list;
511 /* Protected by tbo.reserved */
1ea863fd
CK		 512 u32 prefered_domains;
513 u32 allowed_domains;
7e5a547f 514 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 515 struct ttm_placement placement;
516 struct ttm_buffer_object tbo;
517 struct ttm_bo_kmap_obj kmap;
518 u64 flags;
519 unsigned pin_count;
520 void *kptr;
521 u64 tiling_flags;
522 u64 metadata_flags;
523 void *metadata;
524 u32 metadata_size;
525 /* list of all virtual address to which this bo
526 * is associated to
527 */
528 struct list_head va;
529 /* Constant after initialization */
530 struct amdgpu_device *adev;
531 struct drm_gem_object gem_base;
82b9c55b 532 struct amdgpu_bo *parent;
97b2e202
AD		 533
534 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 535 struct amdgpu_mn *mn;
536 struct list_head mn_list;
537};
538#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
539
540void amdgpu_gem_object_free(struct drm_gem_object *obj);
541int amdgpu_gem_object_open(struct drm_gem_object *obj,
542 struct drm_file *file_priv);
543void amdgpu_gem_object_close(struct drm_gem_object *obj,
544 struct drm_file *file_priv);
545unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
546struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
547struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
548 struct dma_buf_attachment *attach,
549 struct sg_table *sg);
550struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
551 struct drm_gem_object *gobj,
552 int flags);
553int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
554void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
555struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
556void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
557void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
558int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
559
560/* sub-allocation manager, it has to be protected by another lock.
561 * By conception this is an helper for other part of the driver
562 * like the indirect buffer or semaphore, which both have their
563 * locking.
564 *
565 * Principe is simple, we keep a list of sub allocation in offset
566 * order (first entry has offset == 0, last entry has the highest
567 * offset).
568 *
569 * When allocating new object we first check if there is room at
570 * the end total_size - (last_object_offset + last_object_size) >=
571 * alloc_size. If so we allocate new object there.
572 *
573 * When there is not enough room at the end, we start waiting for
574 * each sub object until we reach object_offset+object_size >=
575 * alloc_size, this object then become the sub object we return.
576 *
577 * Alignment can't be bigger than page size.
578 *
579 * Hole are not considered for allocation to keep things simple.
580 * Assumption is that there won't be hole (all object on same
581 * alignment).
582 */
583struct amdgpu_sa_manager {
584 wait_queue_head_t wq;
585 struct amdgpu_bo *bo;
586 struct list_head *hole;
587 struct list_head flist[AMDGPU_MAX_RINGS];
588 struct list_head olist;
589 unsigned size;
590 uint64_t gpu_addr;
591 void *cpu_ptr;
592 uint32_t domain;
593 uint32_t align;
594};
595
596struct amdgpu_sa_bo;
597
598/* sub-allocation buffer */
599struct amdgpu_sa_bo {
600 struct list_head olist;
601 struct list_head flist;
602 struct amdgpu_sa_manager *manager;
603 unsigned soffset;
604 unsigned eoffset;
4ce9891e 605 struct fence *fence;
97b2e202
AD		 606};
607
608/*
609 * GEM objects.
610 */
418aa0c2 611void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 612int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
613 int alignment, u32 initial_domain,
614 u64 flags, bool kernel,
615 struct drm_gem_object **obj);
616
617int amdgpu_mode_dumb_create(struct drm_file *file_priv,
618 struct drm_device *dev,
619 struct drm_mode_create_dumb *args);
620int amdgpu_mode_dumb_mmap(struct drm_file *filp,
621 struct drm_device *dev,
622 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 623/*
624 * Synchronization
625 */
626struct amdgpu_sync {
f91b3a69 627 DECLARE_HASHTABLE(fences, 4);
3c62338c 628 struct fence *last_vm_update;
97b2e202
AD		 629};
630
631void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 632int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
633 struct fence *f);
97b2e202
AD		 634int amdgpu_sync_resv(struct amdgpu_device *adev,
635 struct amdgpu_sync *sync,
636 struct reservation_object *resv,
637 void *owner);
e61235db 638struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 639int amdgpu_sync_wait(struct amdgpu_sync *sync);
8a8f0b48 640void amdgpu_sync_free(struct amdgpu_sync *sync);
97b2e202
AD		 641
642/*
643 * GART structures, functions & helpers
644 */
645struct amdgpu_mc;
646
647#define AMDGPU_GPU_PAGE_SIZE 4096
648#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
649#define AMDGPU_GPU_PAGE_SHIFT 12
650#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
651
652struct amdgpu_gart {
653 dma_addr_t table_addr;
654 struct amdgpu_bo *robj;
655 void *ptr;
656 unsigned num_gpu_pages;
657 unsigned num_cpu_pages;
658 unsigned table_size;
659 struct page **pages;
660 dma_addr_t *pages_addr;
661 bool ready;
662 const struct amdgpu_gart_funcs *gart_funcs;
663};
664
665int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
666void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
667int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
668void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
669int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
670void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
671int amdgpu_gart_init(struct amdgpu_device *adev);
672void amdgpu_gart_fini(struct amdgpu_device *adev);
673void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
674 int pages);
675int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
676 int pages, struct page **pagelist,
677 dma_addr_t *dma_addr, uint32_t flags);
678
679/*
680 * GPU MC structures, functions & helpers
681 */
682struct amdgpu_mc {
683 resource_size_t aper_size;
684 resource_size_t aper_base;
685 resource_size_t agp_base;
686 /* for some chips with <= 32MB we need to lie
687 * about vram size near mc fb location */
688 u64 mc_vram_size;
689 u64 visible_vram_size;
690 u64 gtt_size;
691 u64 gtt_start;
692 u64 gtt_end;
693 u64 vram_start;
694 u64 vram_end;
695 unsigned vram_width;
696 u64 real_vram_size;
697 int vram_mtrr;
698 u64 gtt_base_align;
699 u64 mc_mask;
700 const struct firmware *fw; /* MC firmware */
701 uint32_t fw_version;
702 struct amdgpu_irq_src vm_fault;
81c59f54 703 uint32_t vram_type;
97b2e202
AD		 704};
705
706/*
707 * GPU doorbell structures, functions & helpers
708 */
709typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
710{
711 AMDGPU_DOORBELL_KIQ = 0x000,
712 AMDGPU_DOORBELL_HIQ = 0x001,
713 AMDGPU_DOORBELL_DIQ = 0x002,
714 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
715 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
716 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
717 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
718 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
719 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
720 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
721 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
722 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
723 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
724 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
725 AMDGPU_DOORBELL_IH = 0x1E8,
726 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
727 AMDGPU_DOORBELL_INVALID = 0xFFFF
728} AMDGPU_DOORBELL_ASSIGNMENT;
729
730struct amdgpu_doorbell {
731 /* doorbell mmio */
732 resource_size_t base;
733 resource_size_t size;
734 u32 __iomem *ptr;
735 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
736};
737
738void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
739 phys_addr_t *aperture_base,
740 size_t *aperture_size,
741 size_t *start_offset);
742
743/*
744 * IRQS.
745 */
746
747struct amdgpu_flip_work {
748 struct work_struct flip_work;
749 struct work_struct unpin_work;
750 struct amdgpu_device *adev;
751 int crtc_id;
752 uint64_t base;
753 struct drm_pending_vblank_event *event;
754 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 755 struct fence *excl;
756 unsigned shared_count;
757 struct fence **shared;
c3874b75 758 struct fence_cb cb;
97b2e202
AD		 759};
760
761
762/*
763 * CP & rings.
764 */
765
766struct amdgpu_ib {
767 struct amdgpu_sa_bo *sa_bo;
768 uint32_t length_dw;
769 uint64_t gpu_addr;
770 uint32_t *ptr;
97b2e202
AD		 771 struct amdgpu_fence *fence;
772 struct amdgpu_user_fence *user;
773 struct amdgpu_vm *vm;
4ff37a83
CK		 774 unsigned vm_id;
775 uint64_t vm_pd_addr;
3cb485f3 776 struct amdgpu_ctx *ctx;
97b2e202
AD		 777 uint32_t gds_base, gds_size;
778 uint32_t gws_base, gws_size;
779 uint32_t oa_base, oa_size;
de807f81 780 uint32_t flags;
5430a3ff
CK		 781 /* resulting sequence number */
782 uint64_t sequence;
97b2e202
AD		 783};
784
785enum amdgpu_ring_type {
786 AMDGPU_RING_TYPE_GFX,
787 AMDGPU_RING_TYPE_COMPUTE,
788 AMDGPU_RING_TYPE_SDMA,
789 AMDGPU_RING_TYPE_UVD,
790 AMDGPU_RING_TYPE_VCE
791};
792
c1b69ed0
CZ		 793extern struct amd_sched_backend_ops amdgpu_sched_ops;
794
50838c8c
CK		 795int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
796 struct amdgpu_job **job);
d71518b5
CK		 797int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
798 struct amdgpu_job **job);
50838c8c 799void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 800int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa
CK		 801 struct amd_sched_entity *entity, void *owner,
802 struct fence **f);
3c704e93 803
97b2e202
AD		 804struct amdgpu_ring {
805 struct amdgpu_device *adev;
806 const struct amdgpu_ring_funcs *funcs;
807 struct amdgpu_fence_driver fence_drv;
4f839a24 808 struct amd_gpu_scheduler sched;
97b2e202 809
176e1ab1 810 spinlock_t fence_lock;
97b2e202
AD		 811 struct amdgpu_bo *ring_obj;
812 volatile uint32_t *ring;
813 unsigned rptr_offs;
814 u64 next_rptr_gpu_addr;
815 volatile u32 *next_rptr_cpu_addr;
816 unsigned wptr;
817 unsigned wptr_old;
818 unsigned ring_size;
c7e6be23 819 unsigned max_dw;
97b2e202 820 int count_dw;
97b2e202
AD		 821 uint64_t gpu_addr;
822 uint32_t align_mask;
823 uint32_t ptr_mask;
824 bool ready;
825 u32 nop;
826 u32 idx;
97b2e202
AD		 827 u32 me;
828 u32 pipe;
829 u32 queue;
830 struct amdgpu_bo *mqd_obj;
831 u32 doorbell_index;
832 bool use_doorbell;
833 unsigned wptr_offs;
834 unsigned next_rptr_offs;
835 unsigned fence_offs;
3cb485f3 836 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 837 enum amdgpu_ring_type type;
838 char name[16];
839};
840
841/*
842 * VM
843 */
844
845/* maximum number of VMIDs */
846#define AMDGPU_NUM_VM 16
847
848/* number of entries in page table */
849#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
850
851/* PTBs (Page Table Blocks) need to be aligned to 32K */
852#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
853#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
854#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
855
856#define AMDGPU_PTE_VALID (1 << 0)
857#define AMDGPU_PTE_SYSTEM (1 << 1)
858#define AMDGPU_PTE_SNOOPED (1 << 2)
859
860/* VI only */
861#define AMDGPU_PTE_EXECUTABLE (1 << 4)
862
863#define AMDGPU_PTE_READABLE (1 << 5)
864#define AMDGPU_PTE_WRITEABLE (1 << 6)
865
866/* PTE (Page Table Entry) fragment field for different page sizes */
867#define AMDGPU_PTE_FRAG_4KB (0 << 7)
868#define AMDGPU_PTE_FRAG_64KB (4 << 7)
869#define AMDGPU_LOG2_PAGES_PER_FRAG 4
870
d9c13156
CK		 871/* How to programm VM fault handling */
872#define AMDGPU_VM_FAULT_STOP_NEVER 0
873#define AMDGPU_VM_FAULT_STOP_FIRST 1
874#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
875
97b2e202 876struct amdgpu_vm_pt {
ee1782c3
CK		 877 struct amdgpu_bo_list_entry entry;
878 uint64_t addr;
97b2e202
AD		 879};
880
881struct amdgpu_vm_id {
4ff37a83
CK		 882 struct amdgpu_vm_manager_id *mgr_id;
883 uint64_t pd_gpu_addr;
97b2e202 884 /* last flushed PD/PT update */
4ff37a83 885 struct fence *flushed_updates;
97b2e202
AD		 886};
887
888struct amdgpu_vm {
25cfc3c2
CK		 889 /* tree of virtual addresses mapped */
890 spinlock_t it_lock;
97b2e202
AD		 891 struct rb_root va;
892
7fc11959 893 /* protecting invalidated */
97b2e202
AD		 894 spinlock_t status_lock;
895
896 /* BOs moved, but not yet updated in the PT */
897 struct list_head invalidated;
898
7fc11959
CK		 899 /* BOs cleared in the PT because of a move */
900 struct list_head cleared;
901
902 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 903 struct list_head freed;
904
905 /* contains the page directory */
906 struct amdgpu_bo *page_directory;
907 unsigned max_pde_used;
05906dec 908 struct fence *page_directory_fence;
97b2e202
AD		 909
910 /* array of page tables, one for each page directory entry */
911 struct amdgpu_vm_pt *page_tables;
912
913 /* for id and flush management per ring */
914 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
25cfc3c2 915
81d75a30 916 /* protecting freed */
917 spinlock_t freed_lock;
2bd9ccfa
CK		 918
919 /* Scheduler entity for page table updates */
920 struct amd_sched_entity entity;
97b2e202
AD		 921};
922
a9a78b32
CK		 923struct amdgpu_vm_manager_id {
924 struct list_head list;
925 struct fence *active;
926 atomic_long_t owner;
927};
928
97b2e202 929struct amdgpu_vm_manager {
a9a78b32 930 /* Handling of VMIDs */
8d0a7cea 931 struct mutex lock;
a9a78b32
CK		 932 unsigned num_ids;
933 struct list_head ids_lru;
934 struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM];
1c16c0a7 935
8b4fb00b 936 uint32_t max_pfn;
97b2e202 937 /* vram base address for page table entry */
8b4fb00b 938 u64 vram_base_offset;
97b2e202 939 /* is vm enabled? */
8b4fb00b 940 bool enabled;
97b2e202
AD		 941 /* vm pte handling */
942 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
2d55e45a
CK		 943 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
944 unsigned vm_pte_num_rings;
945 atomic_t vm_pte_next_ring;
97b2e202
AD		 946};
947
a9a78b32 948void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 949void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 950int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
951void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 952void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
953 struct list_head *validated,
954 struct amdgpu_bo_list_entry *entry);
ee1782c3 955void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 956void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
957 struct amdgpu_vm *vm);
8b4fb00b 958int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
4ff37a83
CK		 959 struct amdgpu_sync *sync, struct fence *fence,
960 unsigned *vm_id, uint64_t *vm_pd_addr);
8b4fb00b 961void amdgpu_vm_flush(struct amdgpu_ring *ring,
4ff37a83
CK		 962 unsigned vmid,
963 uint64_t pd_addr);
b07c9d2a 964uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
8b4fb00b
CK		 965int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
966 struct amdgpu_vm *vm);
967int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
968 struct amdgpu_vm *vm);
969int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
970 struct amdgpu_sync *sync);
971int amdgpu_vm_bo_update(struct amdgpu_device *adev,
972 struct amdgpu_bo_va *bo_va,
973 struct ttm_mem_reg *mem);
974void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
975 struct amdgpu_bo *bo);
976struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
977 struct amdgpu_bo *bo);
978struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
979 struct amdgpu_vm *vm,
980 struct amdgpu_bo *bo);
981int amdgpu_vm_bo_map(struct amdgpu_device *adev,
982 struct amdgpu_bo_va *bo_va,
983 uint64_t addr, uint64_t offset,
984 uint64_t size, uint32_t flags);
985int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
986 struct amdgpu_bo_va *bo_va,
987 uint64_t addr);
988void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
989 struct amdgpu_bo_va *bo_va);
8b4fb00b 990
97b2e202
AD		 991/*
992 * context related structures
993 */
994
21c16bf6 995struct amdgpu_ctx_ring {
91404fb2 996 uint64_t sequence;
37cd0ca2 997 struct fence **fences;
91404fb2 998 struct amd_sched_entity entity;
21c16bf6
CK		 999};
1000
97b2e202 1001struct amdgpu_ctx {
0b492a4c 1002 struct kref refcount;
9cb7e5a9 1003 struct amdgpu_device *adev;
0b492a4c 1004 unsigned reset_counter;
21c16bf6 1005 spinlock_t ring_lock;
37cd0ca2 1006 struct fence **fences;
21c16bf6 1007 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1008};
1009
1010struct amdgpu_ctx_mgr {
0b492a4c
AD		 1011 struct amdgpu_device *adev;
1012 struct mutex lock;
1013 /* protected by lock */
1014 struct idr ctx_handles;
97b2e202
AD		 1015};
1016
0b492a4c
AD		 1017struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1018int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1019
21c16bf6 1020uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1021 struct fence *fence);
21c16bf6
CK		 1022struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1023 struct amdgpu_ring *ring, uint64_t seq);
1024
0b492a4c
AD		 1025int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1026 struct drm_file *filp);
1027
efd4ccb5
CK		 1028void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1029void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1030
97b2e202
AD		 1031/*
1032 * file private structure
1033 */
1034
1035struct amdgpu_fpriv {
1036 struct amdgpu_vm vm;
1037 struct mutex bo_list_lock;
1038 struct idr bo_list_handles;
0b492a4c 1039 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1040};
1041
1042/*
1043 * residency list
1044 */
1045
1046struct amdgpu_bo_list {
1047 struct mutex lock;
1048 struct amdgpu_bo *gds_obj;
1049 struct amdgpu_bo *gws_obj;
1050 struct amdgpu_bo *oa_obj;
1051 bool has_userptr;
1052 unsigned num_entries;
1053 struct amdgpu_bo_list_entry *array;
1054};
1055
1056struct amdgpu_bo_list *
1057amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1058void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1059 struct list_head *validated);
97b2e202
AD		 1060void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1061void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1062
1063/*
1064 * GFX stuff
1065 */
1066#include "clearstate_defs.h"
1067
1068struct amdgpu_rlc {
1069 /* for power gating */
1070 struct amdgpu_bo *save_restore_obj;
1071 uint64_t save_restore_gpu_addr;
1072 volatile uint32_t *sr_ptr;
1073 const u32 *reg_list;
1074 u32 reg_list_size;
1075 /* for clear state */
1076 struct amdgpu_bo *clear_state_obj;
1077 uint64_t clear_state_gpu_addr;
1078 volatile uint32_t *cs_ptr;
1079 const struct cs_section_def *cs_data;
1080 u32 clear_state_size;
1081 /* for cp tables */
1082 struct amdgpu_bo *cp_table_obj;
1083 uint64_t cp_table_gpu_addr;
1084 volatile uint32_t *cp_table_ptr;
1085 u32 cp_table_size;
1086};
1087
1088struct amdgpu_mec {
1089 struct amdgpu_bo *hpd_eop_obj;
1090 u64 hpd_eop_gpu_addr;
1091 u32 num_pipe;
1092 u32 num_mec;
1093 u32 num_queue;
1094};
1095
1096/*
1097 * GPU scratch registers structures, functions & helpers
1098 */
1099struct amdgpu_scratch {
1100 unsigned num_reg;
1101 uint32_t reg_base;
1102 bool free[32];
1103 uint32_t reg[32];
1104};
1105
1106/*
1107 * GFX configurations
1108 */
1109struct amdgpu_gca_config {
1110 unsigned max_shader_engines;
1111 unsigned max_tile_pipes;
1112 unsigned max_cu_per_sh;
1113 unsigned max_sh_per_se;
1114 unsigned max_backends_per_se;
1115 unsigned max_texture_channel_caches;
1116 unsigned max_gprs;
1117 unsigned max_gs_threads;
1118 unsigned max_hw_contexts;
1119 unsigned sc_prim_fifo_size_frontend;
1120 unsigned sc_prim_fifo_size_backend;
1121 unsigned sc_hiz_tile_fifo_size;
1122 unsigned sc_earlyz_tile_fifo_size;
1123
1124 unsigned num_tile_pipes;
1125 unsigned backend_enable_mask;
1126 unsigned mem_max_burst_length_bytes;
1127 unsigned mem_row_size_in_kb;
1128 unsigned shader_engine_tile_size;
1129 unsigned num_gpus;
1130 unsigned multi_gpu_tile_size;
1131 unsigned mc_arb_ramcfg;
1132 unsigned gb_addr_config;
8f8e00c1 1133 unsigned num_rbs;
97b2e202
AD		 1134
1135 uint32_t tile_mode_array[32];
1136 uint32_t macrotile_mode_array[16];
1137};
1138
1139struct amdgpu_gfx {
1140 struct mutex gpu_clock_mutex;
1141 struct amdgpu_gca_config config;
1142 struct amdgpu_rlc rlc;
1143 struct amdgpu_mec mec;
1144 struct amdgpu_scratch scratch;
1145 const struct firmware *me_fw; /* ME firmware */
1146 uint32_t me_fw_version;
1147 const struct firmware *pfp_fw; /* PFP firmware */
1148 uint32_t pfp_fw_version;
1149 const struct firmware *ce_fw; /* CE firmware */
1150 uint32_t ce_fw_version;
1151 const struct firmware *rlc_fw; /* RLC firmware */
1152 uint32_t rlc_fw_version;
1153 const struct firmware *mec_fw; /* MEC firmware */
1154 uint32_t mec_fw_version;
1155 const struct firmware *mec2_fw; /* MEC2 firmware */
1156 uint32_t mec2_fw_version;
02558a00
KW		 1157 uint32_t me_feature_version;
1158 uint32_t ce_feature_version;
1159 uint32_t pfp_feature_version;
351643d7
JZ		 1160 uint32_t rlc_feature_version;
1161 uint32_t mec_feature_version;
1162 uint32_t mec2_feature_version;
97b2e202
AD		 1163 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1164 unsigned num_gfx_rings;
1165 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1166 unsigned num_compute_rings;
1167 struct amdgpu_irq_src eop_irq;
1168 struct amdgpu_irq_src priv_reg_irq;
1169 struct amdgpu_irq_src priv_inst_irq;
1170 /* gfx status */
1171 uint32_t gfx_current_status;
a101a899
KW		 1172 /* ce ram size*/
1173 unsigned ce_ram_size;
97b2e202
AD		 1174};
1175
b07c60c0 1176int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202
AD		 1177 unsigned size, struct amdgpu_ib *ib);
1178void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
b07c60c0 1179int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
ec72b800 1180 struct amdgpu_ib *ib, void *owner,
e86f9cee 1181 struct fence *last_vm_update,
ec72b800 1182 struct fence **f);
97b2e202
AD		 1183int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1184void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1185int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202 1186int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1187void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
9e5d5309 1188void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202 1189void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1190void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1191unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1192 uint32_t **data);
1193int amdgpu_ring_restore(struct amdgpu_ring *ring,
1194 unsigned size, uint32_t *data);
1195int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1196 unsigned ring_size, u32 nop, u32 align_mask,
1197 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1198 enum amdgpu_ring_type ring_type);
1199void amdgpu_ring_fini(struct amdgpu_ring *ring);
8120b61f 1200struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
97b2e202
AD		 1201
1202/*
1203 * CS.
1204 */
1205struct amdgpu_cs_chunk {
1206 uint32_t chunk_id;
1207 uint32_t length_dw;
1208 uint32_t *kdata;
97b2e202
AD		 1209};
1210
1211struct amdgpu_cs_parser {
1212 struct amdgpu_device *adev;
1213 struct drm_file *filp;
3cb485f3 1214 struct amdgpu_ctx *ctx;
c3cca41e 1215
97b2e202
AD		 1216 /* chunks */
1217 unsigned nchunks;
1218 struct amdgpu_cs_chunk *chunks;
97b2e202 1219
50838c8c
CK		 1220 /* scheduler job object */
1221 struct amdgpu_job *job;
97b2e202 1222
c3cca41e
CK		 1223 /* buffer objects */
1224 struct ww_acquire_ctx ticket;
1225 struct amdgpu_bo_list *bo_list;
1226 struct amdgpu_bo_list_entry vm_pd;
1227 struct list_head validated;
1228 struct fence *fence;
1229 uint64_t bytes_moved_threshold;
1230 uint64_t bytes_moved;
97b2e202
AD		 1231
1232 /* user fence */
91acbeb6 1233 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1234};
1235
bb977d37
CZ		 1236struct amdgpu_job {
1237 struct amd_sched_job base;
1238 struct amdgpu_device *adev;
b07c60c0 1239 struct amdgpu_ring *ring;
e86f9cee 1240 struct amdgpu_sync sync;
bb977d37
CZ		 1241 struct amdgpu_ib *ibs;
1242 uint32_t num_ibs;
e2840221 1243 void *owner;
bb977d37 1244 struct amdgpu_user_fence uf;
bb977d37 1245};
a6db8a33
JZ		 1246#define to_amdgpu_job(sched_job) \
1247 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1248
7270f839
CK		 1249static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1250 uint32_t ib_idx, int idx)
97b2e202 1251{
50838c8c 1252 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1253}
1254
7270f839
CK		 1255static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1256 uint32_t ib_idx, int idx,
1257 uint32_t value)
1258{
50838c8c 1259 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1260}
1261
97b2e202
AD		 1262/*
1263 * Writeback
1264 */
1265#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1266
1267struct amdgpu_wb {
1268 struct amdgpu_bo *wb_obj;
1269 volatile uint32_t *wb;
1270 uint64_t gpu_addr;
1271 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1272 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1273};
1274
1275int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1276void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1277
97b2e202 1278
97b2e202
AD		 1279
1280enum amdgpu_int_thermal_type {
1281 THERMAL_TYPE_NONE,
1282 THERMAL_TYPE_EXTERNAL,
1283 THERMAL_TYPE_EXTERNAL_GPIO,
1284 THERMAL_TYPE_RV6XX,
1285 THERMAL_TYPE_RV770,
1286 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1287 THERMAL_TYPE_EVERGREEN,
1288 THERMAL_TYPE_SUMO,
1289 THERMAL_TYPE_NI,
1290 THERMAL_TYPE_SI,
1291 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1292 THERMAL_TYPE_CI,
1293 THERMAL_TYPE_KV,
1294};
1295
1296enum amdgpu_dpm_auto_throttle_src {
1297 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1298 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1299};
1300
1301enum amdgpu_dpm_event_src {
1302 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1303 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1304 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1305 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1306 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1307};
1308
1309#define AMDGPU_MAX_VCE_LEVELS 6
1310
1311enum amdgpu_vce_level {
1312 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1313 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1314 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1315 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1316 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1317 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1318};
1319
1320struct amdgpu_ps {
1321 u32 caps; /* vbios flags */
1322 u32 class; /* vbios flags */
1323 u32 class2; /* vbios flags */
1324 /* UVD clocks */
1325 u32 vclk;
1326 u32 dclk;
1327 /* VCE clocks */
1328 u32 evclk;
1329 u32 ecclk;
1330 bool vce_active;
1331 enum amdgpu_vce_level vce_level;
1332 /* asic priv */
1333 void *ps_priv;
1334};
1335
1336struct amdgpu_dpm_thermal {
1337 /* thermal interrupt work */
1338 struct work_struct work;
1339 /* low temperature threshold */
1340 int min_temp;
1341 /* high temperature threshold */
1342 int max_temp;
1343 /* was last interrupt low to high or high to low */
1344 bool high_to_low;
1345 /* interrupt source */
1346 struct amdgpu_irq_src irq;
1347};
1348
1349enum amdgpu_clk_action
1350{
1351 AMDGPU_SCLK_UP = 1,
1352 AMDGPU_SCLK_DOWN
1353};
1354
1355struct amdgpu_blacklist_clocks
1356{
1357 u32 sclk;
1358 u32 mclk;
1359 enum amdgpu_clk_action action;
1360};
1361
1362struct amdgpu_clock_and_voltage_limits {
1363 u32 sclk;
1364 u32 mclk;
1365 u16 vddc;
1366 u16 vddci;
1367};
1368
1369struct amdgpu_clock_array {
1370 u32 count;
1371 u32 *values;
1372};
1373
1374struct amdgpu_clock_voltage_dependency_entry {
1375 u32 clk;
1376 u16 v;
1377};
1378
1379struct amdgpu_clock_voltage_dependency_table {
1380 u32 count;
1381 struct amdgpu_clock_voltage_dependency_entry *entries;
1382};
1383
1384union amdgpu_cac_leakage_entry {
1385 struct {
1386 u16 vddc;
1387 u32 leakage;
1388 };
1389 struct {
1390 u16 vddc1;
1391 u16 vddc2;
1392 u16 vddc3;
1393 };
1394};
1395
1396struct amdgpu_cac_leakage_table {
1397 u32 count;
1398 union amdgpu_cac_leakage_entry *entries;
1399};
1400
1401struct amdgpu_phase_shedding_limits_entry {
1402 u16 voltage;
1403 u32 sclk;
1404 u32 mclk;
1405};
1406
1407struct amdgpu_phase_shedding_limits_table {
1408 u32 count;
1409 struct amdgpu_phase_shedding_limits_entry *entries;
1410};
1411
1412struct amdgpu_uvd_clock_voltage_dependency_entry {
1413 u32 vclk;
1414 u32 dclk;
1415 u16 v;
1416};
1417
1418struct amdgpu_uvd_clock_voltage_dependency_table {
1419 u8 count;
1420 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1421};
1422
1423struct amdgpu_vce_clock_voltage_dependency_entry {
1424 u32 ecclk;
1425 u32 evclk;
1426 u16 v;
1427};
1428
1429struct amdgpu_vce_clock_voltage_dependency_table {
1430 u8 count;
1431 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1432};
1433
1434struct amdgpu_ppm_table {
1435 u8 ppm_design;
1436 u16 cpu_core_number;
1437 u32 platform_tdp;
1438 u32 small_ac_platform_tdp;
1439 u32 platform_tdc;
1440 u32 small_ac_platform_tdc;
1441 u32 apu_tdp;
1442 u32 dgpu_tdp;
1443 u32 dgpu_ulv_power;
1444 u32 tj_max;
1445};
1446
1447struct amdgpu_cac_tdp_table {
1448 u16 tdp;
1449 u16 configurable_tdp;
1450 u16 tdc;
1451 u16 battery_power_limit;
1452 u16 small_power_limit;
1453 u16 low_cac_leakage;
1454 u16 high_cac_leakage;
1455 u16 maximum_power_delivery_limit;
1456};
1457
1458struct amdgpu_dpm_dynamic_state {
1459 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1460 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1461 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1462 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1463 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1464 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1465 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1466 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1467 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1468 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1469 struct amdgpu_clock_array valid_sclk_values;
1470 struct amdgpu_clock_array valid_mclk_values;
1471 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1472 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1473 u32 mclk_sclk_ratio;
1474 u32 sclk_mclk_delta;
1475 u16 vddc_vddci_delta;
1476 u16 min_vddc_for_pcie_gen2;
1477 struct amdgpu_cac_leakage_table cac_leakage_table;
1478 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1479 struct amdgpu_ppm_table *ppm_table;
1480 struct amdgpu_cac_tdp_table *cac_tdp_table;
1481};
1482
1483struct amdgpu_dpm_fan {
1484 u16 t_min;
1485 u16 t_med;
1486 u16 t_high;
1487 u16 pwm_min;
1488 u16 pwm_med;
1489 u16 pwm_high;
1490 u8 t_hyst;
1491 u32 cycle_delay;
1492 u16 t_max;
1493 u8 control_mode;
1494 u16 default_max_fan_pwm;
1495 u16 default_fan_output_sensitivity;
1496 u16 fan_output_sensitivity;
1497 bool ucode_fan_control;
1498};
1499
1500enum amdgpu_pcie_gen {
1501 AMDGPU_PCIE_GEN1 = 0,
1502 AMDGPU_PCIE_GEN2 = 1,
1503 AMDGPU_PCIE_GEN3 = 2,
1504 AMDGPU_PCIE_GEN_INVALID = 0xffff
1505};
1506
1507enum amdgpu_dpm_forced_level {
1508 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1509 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1510 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1 1511 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
97b2e202
AD		 1512};
1513
1514struct amdgpu_vce_state {
1515 /* vce clocks */
1516 u32 evclk;
1517 u32 ecclk;
1518 /* gpu clocks */
1519 u32 sclk;
1520 u32 mclk;
1521 u8 clk_idx;
1522 u8 pstate;
1523};
1524
1525struct amdgpu_dpm_funcs {
1526 int (*get_temperature)(struct amdgpu_device *adev);
1527 int (*pre_set_power_state)(struct amdgpu_device *adev);
1528 int (*set_power_state)(struct amdgpu_device *adev);
1529 void (*post_set_power_state)(struct amdgpu_device *adev);
1530 void (*display_configuration_changed)(struct amdgpu_device *adev);
1531 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1532 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1533 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1534 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1535 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1536 bool (*vblank_too_short)(struct amdgpu_device *adev);
1537 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1538 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1539 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1540 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1541 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1542 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1543 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1544};
1545
1546struct amdgpu_dpm {
1547 struct amdgpu_ps *ps;
1548 /* number of valid power states */
1549 int num_ps;
1550 /* current power state that is active */
1551 struct amdgpu_ps *current_ps;
1552 /* requested power state */
1553 struct amdgpu_ps *requested_ps;
1554 /* boot up power state */
1555 struct amdgpu_ps *boot_ps;
1556 /* default uvd power state */
1557 struct amdgpu_ps *uvd_ps;
1558 /* vce requirements */
1559 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1560 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1561 enum amd_pm_state_type state;
1562 enum amd_pm_state_type user_state;
97b2e202
AD		 1563 u32 platform_caps;
1564 u32 voltage_response_time;
1565 u32 backbias_response_time;
1566 void *priv;
1567 u32 new_active_crtcs;
1568 int new_active_crtc_count;
1569 u32 current_active_crtcs;
1570 int current_active_crtc_count;
1571 struct amdgpu_dpm_dynamic_state dyn_state;
1572 struct amdgpu_dpm_fan fan;
1573 u32 tdp_limit;
1574 u32 near_tdp_limit;
1575 u32 near_tdp_limit_adjusted;
1576 u32 sq_ramping_threshold;
1577 u32 cac_leakage;
1578 u16 tdp_od_limit;
1579 u32 tdp_adjustment;
1580 u16 load_line_slope;
1581 bool power_control;
1582 bool ac_power;
1583 /* special states active */
1584 bool thermal_active;
1585 bool uvd_active;
1586 bool vce_active;
1587 /* thermal handling */
1588 struct amdgpu_dpm_thermal thermal;
1589 /* forced levels */
1590 enum amdgpu_dpm_forced_level forced_level;
1591};
1592
1593struct amdgpu_pm {
1594 struct mutex mutex;
97b2e202
AD		 1595 u32 current_sclk;
1596 u32 current_mclk;
1597 u32 default_sclk;
1598 u32 default_mclk;
1599 struct amdgpu_i2c_chan *i2c_bus;
1600 /* internal thermal controller on rv6xx+ */
1601 enum amdgpu_int_thermal_type int_thermal_type;
1602 struct device *int_hwmon_dev;
1603 /* fan control parameters */
1604 bool no_fan;
1605 u8 fan_pulses_per_revolution;
1606 u8 fan_min_rpm;
1607 u8 fan_max_rpm;
1608 /* dpm */
1609 bool dpm_enabled;
c86f5ebf 1610 bool sysfs_initialized;
97b2e202
AD		 1611 struct amdgpu_dpm dpm;
1612 const struct firmware *fw; /* SMC firmware */
1613 uint32_t fw_version;
1614 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1615 uint32_t pcie_gen_mask;
1616 uint32_t pcie_mlw_mask;
7fb72a1f 1617 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1618};
1619
d0dd7f0c
AD		 1620void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1621
97b2e202
AD		 1622/*
1623 * UVD
1624 */
1625#define AMDGPU_MAX_UVD_HANDLES 10
1626#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1627#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1628#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1629
1630struct amdgpu_uvd {
1631 struct amdgpu_bo *vcpu_bo;
1632 void *cpu_addr;
1633 uint64_t gpu_addr;
97b2e202
AD		 1634 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1635 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1636 struct delayed_work idle_work;
1637 const struct firmware *fw; /* UVD firmware */
1638 struct amdgpu_ring ring;
1639 struct amdgpu_irq_src irq;
1640 bool address_64_bit;
ead833ec 1641 struct amd_sched_entity entity;
97b2e202
AD		 1642};
1643
1644/*
1645 * VCE
1646 */
1647#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1648#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1649
6a585777
AD		 1650#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1651#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1652
97b2e202
AD		 1653struct amdgpu_vce {
1654 struct amdgpu_bo *vcpu_bo;
1655 uint64_t gpu_addr;
1656 unsigned fw_version;
1657 unsigned fb_version;
1658 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1659 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1660 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1661 struct delayed_work idle_work;
1662 const struct firmware *fw; /* VCE firmware */
1663 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1664 struct amdgpu_irq_src irq;
6a585777 1665 unsigned harvest_config;
c594989c 1666 struct amd_sched_entity entity;
97b2e202
AD		 1667};
1668
1669/*
1670 * SDMA
1671 */
c113ea1c 1672struct amdgpu_sdma_instance {
97b2e202
AD		 1673 /* SDMA firmware */
1674 const struct firmware *fw;
1675 uint32_t fw_version;
cfa2104f 1676 uint32_t feature_version;
97b2e202
AD		 1677
1678 struct amdgpu_ring ring;
18111de0 1679 bool burst_nop;
97b2e202
AD		 1680};
1681
c113ea1c
AD		 1682struct amdgpu_sdma {
1683 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1684 struct amdgpu_irq_src trap_irq;
1685 struct amdgpu_irq_src illegal_inst_irq;
1686 int num_instances;
1687};
1688
97b2e202
AD		 1689/*
1690 * Firmware
1691 */
1692struct amdgpu_firmware {
1693 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1694 bool smu_load;
1695 struct amdgpu_bo *fw_buf;
1696 unsigned int fw_size;
1697};
1698
1699/*
1700 * Benchmarking
1701 */
1702void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1703
1704
1705/*
1706 * Testing
1707 */
1708void amdgpu_test_moves(struct amdgpu_device *adev);
1709void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1710 struct amdgpu_ring *cpA,
1711 struct amdgpu_ring *cpB);
1712void amdgpu_test_syncing(struct amdgpu_device *adev);
1713
1714/*
1715 * MMU Notifier
1716 */
1717#if defined(CONFIG_MMU_NOTIFIER)
1718int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1719void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1720#else
1d1106b0 1721static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1722{
1723 return -ENODEV;
1724}
1d1106b0 1725static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1726#endif
1727
1728/*
1729 * Debugfs
1730 */
1731struct amdgpu_debugfs {
1732 struct drm_info_list *files;
1733 unsigned num_files;
1734};
1735
1736int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1737 struct drm_info_list *files,
1738 unsigned nfiles);
1739int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1740
1741#if defined(CONFIG_DEBUG_FS)
1742int amdgpu_debugfs_init(struct drm_minor *minor);
1743void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1744#endif
1745
1746/*
1747 * amdgpu smumgr functions
1748 */
1749struct amdgpu_smumgr_funcs {
1750 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1751 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1752 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1753};
1754
1755/*
1756 * amdgpu smumgr
1757 */
1758struct amdgpu_smumgr {
1759 struct amdgpu_bo *toc_buf;
1760 struct amdgpu_bo *smu_buf;
1761 /* asic priv smu data */
1762 void *priv;
1763 spinlock_t smu_lock;
1764 /* smumgr functions */
1765 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1766 /* ucode loading complete flag */
1767 uint32_t fw_flags;
1768};
1769
1770/*
1771 * ASIC specific register table accessible by UMD
1772 */
1773struct amdgpu_allowed_register_entry {
1774 uint32_t reg_offset;
1775 bool untouched;
1776 bool grbm_indexed;
1777};
1778
1779struct amdgpu_cu_info {
1780 uint32_t number; /* total active CU number */
1781 uint32_t ao_cu_mask;
1782 uint32_t bitmap[4][4];
1783};
1784
1785
1786/*
1787 * ASIC specific functions.
1788 */
1789struct amdgpu_asic_funcs {
1790 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1791 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1792 u8 *bios, u32 length_bytes);
97b2e202
AD		 1793 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1794 u32 sh_num, u32 reg_offset, u32 *value);
1795 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1796 int (*reset)(struct amdgpu_device *adev);
1797 /* wait for mc_idle */
1798 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1799 /* get the reference clock */
1800 u32 (*get_xclk)(struct amdgpu_device *adev);
1801 /* get the gpu clock counter */
1802 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1803 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1804 /* MM block clocks */
1805 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1806 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1807};
1808
1809/*
1810 * IOCTL.
1811 */
1812int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1813 struct drm_file *filp);
1814int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1815 struct drm_file *filp);
1816
1817int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1818 struct drm_file *filp);
1819int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1820 struct drm_file *filp);
1821int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1822 struct drm_file *filp);
1823int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1824 struct drm_file *filp);
1825int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1826 struct drm_file *filp);
1827int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1828 struct drm_file *filp);
1829int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1830int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1831
1832int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1833 struct drm_file *filp);
1834
1835/* VRAM scratch page for HDP bug, default vram page */
1836struct amdgpu_vram_scratch {
1837 struct amdgpu_bo *robj;
1838 volatile uint32_t *ptr;
1839 u64 gpu_addr;
1840};
1841
1842/*
1843 * ACPI
1844 */
1845struct amdgpu_atif_notification_cfg {
1846 bool enabled;
1847 int command_code;
1848};
1849
1850struct amdgpu_atif_notifications {
1851 bool display_switch;
1852 bool expansion_mode_change;
1853 bool thermal_state;
1854 bool forced_power_state;
1855 bool system_power_state;
1856 bool display_conf_change;
1857 bool px_gfx_switch;
1858 bool brightness_change;
1859 bool dgpu_display_event;
1860};
1861
1862struct amdgpu_atif_functions {
1863 bool system_params;
1864 bool sbios_requests;
1865 bool select_active_disp;
1866 bool lid_state;
1867 bool get_tv_standard;
1868 bool set_tv_standard;
1869 bool get_panel_expansion_mode;
1870 bool set_panel_expansion_mode;
1871 bool temperature_change;
1872 bool graphics_device_types;
1873};
1874
1875struct amdgpu_atif {
1876 struct amdgpu_atif_notifications notifications;
1877 struct amdgpu_atif_functions functions;
1878 struct amdgpu_atif_notification_cfg notification_cfg;
1879 struct amdgpu_encoder *encoder_for_bl;
1880};
1881
1882struct amdgpu_atcs_functions {
1883 bool get_ext_state;
1884 bool pcie_perf_req;
1885 bool pcie_dev_rdy;
1886 bool pcie_bus_width;
1887};
1888
1889struct amdgpu_atcs {
1890 struct amdgpu_atcs_functions functions;
1891};
1892
d03846af
CZ		 1893/*
1894 * CGS
1895 */
1896void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1897void amdgpu_cgs_destroy_device(void *cgs_device);
1898
1899
a8fe58ce
MB		 1900/*
1901 * CGS
1902 */
1903void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1904void amdgpu_cgs_destroy_device(void *cgs_device);
1905
1906
7e471e6f
AD		 1907/* GPU virtualization */
1908struct amdgpu_virtualization {
1909 bool supports_sr_iov;
1910};
1911
97b2e202
AD		 1912/*
1913 * Core structure, functions and helpers.
1914 */
1915typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1916typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1917
1918typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1919typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1920
8faf0e08
AD		 1921struct amdgpu_ip_block_status {
1922 bool valid;
1923 bool sw;
1924 bool hw;
1925};
1926
97b2e202
AD		 1927struct amdgpu_device {
1928 struct device *dev;
1929 struct drm_device *ddev;
1930 struct pci_dev *pdev;
97b2e202 1931
a8fe58ce
MB		 1932#ifdef CONFIG_DRM_AMD_ACP
1933 struct amdgpu_acp acp;
1934#endif
1935
97b2e202 1936 /* ASIC */
2f7d10b3 1937 enum amd_asic_type asic_type;
97b2e202
AD		 1938 uint32_t family;
1939 uint32_t rev_id;
1940 uint32_t external_rev_id;
1941 unsigned long flags;
1942 int usec_timeout;
1943 const struct amdgpu_asic_funcs *asic_funcs;
1944 bool shutdown;
1945 bool suspend;
1946 bool need_dma32;
1947 bool accel_working;
97b2e202
AD		 1948 struct work_struct reset_work;
1949 struct notifier_block acpi_nb;
1950 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1951 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1952 unsigned debugfs_count;
1953#if defined(CONFIG_DEBUG_FS)
1954 struct dentry *debugfs_regs;
1955#endif
1956 struct amdgpu_atif atif;
1957 struct amdgpu_atcs atcs;
1958 struct mutex srbm_mutex;
1959 /* GRBM index mutex. Protects concurrent access to GRBM index */
1960 struct mutex grbm_idx_mutex;
1961 struct dev_pm_domain vga_pm_domain;
1962 bool have_disp_power_ref;
1963
1964 /* BIOS */
1965 uint8_t *bios;
1966 bool is_atom_bios;
1967 uint16_t bios_header_start;
1968 struct amdgpu_bo *stollen_vga_memory;
1969 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1970
1971 /* Register/doorbell mmio */
1972 resource_size_t rmmio_base;
1973 resource_size_t rmmio_size;
1974 void __iomem *rmmio;
1975 /* protects concurrent MM_INDEX/DATA based register access */
1976 spinlock_t mmio_idx_lock;
1977 /* protects concurrent SMC based register access */
1978 spinlock_t smc_idx_lock;
1979 amdgpu_rreg_t smc_rreg;
1980 amdgpu_wreg_t smc_wreg;
1981 /* protects concurrent PCIE register access */
1982 spinlock_t pcie_idx_lock;
1983 amdgpu_rreg_t pcie_rreg;
1984 amdgpu_wreg_t pcie_wreg;
1985 /* protects concurrent UVD register access */
1986 spinlock_t uvd_ctx_idx_lock;
1987 amdgpu_rreg_t uvd_ctx_rreg;
1988 amdgpu_wreg_t uvd_ctx_wreg;
1989 /* protects concurrent DIDT register access */
1990 spinlock_t didt_idx_lock;
1991 amdgpu_rreg_t didt_rreg;
1992 amdgpu_wreg_t didt_wreg;
1993 /* protects concurrent ENDPOINT (audio) register access */
1994 spinlock_t audio_endpt_idx_lock;
1995 amdgpu_block_rreg_t audio_endpt_rreg;
1996 amdgpu_block_wreg_t audio_endpt_wreg;
1997 void __iomem *rio_mem;
1998 resource_size_t rio_mem_size;
1999 struct amdgpu_doorbell doorbell;
2000
2001 /* clock/pll info */
2002 struct amdgpu_clock clock;
2003
2004 /* MC */
2005 struct amdgpu_mc mc;
2006 struct amdgpu_gart gart;
2007 struct amdgpu_dummy_page dummy_page;
2008 struct amdgpu_vm_manager vm_manager;
2009
2010 /* memory management */
2011 struct amdgpu_mman mman;
97b2e202
AD		 2012 struct amdgpu_vram_scratch vram_scratch;
2013 struct amdgpu_wb wb;
2014 atomic64_t vram_usage;
2015 atomic64_t vram_vis_usage;
2016 atomic64_t gtt_usage;
2017 atomic64_t num_bytes_moved;
d94aed5a 2018 atomic_t gpu_reset_counter;
97b2e202
AD		 2019
2020 /* display */
2021 struct amdgpu_mode_info mode_info;
2022 struct work_struct hotplug_work;
2023 struct amdgpu_irq_src crtc_irq;
2024 struct amdgpu_irq_src pageflip_irq;
2025 struct amdgpu_irq_src hpd_irq;
2026
2027 /* rings */
97b2e202 2028 unsigned fence_context;
97b2e202
AD		 2029 unsigned num_rings;
2030 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2031 bool ib_pool_ready;
2032 struct amdgpu_sa_manager ring_tmp_bo;
2033
2034 /* interrupts */
2035 struct amdgpu_irq irq;
2036
1f7371b2
AD		 2037 /* powerplay */
2038 struct amd_powerplay powerplay;
e61710c5 2039 bool pp_enabled;
f3898ea1 2040 bool pp_force_state_enabled;
1f7371b2 2041
97b2e202
AD		 2042 /* dpm */
2043 struct amdgpu_pm pm;
2044 u32 cg_flags;
2045 u32 pg_flags;
2046
2047 /* amdgpu smumgr */
2048 struct amdgpu_smumgr smu;
2049
2050 /* gfx */
2051 struct amdgpu_gfx gfx;
2052
2053 /* sdma */
c113ea1c 2054 struct amdgpu_sdma sdma;
97b2e202
AD		 2055
2056 /* uvd */
97b2e202
AD		 2057 struct amdgpu_uvd uvd;
2058
2059 /* vce */
2060 struct amdgpu_vce vce;
2061
2062 /* firmwares */
2063 struct amdgpu_firmware firmware;
2064
2065 /* GDS */
2066 struct amdgpu_gds gds;
2067
2068 const struct amdgpu_ip_block_version *ip_blocks;
2069 int num_ip_blocks;
8faf0e08 2070 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2071 struct mutex mn_lock;
2072 DECLARE_HASHTABLE(mn_hash, 7);
2073
2074 /* tracking pinned memory */
2075 u64 vram_pin_size;
2076 u64 gart_pin_size;
130e0371
OG		 2077
2078 /* amdkfd interface */
2079 struct kfd_dev *kfd;
23ca0e4e 2080
7e471e6f 2081 struct amdgpu_virtualization virtualization;
97b2e202
AD		 2082};
2083
2084bool amdgpu_device_is_px(struct drm_device *dev);
2085int amdgpu_device_init(struct amdgpu_device *adev,
2086 struct drm_device *ddev,
2087 struct pci_dev *pdev,
2088 uint32_t flags);
2089void amdgpu_device_fini(struct amdgpu_device *adev);
2090int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2091
2092uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2093 bool always_indirect);
2094void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2095 bool always_indirect);
2096u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2097void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2098
2099u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2100void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2101
2102/*
2103 * Cast helper
2104 */
2105extern const struct fence_ops amdgpu_fence_ops;
2106static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2107{
2108 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2109
2110 if (__f->base.ops == &amdgpu_fence_ops)
2111 return __f;
2112
2113 return NULL;
2114}
2115
2116/*
2117 * Registers read & write functions.
2118 */
2119#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2120#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2121#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2122#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2123#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2124#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2125#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2126#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2127#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2128#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2129#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2130#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2131#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2132#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2133#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2134#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2135#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2136#define WREG32_P(reg, val, mask) \
2137 do { \
2138 uint32_t tmp_ = RREG32(reg); \
2139 tmp_ &= (mask); \
2140 tmp_ |= ((val) & ~(mask)); \
2141 WREG32(reg, tmp_); \
2142 } while (0)
2143#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2144#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2145#define WREG32_PLL_P(reg, val, mask) \
2146 do { \
2147 uint32_t tmp_ = RREG32_PLL(reg); \
2148 tmp_ &= (mask); \
2149 tmp_ |= ((val) & ~(mask)); \
2150 WREG32_PLL(reg, tmp_); \
2151 } while (0)
2152#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2153#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2154#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2155
2156#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2157#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2158
2159#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2160#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2161
2162#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2163 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2164 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2165
2166#define REG_GET_FIELD(value, reg, field) \
2167 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2168
2169/*
2170 * BIOS helpers.
2171 */
2172#define RBIOS8(i) (adev->bios[i])
2173#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2174#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2175
2176/*
2177 * RING helpers.
2178 */
2179static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2180{
2181 if (ring->count_dw <= 0)
86c2b790 2182 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2183 ring->ring[ring->wptr++] = v;
2184 ring->wptr &= ring->ptr_mask;
2185 ring->count_dw--;
97b2e202
AD		 2186}
2187
c113ea1c
AD		 2188static inline struct amdgpu_sdma_instance *
2189amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2190{
2191 struct amdgpu_device *adev = ring->adev;
2192 int i;
2193
c113ea1c
AD		 2194 for (i = 0; i < adev->sdma.num_instances; i++)
2195 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2196 break;
2197
2198 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2199 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2200 else
2201 return NULL;
2202}
2203
97b2e202
AD		 2204/*
2205 * ASICs macro.
2206 */
2207#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2208#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2209#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2210#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2211#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2212#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2213#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2214#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2215#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2216#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2217#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2218#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2219#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2220#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
b07c9d2a 2221#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
97b2e202 2222#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 2223#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2224#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2225#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2226#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2227#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2228#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2229#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2230#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2231#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2232#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2233#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 2234#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
9e5d5309 2235#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
97b2e202
AD		 2236#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2237#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2238#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2239#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2240#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2241#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2242#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2243#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2244#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2245#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2246#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2247#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2248#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2249#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2250#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2251#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2252#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2253#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2254#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2255#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2256#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2257#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2258#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2259#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2260#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2261#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2262#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2263#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2264
2265#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2266 ((adev)->pp_enabled ? \
e61710c5 2267 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2268 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2269
2270#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2271 ((adev)->pp_enabled ? \
e61710c5 2272 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2273 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2274
2275#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2276 ((adev)->pp_enabled ? \
e61710c5 2277 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2278 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2279
2280#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2281 ((adev)->pp_enabled ? \
e61710c5 2282 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2283 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2284
2285#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2286 ((adev)->pp_enabled ? \
e61710c5 2287 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2288 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2289
1b5708ff 2290#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2291 ((adev)->pp_enabled ? \
e61710c5 2292 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2293 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2294
2295#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2296 ((adev)->pp_enabled ? \
e61710c5 2297 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2298 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2299
2300
2301#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2302 ((adev)->pp_enabled ? \
e61710c5 2303 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2304 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2305
2306#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2307 ((adev)->pp_enabled ? \
e61710c5 2308 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2309 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2310
2311#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2312 ((adev)->pp_enabled ? \
e61710c5 2313 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2314 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2315
2316#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2317 ((adev)->pp_enabled ? \
e61710c5 2318 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2319 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2320
2321#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2322 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2323
2324#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2325 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2326
f3898ea1
EH		 2327#define amdgpu_dpm_get_pp_num_states(adev, data) \
2328 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2329
2330#define amdgpu_dpm_get_pp_table(adev, table) \
2331 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2332
2333#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2334 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2335
2336#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2337 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2338
2339#define amdgpu_dpm_force_clock_level(adev, type, level) \
2340 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2341
e61710c5 2342#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2343 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2344
2345#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2346
2347/* Common functions */
2348int amdgpu_gpu_reset(struct amdgpu_device *adev);
2349void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2350bool amdgpu_card_posted(struct amdgpu_device *adev);
2351void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 2352
97b2e202
AD		 2353int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2354int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2355 u32 ip_instance, u32 ring,
2356 struct amdgpu_ring **out_ring);
2357void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2358bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2359int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2360 uint32_t flags);
cc325d19 2361struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 2362bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2363 unsigned long end);
97b2e202
AD		 2364bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2365uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2366 struct ttm_mem_reg *mem);
2367void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2368void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2369void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2370void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2371 const u32 *registers,
2372 const u32 array_size);
2373
2374bool amdgpu_device_is_px(struct drm_device *dev);
2375/* atpx handler */
2376#if defined(CONFIG_VGA_SWITCHEROO)
2377void amdgpu_register_atpx_handler(void);
2378void amdgpu_unregister_atpx_handler(void);
2379#else
2380static inline void amdgpu_register_atpx_handler(void) {}
2381static inline void amdgpu_unregister_atpx_handler(void) {}
2382#endif
2383
2384/*
2385 * KMS
2386 */
2387extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2388extern int amdgpu_max_kms_ioctl;
2389
2390int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2391int amdgpu_driver_unload_kms(struct drm_device *dev);
2392void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2393int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2394void amdgpu_driver_postclose_kms(struct drm_device *dev,
2395 struct drm_file *file_priv);
2396void amdgpu_driver_preclose_kms(struct drm_device *dev,
2397 struct drm_file *file_priv);
2398int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2399int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2400u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2401int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2402void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2403int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2404 int *max_error,
2405 struct timeval *vblank_time,
2406 unsigned flags);
2407long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2408 unsigned long arg);
2409
97b2e202
AD		 2410/*
2411 * functions used by amdgpu_encoder.c
2412 */
2413struct amdgpu_afmt_acr {
2414 u32 clock;
2415
2416 int n_32khz;
2417 int cts_32khz;
2418
2419 int n_44_1khz;
2420 int cts_44_1khz;
2421
2422 int n_48khz;
2423 int cts_48khz;
2424
2425};
2426
2427struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2428
2429/* amdgpu_acpi.c */
2430#if defined(CONFIG_ACPI)
2431int amdgpu_acpi_init(struct amdgpu_device *adev);
2432void amdgpu_acpi_fini(struct amdgpu_device *adev);
2433bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2434int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2435 u8 perf_req, bool advertise);
2436int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2437#else
2438static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2439static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2440#endif
2441
2442struct amdgpu_bo_va_mapping *
2443amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2444 uint64_t addr, struct amdgpu_bo **bo);
2445
2446#include "amdgpu_object.h"
2447
2448#endif
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