]>
Commit | Line | Data |
---|---|---|
97b2e202 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __AMDGPU_H__ | |
29 | #define __AMDGPU_H__ | |
30 | ||
31 | #include <linux/atomic.h> | |
32 | #include <linux/wait.h> | |
33 | #include <linux/list.h> | |
34 | #include <linux/kref.h> | |
35 | #include <linux/interval_tree.h> | |
36 | #include <linux/hashtable.h> | |
37 | #include <linux/fence.h> | |
38 | ||
39 | #include <ttm/ttm_bo_api.h> | |
40 | #include <ttm/ttm_bo_driver.h> | |
41 | #include <ttm/ttm_placement.h> | |
42 | #include <ttm/ttm_module.h> | |
43 | #include <ttm/ttm_execbuf_util.h> | |
44 | ||
d03846af | 45 | #include <drm/drmP.h> |
97b2e202 | 46 | #include <drm/drm_gem.h> |
7e5a547f | 47 | #include <drm/amdgpu_drm.h> |
97b2e202 | 48 | |
5fc3aeeb | 49 | #include "amd_shared.h" |
97b2e202 AD |
50 | #include "amdgpu_mode.h" |
51 | #include "amdgpu_ih.h" | |
52 | #include "amdgpu_irq.h" | |
53 | #include "amdgpu_ucode.h" | |
54 | #include "amdgpu_gds.h" | |
1f7371b2 | 55 | #include "amd_powerplay.h" |
a8fe58ce | 56 | #include "amdgpu_acp.h" |
97b2e202 | 57 | |
b80d8475 AD |
58 | #include "gpu_scheduler.h" |
59 | ||
97b2e202 AD |
60 | /* |
61 | * Modules parameters. | |
62 | */ | |
63 | extern int amdgpu_modeset; | |
64 | extern int amdgpu_vram_limit; | |
65 | extern int amdgpu_gart_size; | |
66 | extern int amdgpu_benchmarking; | |
67 | extern int amdgpu_testing; | |
68 | extern int amdgpu_audio; | |
69 | extern int amdgpu_disp_priority; | |
70 | extern int amdgpu_hw_i2c; | |
71 | extern int amdgpu_pcie_gen2; | |
72 | extern int amdgpu_msi; | |
73 | extern int amdgpu_lockup_timeout; | |
74 | extern int amdgpu_dpm; | |
75 | extern int amdgpu_smc_load_fw; | |
76 | extern int amdgpu_aspm; | |
77 | extern int amdgpu_runtime_pm; | |
97b2e202 AD |
78 | extern unsigned amdgpu_ip_block_mask; |
79 | extern int amdgpu_bapm; | |
80 | extern int amdgpu_deep_color; | |
81 | extern int amdgpu_vm_size; | |
82 | extern int amdgpu_vm_block_size; | |
d9c13156 | 83 | extern int amdgpu_vm_fault_stop; |
b495bd3a | 84 | extern int amdgpu_vm_debug; |
1333f723 | 85 | extern int amdgpu_sched_jobs; |
4afcb303 | 86 | extern int amdgpu_sched_hw_submission; |
1f7371b2 | 87 | extern int amdgpu_powerplay; |
97b2e202 | 88 | |
4b559c90 | 89 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
97b2e202 AD |
90 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
91 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
92 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ | |
93 | #define AMDGPU_IB_POOL_SIZE 16 | |
94 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 | |
95 | #define AMDGPUFB_CONN_LIMIT 4 | |
96 | #define AMDGPU_BIOS_NUM_SCRATCH 8 | |
97 | ||
97b2e202 AD |
98 | /* max number of rings */ |
99 | #define AMDGPU_MAX_RINGS 16 | |
100 | #define AMDGPU_MAX_GFX_RINGS 1 | |
101 | #define AMDGPU_MAX_COMPUTE_RINGS 8 | |
102 | #define AMDGPU_MAX_VCE_RINGS 2 | |
103 | ||
36f523a7 JZ |
104 | /* max number of IP instances */ |
105 | #define AMDGPU_MAX_SDMA_INSTANCES 2 | |
106 | ||
97b2e202 AD |
107 | /* hardcode that limit for now */ |
108 | #define AMDGPU_VA_RESERVED_SIZE (8 << 20) | |
109 | ||
110 | /* hard reset data */ | |
111 | #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b | |
112 | ||
113 | /* reset flags */ | |
114 | #define AMDGPU_RESET_GFX (1 << 0) | |
115 | #define AMDGPU_RESET_COMPUTE (1 << 1) | |
116 | #define AMDGPU_RESET_DMA (1 << 2) | |
117 | #define AMDGPU_RESET_CP (1 << 3) | |
118 | #define AMDGPU_RESET_GRBM (1 << 4) | |
119 | #define AMDGPU_RESET_DMA1 (1 << 5) | |
120 | #define AMDGPU_RESET_RLC (1 << 6) | |
121 | #define AMDGPU_RESET_SEM (1 << 7) | |
122 | #define AMDGPU_RESET_IH (1 << 8) | |
123 | #define AMDGPU_RESET_VMC (1 << 9) | |
124 | #define AMDGPU_RESET_MC (1 << 10) | |
125 | #define AMDGPU_RESET_DISPLAY (1 << 11) | |
126 | #define AMDGPU_RESET_UVD (1 << 12) | |
127 | #define AMDGPU_RESET_VCE (1 << 13) | |
128 | #define AMDGPU_RESET_VCE1 (1 << 14) | |
129 | ||
130 | /* CG block flags */ | |
131 | #define AMDGPU_CG_BLOCK_GFX (1 << 0) | |
132 | #define AMDGPU_CG_BLOCK_MC (1 << 1) | |
133 | #define AMDGPU_CG_BLOCK_SDMA (1 << 2) | |
134 | #define AMDGPU_CG_BLOCK_UVD (1 << 3) | |
135 | #define AMDGPU_CG_BLOCK_VCE (1 << 4) | |
136 | #define AMDGPU_CG_BLOCK_HDP (1 << 5) | |
137 | #define AMDGPU_CG_BLOCK_BIF (1 << 6) | |
138 | ||
139 | /* CG flags */ | |
140 | #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) | |
141 | #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) | |
142 | #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) | |
143 | #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) | |
144 | #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) | |
145 | #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) | |
146 | #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) | |
147 | #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) | |
148 | #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) | |
149 | #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) | |
150 | #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) | |
151 | #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) | |
152 | #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) | |
153 | #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) | |
154 | #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) | |
155 | #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) | |
156 | #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) | |
157 | ||
158 | /* PG flags */ | |
159 | #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) | |
160 | #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) | |
161 | #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) | |
162 | #define AMDGPU_PG_SUPPORT_UVD (1 << 3) | |
163 | #define AMDGPU_PG_SUPPORT_VCE (1 << 4) | |
164 | #define AMDGPU_PG_SUPPORT_CP (1 << 5) | |
165 | #define AMDGPU_PG_SUPPORT_GDS (1 << 6) | |
166 | #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) | |
167 | #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) | |
168 | #define AMDGPU_PG_SUPPORT_ACP (1 << 9) | |
169 | #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) | |
170 | ||
171 | /* GFX current status */ | |
172 | #define AMDGPU_GFX_NORMAL_MODE 0x00000000L | |
173 | #define AMDGPU_GFX_SAFE_MODE 0x00000001L | |
174 | #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L | |
175 | #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L | |
176 | #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L | |
177 | ||
178 | /* max cursor sizes (in pixels) */ | |
179 | #define CIK_CURSOR_WIDTH 128 | |
180 | #define CIK_CURSOR_HEIGHT 128 | |
181 | ||
182 | struct amdgpu_device; | |
97b2e202 AD |
183 | struct amdgpu_ib; |
184 | struct amdgpu_vm; | |
185 | struct amdgpu_ring; | |
97b2e202 | 186 | struct amdgpu_cs_parser; |
bb977d37 | 187 | struct amdgpu_job; |
97b2e202 | 188 | struct amdgpu_irq_src; |
0b492a4c | 189 | struct amdgpu_fpriv; |
97b2e202 AD |
190 | |
191 | enum amdgpu_cp_irq { | |
192 | AMDGPU_CP_IRQ_GFX_EOP = 0, | |
193 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, | |
194 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, | |
195 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, | |
196 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, | |
197 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, | |
198 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, | |
199 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, | |
200 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, | |
201 | ||
202 | AMDGPU_CP_IRQ_LAST | |
203 | }; | |
204 | ||
205 | enum amdgpu_sdma_irq { | |
206 | AMDGPU_SDMA_IRQ_TRAP0 = 0, | |
207 | AMDGPU_SDMA_IRQ_TRAP1, | |
208 | ||
209 | AMDGPU_SDMA_IRQ_LAST | |
210 | }; | |
211 | ||
212 | enum amdgpu_thermal_irq { | |
213 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, | |
214 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, | |
215 | ||
216 | AMDGPU_THERMAL_IRQ_LAST | |
217 | }; | |
218 | ||
97b2e202 | 219 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, |
5fc3aeeb | 220 | enum amd_ip_block_type block_type, |
221 | enum amd_clockgating_state state); | |
97b2e202 | 222 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, |
5fc3aeeb | 223 | enum amd_ip_block_type block_type, |
224 | enum amd_powergating_state state); | |
97b2e202 AD |
225 | |
226 | struct amdgpu_ip_block_version { | |
5fc3aeeb | 227 | enum amd_ip_block_type type; |
97b2e202 AD |
228 | u32 major; |
229 | u32 minor; | |
230 | u32 rev; | |
5fc3aeeb | 231 | const struct amd_ip_funcs *funcs; |
97b2e202 AD |
232 | }; |
233 | ||
234 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 235 | enum amd_ip_block_type type, |
97b2e202 AD |
236 | u32 major, u32 minor); |
237 | ||
238 | const struct amdgpu_ip_block_version * amdgpu_get_ip_block( | |
239 | struct amdgpu_device *adev, | |
5fc3aeeb | 240 | enum amd_ip_block_type type); |
97b2e202 AD |
241 | |
242 | /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ | |
243 | struct amdgpu_buffer_funcs { | |
244 | /* maximum bytes in a single operation */ | |
245 | uint32_t copy_max_bytes; | |
246 | ||
247 | /* number of dw to reserve per operation */ | |
248 | unsigned copy_num_dw; | |
249 | ||
250 | /* used for buffer migration */ | |
c7ae72c0 | 251 | void (*emit_copy_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
252 | /* src addr in bytes */ |
253 | uint64_t src_offset, | |
254 | /* dst addr in bytes */ | |
255 | uint64_t dst_offset, | |
256 | /* number of byte to transfer */ | |
257 | uint32_t byte_count); | |
258 | ||
259 | /* maximum bytes in a single operation */ | |
260 | uint32_t fill_max_bytes; | |
261 | ||
262 | /* number of dw to reserve per operation */ | |
263 | unsigned fill_num_dw; | |
264 | ||
265 | /* used for buffer clearing */ | |
6e7a3840 | 266 | void (*emit_fill_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
267 | /* value to write to memory */ |
268 | uint32_t src_data, | |
269 | /* dst addr in bytes */ | |
270 | uint64_t dst_offset, | |
271 | /* number of byte to fill */ | |
272 | uint32_t byte_count); | |
273 | }; | |
274 | ||
275 | /* provided by hw blocks that can write ptes, e.g., sdma */ | |
276 | struct amdgpu_vm_pte_funcs { | |
277 | /* copy pte entries from GART */ | |
278 | void (*copy_pte)(struct amdgpu_ib *ib, | |
279 | uint64_t pe, uint64_t src, | |
280 | unsigned count); | |
281 | /* write pte one entry at a time with addr mapping */ | |
282 | void (*write_pte)(struct amdgpu_ib *ib, | |
b07c9d2a | 283 | const dma_addr_t *pages_addr, uint64_t pe, |
97b2e202 AD |
284 | uint64_t addr, unsigned count, |
285 | uint32_t incr, uint32_t flags); | |
286 | /* for linear pte/pde updates without addr mapping */ | |
287 | void (*set_pte_pde)(struct amdgpu_ib *ib, | |
288 | uint64_t pe, | |
289 | uint64_t addr, unsigned count, | |
290 | uint32_t incr, uint32_t flags); | |
97b2e202 AD |
291 | }; |
292 | ||
293 | /* provided by the gmc block */ | |
294 | struct amdgpu_gart_funcs { | |
295 | /* flush the vm tlb via mmio */ | |
296 | void (*flush_gpu_tlb)(struct amdgpu_device *adev, | |
297 | uint32_t vmid); | |
298 | /* write pte/pde updates using the cpu */ | |
299 | int (*set_pte_pde)(struct amdgpu_device *adev, | |
300 | void *cpu_pt_addr, /* cpu addr of page table */ | |
301 | uint32_t gpu_page_idx, /* pte/pde to update */ | |
302 | uint64_t addr, /* addr to write into pte/pde */ | |
303 | uint32_t flags); /* access flags */ | |
304 | }; | |
305 | ||
306 | /* provided by the ih block */ | |
307 | struct amdgpu_ih_funcs { | |
308 | /* ring read/write ptr handling, called from interrupt context */ | |
309 | u32 (*get_wptr)(struct amdgpu_device *adev); | |
310 | void (*decode_iv)(struct amdgpu_device *adev, | |
311 | struct amdgpu_iv_entry *entry); | |
312 | void (*set_rptr)(struct amdgpu_device *adev); | |
313 | }; | |
314 | ||
315 | /* provided by hw blocks that expose a ring buffer for commands */ | |
316 | struct amdgpu_ring_funcs { | |
317 | /* ring read/write ptr handling */ | |
318 | u32 (*get_rptr)(struct amdgpu_ring *ring); | |
319 | u32 (*get_wptr)(struct amdgpu_ring *ring); | |
320 | void (*set_wptr)(struct amdgpu_ring *ring); | |
321 | /* validating and patching of IBs */ | |
322 | int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); | |
323 | /* command emit functions */ | |
324 | void (*emit_ib)(struct amdgpu_ring *ring, | |
325 | struct amdgpu_ib *ib); | |
326 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, | |
890ee23f | 327 | uint64_t seq, unsigned flags); |
b8c7b39e | 328 | void (*emit_pipeline_sync)(struct amdgpu_ring *ring); |
97b2e202 AD |
329 | void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, |
330 | uint64_t pd_addr); | |
d2edb07b | 331 | void (*emit_hdp_flush)(struct amdgpu_ring *ring); |
11afbde8 | 332 | void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); |
97b2e202 AD |
333 | void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, |
334 | uint32_t gds_base, uint32_t gds_size, | |
335 | uint32_t gws_base, uint32_t gws_size, | |
336 | uint32_t oa_base, uint32_t oa_size); | |
337 | /* testing functions */ | |
338 | int (*test_ring)(struct amdgpu_ring *ring); | |
339 | int (*test_ib)(struct amdgpu_ring *ring); | |
edff0e28 JZ |
340 | /* insert NOP packets */ |
341 | void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); | |
9e5d5309 CK |
342 | /* pad the indirect buffer to the necessary number of dw */ |
343 | void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | |
97b2e202 AD |
344 | }; |
345 | ||
346 | /* | |
347 | * BIOS. | |
348 | */ | |
349 | bool amdgpu_get_bios(struct amdgpu_device *adev); | |
350 | bool amdgpu_read_bios(struct amdgpu_device *adev); | |
351 | ||
352 | /* | |
353 | * Dummy page | |
354 | */ | |
355 | struct amdgpu_dummy_page { | |
356 | struct page *page; | |
357 | dma_addr_t addr; | |
358 | }; | |
359 | int amdgpu_dummy_page_init(struct amdgpu_device *adev); | |
360 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev); | |
361 | ||
362 | ||
363 | /* | |
364 | * Clocks | |
365 | */ | |
366 | ||
367 | #define AMDGPU_MAX_PPLL 3 | |
368 | ||
369 | struct amdgpu_clock { | |
370 | struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; | |
371 | struct amdgpu_pll spll; | |
372 | struct amdgpu_pll mpll; | |
373 | /* 10 Khz units */ | |
374 | uint32_t default_mclk; | |
375 | uint32_t default_sclk; | |
376 | uint32_t default_dispclk; | |
377 | uint32_t current_dispclk; | |
378 | uint32_t dp_extclk; | |
379 | uint32_t max_pixel_clock; | |
380 | }; | |
381 | ||
382 | /* | |
383 | * Fences. | |
384 | */ | |
385 | struct amdgpu_fence_driver { | |
97b2e202 AD |
386 | uint64_t gpu_addr; |
387 | volatile uint32_t *cpu_addr; | |
388 | /* sync_seq is protected by ring emission lock */ | |
742c085f CK |
389 | uint32_t sync_seq; |
390 | atomic_t last_seq; | |
97b2e202 | 391 | bool initialized; |
97b2e202 AD |
392 | struct amdgpu_irq_src *irq_src; |
393 | unsigned irq_type; | |
c2776afe | 394 | struct timer_list fallback_timer; |
c89377d1 | 395 | unsigned num_fences_mask; |
4a7d74f1 | 396 | spinlock_t lock; |
c89377d1 | 397 | struct fence **fences; |
97b2e202 AD |
398 | }; |
399 | ||
400 | /* some special values for the owner field */ | |
401 | #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) | |
402 | #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) | |
97b2e202 | 403 | |
890ee23f CZ |
404 | #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) |
405 | #define AMDGPU_FENCE_FLAG_INT (1 << 1) | |
406 | ||
97b2e202 AD |
407 | struct amdgpu_user_fence { |
408 | /* write-back bo */ | |
409 | struct amdgpu_bo *bo; | |
410 | /* write-back address offset to bo start */ | |
411 | uint32_t offset; | |
412 | }; | |
413 | ||
414 | int amdgpu_fence_driver_init(struct amdgpu_device *adev); | |
415 | void amdgpu_fence_driver_fini(struct amdgpu_device *adev); | |
416 | void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); | |
417 | ||
e6151a08 CK |
418 | int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, |
419 | unsigned num_hw_submission); | |
97b2e202 AD |
420 | int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, |
421 | struct amdgpu_irq_src *irq_src, | |
422 | unsigned irq_type); | |
5ceb54c6 AD |
423 | void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); |
424 | void amdgpu_fence_driver_resume(struct amdgpu_device *adev); | |
364beb2c | 425 | int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); |
97b2e202 | 426 | void amdgpu_fence_process(struct amdgpu_ring *ring); |
97b2e202 AD |
427 | int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); |
428 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); | |
429 | ||
97b2e202 AD |
430 | /* |
431 | * TTM. | |
432 | */ | |
433 | struct amdgpu_mman { | |
434 | struct ttm_bo_global_ref bo_global_ref; | |
435 | struct drm_global_reference mem_global_ref; | |
436 | struct ttm_bo_device bdev; | |
437 | bool mem_global_referenced; | |
438 | bool initialized; | |
439 | ||
440 | #if defined(CONFIG_DEBUG_FS) | |
441 | struct dentry *vram; | |
442 | struct dentry *gtt; | |
443 | #endif | |
444 | ||
445 | /* buffer handling */ | |
446 | const struct amdgpu_buffer_funcs *buffer_funcs; | |
447 | struct amdgpu_ring *buffer_funcs_ring; | |
703297c1 CK |
448 | /* Scheduler entity for buffer moves */ |
449 | struct amd_sched_entity entity; | |
97b2e202 AD |
450 | }; |
451 | ||
452 | int amdgpu_copy_buffer(struct amdgpu_ring *ring, | |
453 | uint64_t src_offset, | |
454 | uint64_t dst_offset, | |
455 | uint32_t byte_count, | |
456 | struct reservation_object *resv, | |
c7ae72c0 | 457 | struct fence **fence); |
97b2e202 AD |
458 | int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); |
459 | ||
460 | struct amdgpu_bo_list_entry { | |
461 | struct amdgpu_bo *robj; | |
462 | struct ttm_validate_buffer tv; | |
463 | struct amdgpu_bo_va *bo_va; | |
97b2e202 | 464 | uint32_t priority; |
2f568dbd CK |
465 | struct page **user_pages; |
466 | int user_invalidated; | |
97b2e202 AD |
467 | }; |
468 | ||
469 | struct amdgpu_bo_va_mapping { | |
470 | struct list_head list; | |
471 | struct interval_tree_node it; | |
472 | uint64_t offset; | |
473 | uint32_t flags; | |
474 | }; | |
475 | ||
476 | /* bo virtual addresses in a specific vm */ | |
477 | struct amdgpu_bo_va { | |
478 | /* protected by bo being reserved */ | |
479 | struct list_head bo_list; | |
bb1e38a4 | 480 | struct fence *last_pt_update; |
97b2e202 AD |
481 | unsigned ref_count; |
482 | ||
7fc11959 | 483 | /* protected by vm mutex and spinlock */ |
97b2e202 AD |
484 | struct list_head vm_status; |
485 | ||
7fc11959 CK |
486 | /* mappings for this bo_va */ |
487 | struct list_head invalids; | |
488 | struct list_head valids; | |
489 | ||
97b2e202 AD |
490 | /* constant after initialization */ |
491 | struct amdgpu_vm *vm; | |
492 | struct amdgpu_bo *bo; | |
493 | }; | |
494 | ||
7e5a547f CZ |
495 | #define AMDGPU_GEM_DOMAIN_MAX 0x3 |
496 | ||
97b2e202 AD |
497 | struct amdgpu_bo { |
498 | /* Protected by gem.mutex */ | |
499 | struct list_head list; | |
500 | /* Protected by tbo.reserved */ | |
1ea863fd CK |
501 | u32 prefered_domains; |
502 | u32 allowed_domains; | |
7e5a547f | 503 | struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; |
97b2e202 AD |
504 | struct ttm_placement placement; |
505 | struct ttm_buffer_object tbo; | |
506 | struct ttm_bo_kmap_obj kmap; | |
507 | u64 flags; | |
508 | unsigned pin_count; | |
509 | void *kptr; | |
510 | u64 tiling_flags; | |
511 | u64 metadata_flags; | |
512 | void *metadata; | |
513 | u32 metadata_size; | |
514 | /* list of all virtual address to which this bo | |
515 | * is associated to | |
516 | */ | |
517 | struct list_head va; | |
518 | /* Constant after initialization */ | |
519 | struct amdgpu_device *adev; | |
520 | struct drm_gem_object gem_base; | |
82b9c55b | 521 | struct amdgpu_bo *parent; |
97b2e202 AD |
522 | |
523 | struct ttm_bo_kmap_obj dma_buf_vmap; | |
97b2e202 AD |
524 | struct amdgpu_mn *mn; |
525 | struct list_head mn_list; | |
526 | }; | |
527 | #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) | |
528 | ||
529 | void amdgpu_gem_object_free(struct drm_gem_object *obj); | |
530 | int amdgpu_gem_object_open(struct drm_gem_object *obj, | |
531 | struct drm_file *file_priv); | |
532 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
533 | struct drm_file *file_priv); | |
534 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); | |
535 | struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); | |
536 | struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, | |
537 | struct dma_buf_attachment *attach, | |
538 | struct sg_table *sg); | |
539 | struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, | |
540 | struct drm_gem_object *gobj, | |
541 | int flags); | |
542 | int amdgpu_gem_prime_pin(struct drm_gem_object *obj); | |
543 | void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); | |
544 | struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); | |
545 | void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); | |
546 | void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); | |
547 | int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); | |
548 | ||
549 | /* sub-allocation manager, it has to be protected by another lock. | |
550 | * By conception this is an helper for other part of the driver | |
551 | * like the indirect buffer or semaphore, which both have their | |
552 | * locking. | |
553 | * | |
554 | * Principe is simple, we keep a list of sub allocation in offset | |
555 | * order (first entry has offset == 0, last entry has the highest | |
556 | * offset). | |
557 | * | |
558 | * When allocating new object we first check if there is room at | |
559 | * the end total_size - (last_object_offset + last_object_size) >= | |
560 | * alloc_size. If so we allocate new object there. | |
561 | * | |
562 | * When there is not enough room at the end, we start waiting for | |
563 | * each sub object until we reach object_offset+object_size >= | |
564 | * alloc_size, this object then become the sub object we return. | |
565 | * | |
566 | * Alignment can't be bigger than page size. | |
567 | * | |
568 | * Hole are not considered for allocation to keep things simple. | |
569 | * Assumption is that there won't be hole (all object on same | |
570 | * alignment). | |
571 | */ | |
6ba60b89 CK |
572 | |
573 | #define AMDGPU_SA_NUM_FENCE_LISTS 32 | |
574 | ||
97b2e202 AD |
575 | struct amdgpu_sa_manager { |
576 | wait_queue_head_t wq; | |
577 | struct amdgpu_bo *bo; | |
578 | struct list_head *hole; | |
6ba60b89 | 579 | struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; |
97b2e202 AD |
580 | struct list_head olist; |
581 | unsigned size; | |
582 | uint64_t gpu_addr; | |
583 | void *cpu_ptr; | |
584 | uint32_t domain; | |
585 | uint32_t align; | |
586 | }; | |
587 | ||
588 | struct amdgpu_sa_bo; | |
589 | ||
590 | /* sub-allocation buffer */ | |
591 | struct amdgpu_sa_bo { | |
592 | struct list_head olist; | |
593 | struct list_head flist; | |
594 | struct amdgpu_sa_manager *manager; | |
595 | unsigned soffset; | |
596 | unsigned eoffset; | |
4ce9891e | 597 | struct fence *fence; |
97b2e202 AD |
598 | }; |
599 | ||
600 | /* | |
601 | * GEM objects. | |
602 | */ | |
418aa0c2 | 603 | void amdgpu_gem_force_release(struct amdgpu_device *adev); |
97b2e202 AD |
604 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, |
605 | int alignment, u32 initial_domain, | |
606 | u64 flags, bool kernel, | |
607 | struct drm_gem_object **obj); | |
608 | ||
609 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
610 | struct drm_device *dev, | |
611 | struct drm_mode_create_dumb *args); | |
612 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
613 | struct drm_device *dev, | |
614 | uint32_t handle, uint64_t *offset_p); | |
97b2e202 AD |
615 | /* |
616 | * Synchronization | |
617 | */ | |
618 | struct amdgpu_sync { | |
f91b3a69 | 619 | DECLARE_HASHTABLE(fences, 4); |
3c62338c | 620 | struct fence *last_vm_update; |
97b2e202 AD |
621 | }; |
622 | ||
623 | void amdgpu_sync_create(struct amdgpu_sync *sync); | |
91e1a520 CK |
624 | int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, |
625 | struct fence *f); | |
97b2e202 AD |
626 | int amdgpu_sync_resv(struct amdgpu_device *adev, |
627 | struct amdgpu_sync *sync, | |
628 | struct reservation_object *resv, | |
629 | void *owner); | |
e61235db | 630 | struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); |
f91b3a69 | 631 | int amdgpu_sync_wait(struct amdgpu_sync *sync); |
8a8f0b48 | 632 | void amdgpu_sync_free(struct amdgpu_sync *sync); |
257bf15a CK |
633 | int amdgpu_sync_init(void); |
634 | void amdgpu_sync_fini(void); | |
97b2e202 AD |
635 | |
636 | /* | |
637 | * GART structures, functions & helpers | |
638 | */ | |
639 | struct amdgpu_mc; | |
640 | ||
641 | #define AMDGPU_GPU_PAGE_SIZE 4096 | |
642 | #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) | |
643 | #define AMDGPU_GPU_PAGE_SHIFT 12 | |
644 | #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) | |
645 | ||
646 | struct amdgpu_gart { | |
647 | dma_addr_t table_addr; | |
648 | struct amdgpu_bo *robj; | |
649 | void *ptr; | |
650 | unsigned num_gpu_pages; | |
651 | unsigned num_cpu_pages; | |
652 | unsigned table_size; | |
653 | struct page **pages; | |
654 | dma_addr_t *pages_addr; | |
655 | bool ready; | |
656 | const struct amdgpu_gart_funcs *gart_funcs; | |
657 | }; | |
658 | ||
659 | int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); | |
660 | void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); | |
661 | int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); | |
662 | void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); | |
663 | int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); | |
664 | void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); | |
665 | int amdgpu_gart_init(struct amdgpu_device *adev); | |
666 | void amdgpu_gart_fini(struct amdgpu_device *adev); | |
667 | void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, | |
668 | int pages); | |
669 | int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, | |
670 | int pages, struct page **pagelist, | |
671 | dma_addr_t *dma_addr, uint32_t flags); | |
672 | ||
673 | /* | |
674 | * GPU MC structures, functions & helpers | |
675 | */ | |
676 | struct amdgpu_mc { | |
677 | resource_size_t aper_size; | |
678 | resource_size_t aper_base; | |
679 | resource_size_t agp_base; | |
680 | /* for some chips with <= 32MB we need to lie | |
681 | * about vram size near mc fb location */ | |
682 | u64 mc_vram_size; | |
683 | u64 visible_vram_size; | |
684 | u64 gtt_size; | |
685 | u64 gtt_start; | |
686 | u64 gtt_end; | |
687 | u64 vram_start; | |
688 | u64 vram_end; | |
689 | unsigned vram_width; | |
690 | u64 real_vram_size; | |
691 | int vram_mtrr; | |
692 | u64 gtt_base_align; | |
693 | u64 mc_mask; | |
694 | const struct firmware *fw; /* MC firmware */ | |
695 | uint32_t fw_version; | |
696 | struct amdgpu_irq_src vm_fault; | |
81c59f54 | 697 | uint32_t vram_type; |
97b2e202 AD |
698 | }; |
699 | ||
700 | /* | |
701 | * GPU doorbell structures, functions & helpers | |
702 | */ | |
703 | typedef enum _AMDGPU_DOORBELL_ASSIGNMENT | |
704 | { | |
705 | AMDGPU_DOORBELL_KIQ = 0x000, | |
706 | AMDGPU_DOORBELL_HIQ = 0x001, | |
707 | AMDGPU_DOORBELL_DIQ = 0x002, | |
708 | AMDGPU_DOORBELL_MEC_RING0 = 0x010, | |
709 | AMDGPU_DOORBELL_MEC_RING1 = 0x011, | |
710 | AMDGPU_DOORBELL_MEC_RING2 = 0x012, | |
711 | AMDGPU_DOORBELL_MEC_RING3 = 0x013, | |
712 | AMDGPU_DOORBELL_MEC_RING4 = 0x014, | |
713 | AMDGPU_DOORBELL_MEC_RING5 = 0x015, | |
714 | AMDGPU_DOORBELL_MEC_RING6 = 0x016, | |
715 | AMDGPU_DOORBELL_MEC_RING7 = 0x017, | |
716 | AMDGPU_DOORBELL_GFX_RING0 = 0x020, | |
717 | AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, | |
718 | AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, | |
719 | AMDGPU_DOORBELL_IH = 0x1E8, | |
720 | AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, | |
721 | AMDGPU_DOORBELL_INVALID = 0xFFFF | |
722 | } AMDGPU_DOORBELL_ASSIGNMENT; | |
723 | ||
724 | struct amdgpu_doorbell { | |
725 | /* doorbell mmio */ | |
726 | resource_size_t base; | |
727 | resource_size_t size; | |
728 | u32 __iomem *ptr; | |
729 | u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ | |
730 | }; | |
731 | ||
732 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
733 | phys_addr_t *aperture_base, | |
734 | size_t *aperture_size, | |
735 | size_t *start_offset); | |
736 | ||
737 | /* | |
738 | * IRQS. | |
739 | */ | |
740 | ||
741 | struct amdgpu_flip_work { | |
742 | struct work_struct flip_work; | |
743 | struct work_struct unpin_work; | |
744 | struct amdgpu_device *adev; | |
745 | int crtc_id; | |
746 | uint64_t base; | |
747 | struct drm_pending_vblank_event *event; | |
748 | struct amdgpu_bo *old_rbo; | |
1ffd2652 CK |
749 | struct fence *excl; |
750 | unsigned shared_count; | |
751 | struct fence **shared; | |
c3874b75 | 752 | struct fence_cb cb; |
97b2e202 AD |
753 | }; |
754 | ||
755 | ||
756 | /* | |
757 | * CP & rings. | |
758 | */ | |
759 | ||
760 | struct amdgpu_ib { | |
761 | struct amdgpu_sa_bo *sa_bo; | |
762 | uint32_t length_dw; | |
763 | uint64_t gpu_addr; | |
764 | uint32_t *ptr; | |
364beb2c | 765 | struct fence *fence; |
97b2e202 AD |
766 | struct amdgpu_user_fence *user; |
767 | struct amdgpu_vm *vm; | |
4ff37a83 CK |
768 | unsigned vm_id; |
769 | uint64_t vm_pd_addr; | |
3cb485f3 | 770 | struct amdgpu_ctx *ctx; |
97b2e202 AD |
771 | uint32_t gds_base, gds_size; |
772 | uint32_t gws_base, gws_size; | |
773 | uint32_t oa_base, oa_size; | |
de807f81 | 774 | uint32_t flags; |
5430a3ff CK |
775 | /* resulting sequence number */ |
776 | uint64_t sequence; | |
97b2e202 AD |
777 | }; |
778 | ||
779 | enum amdgpu_ring_type { | |
780 | AMDGPU_RING_TYPE_GFX, | |
781 | AMDGPU_RING_TYPE_COMPUTE, | |
782 | AMDGPU_RING_TYPE_SDMA, | |
783 | AMDGPU_RING_TYPE_UVD, | |
784 | AMDGPU_RING_TYPE_VCE | |
785 | }; | |
786 | ||
c1b69ed0 CZ |
787 | extern struct amd_sched_backend_ops amdgpu_sched_ops; |
788 | ||
50838c8c CK |
789 | int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, |
790 | struct amdgpu_job **job); | |
d71518b5 CK |
791 | int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, |
792 | struct amdgpu_job **job); | |
50838c8c | 793 | void amdgpu_job_free(struct amdgpu_job *job); |
d71518b5 | 794 | int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, |
2bd9ccfa CK |
795 | struct amd_sched_entity *entity, void *owner, |
796 | struct fence **f); | |
3c704e93 | 797 | |
97b2e202 AD |
798 | struct amdgpu_ring { |
799 | struct amdgpu_device *adev; | |
800 | const struct amdgpu_ring_funcs *funcs; | |
801 | struct amdgpu_fence_driver fence_drv; | |
4f839a24 | 802 | struct amd_gpu_scheduler sched; |
97b2e202 | 803 | |
176e1ab1 | 804 | spinlock_t fence_lock; |
97b2e202 AD |
805 | struct amdgpu_bo *ring_obj; |
806 | volatile uint32_t *ring; | |
807 | unsigned rptr_offs; | |
808 | u64 next_rptr_gpu_addr; | |
809 | volatile u32 *next_rptr_cpu_addr; | |
810 | unsigned wptr; | |
811 | unsigned wptr_old; | |
812 | unsigned ring_size; | |
c7e6be23 | 813 | unsigned max_dw; |
97b2e202 | 814 | int count_dw; |
97b2e202 AD |
815 | uint64_t gpu_addr; |
816 | uint32_t align_mask; | |
817 | uint32_t ptr_mask; | |
818 | bool ready; | |
819 | u32 nop; | |
820 | u32 idx; | |
97b2e202 AD |
821 | u32 me; |
822 | u32 pipe; | |
823 | u32 queue; | |
824 | struct amdgpu_bo *mqd_obj; | |
825 | u32 doorbell_index; | |
826 | bool use_doorbell; | |
827 | unsigned wptr_offs; | |
828 | unsigned next_rptr_offs; | |
829 | unsigned fence_offs; | |
3cb485f3 | 830 | struct amdgpu_ctx *current_ctx; |
97b2e202 AD |
831 | enum amdgpu_ring_type type; |
832 | char name[16]; | |
833 | }; | |
834 | ||
835 | /* | |
836 | * VM | |
837 | */ | |
838 | ||
839 | /* maximum number of VMIDs */ | |
840 | #define AMDGPU_NUM_VM 16 | |
841 | ||
842 | /* number of entries in page table */ | |
843 | #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) | |
844 | ||
845 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ | |
846 | #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 | |
847 | #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) | |
848 | #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) | |
849 | ||
850 | #define AMDGPU_PTE_VALID (1 << 0) | |
851 | #define AMDGPU_PTE_SYSTEM (1 << 1) | |
852 | #define AMDGPU_PTE_SNOOPED (1 << 2) | |
853 | ||
854 | /* VI only */ | |
855 | #define AMDGPU_PTE_EXECUTABLE (1 << 4) | |
856 | ||
857 | #define AMDGPU_PTE_READABLE (1 << 5) | |
858 | #define AMDGPU_PTE_WRITEABLE (1 << 6) | |
859 | ||
860 | /* PTE (Page Table Entry) fragment field for different page sizes */ | |
861 | #define AMDGPU_PTE_FRAG_4KB (0 << 7) | |
862 | #define AMDGPU_PTE_FRAG_64KB (4 << 7) | |
863 | #define AMDGPU_LOG2_PAGES_PER_FRAG 4 | |
864 | ||
d9c13156 CK |
865 | /* How to programm VM fault handling */ |
866 | #define AMDGPU_VM_FAULT_STOP_NEVER 0 | |
867 | #define AMDGPU_VM_FAULT_STOP_FIRST 1 | |
868 | #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 | |
869 | ||
97b2e202 | 870 | struct amdgpu_vm_pt { |
ee1782c3 CK |
871 | struct amdgpu_bo_list_entry entry; |
872 | uint64_t addr; | |
97b2e202 AD |
873 | }; |
874 | ||
875 | struct amdgpu_vm_id { | |
4ff37a83 CK |
876 | struct amdgpu_vm_manager_id *mgr_id; |
877 | uint64_t pd_gpu_addr; | |
97b2e202 | 878 | /* last flushed PD/PT update */ |
4ff37a83 | 879 | struct fence *flushed_updates; |
97b2e202 AD |
880 | }; |
881 | ||
882 | struct amdgpu_vm { | |
25cfc3c2 | 883 | /* tree of virtual addresses mapped */ |
97b2e202 AD |
884 | struct rb_root va; |
885 | ||
7fc11959 | 886 | /* protecting invalidated */ |
97b2e202 AD |
887 | spinlock_t status_lock; |
888 | ||
889 | /* BOs moved, but not yet updated in the PT */ | |
890 | struct list_head invalidated; | |
891 | ||
7fc11959 CK |
892 | /* BOs cleared in the PT because of a move */ |
893 | struct list_head cleared; | |
894 | ||
895 | /* BO mappings freed, but not yet updated in the PT */ | |
97b2e202 AD |
896 | struct list_head freed; |
897 | ||
898 | /* contains the page directory */ | |
899 | struct amdgpu_bo *page_directory; | |
900 | unsigned max_pde_used; | |
05906dec | 901 | struct fence *page_directory_fence; |
97b2e202 AD |
902 | |
903 | /* array of page tables, one for each page directory entry */ | |
904 | struct amdgpu_vm_pt *page_tables; | |
905 | ||
906 | /* for id and flush management per ring */ | |
907 | struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; | |
25cfc3c2 | 908 | |
81d75a30 | 909 | /* protecting freed */ |
910 | spinlock_t freed_lock; | |
2bd9ccfa CK |
911 | |
912 | /* Scheduler entity for page table updates */ | |
913 | struct amd_sched_entity entity; | |
97b2e202 AD |
914 | }; |
915 | ||
a9a78b32 CK |
916 | struct amdgpu_vm_manager_id { |
917 | struct list_head list; | |
918 | struct fence *active; | |
919 | atomic_long_t owner; | |
971fe9a9 CK |
920 | |
921 | uint32_t gds_base; | |
922 | uint32_t gds_size; | |
923 | uint32_t gws_base; | |
924 | uint32_t gws_size; | |
925 | uint32_t oa_base; | |
926 | uint32_t oa_size; | |
a9a78b32 CK |
927 | }; |
928 | ||
97b2e202 | 929 | struct amdgpu_vm_manager { |
a9a78b32 | 930 | /* Handling of VMIDs */ |
8d0a7cea | 931 | struct mutex lock; |
a9a78b32 CK |
932 | unsigned num_ids; |
933 | struct list_head ids_lru; | |
934 | struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM]; | |
1c16c0a7 | 935 | |
8b4fb00b | 936 | uint32_t max_pfn; |
97b2e202 | 937 | /* vram base address for page table entry */ |
8b4fb00b | 938 | u64 vram_base_offset; |
97b2e202 | 939 | /* is vm enabled? */ |
8b4fb00b | 940 | bool enabled; |
97b2e202 AD |
941 | /* vm pte handling */ |
942 | const struct amdgpu_vm_pte_funcs *vm_pte_funcs; | |
2d55e45a CK |
943 | struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; |
944 | unsigned vm_pte_num_rings; | |
945 | atomic_t vm_pte_next_ring; | |
97b2e202 AD |
946 | }; |
947 | ||
a9a78b32 | 948 | void amdgpu_vm_manager_init(struct amdgpu_device *adev); |
ea89f8c9 | 949 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev); |
8b4fb00b CK |
950 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
951 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); | |
56467ebf CK |
952 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
953 | struct list_head *validated, | |
954 | struct amdgpu_bo_list_entry *entry); | |
ee1782c3 | 955 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); |
eceb8a15 CK |
956 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, |
957 | struct amdgpu_vm *vm); | |
8b4fb00b | 958 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 CK |
959 | struct amdgpu_sync *sync, struct fence *fence, |
960 | unsigned *vm_id, uint64_t *vm_pd_addr); | |
8b4fb00b | 961 | void amdgpu_vm_flush(struct amdgpu_ring *ring, |
cffadc83 CK |
962 | unsigned vm_id, uint64_t pd_addr, |
963 | uint32_t gds_base, uint32_t gds_size, | |
964 | uint32_t gws_base, uint32_t gws_size, | |
965 | uint32_t oa_base, uint32_t oa_size); | |
971fe9a9 | 966 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); |
b07c9d2a | 967 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); |
8b4fb00b CK |
968 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, |
969 | struct amdgpu_vm *vm); | |
970 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
971 | struct amdgpu_vm *vm); | |
972 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
973 | struct amdgpu_sync *sync); | |
974 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
975 | struct amdgpu_bo_va *bo_va, | |
976 | struct ttm_mem_reg *mem); | |
977 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
978 | struct amdgpu_bo *bo); | |
979 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
980 | struct amdgpu_bo *bo); | |
981 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
982 | struct amdgpu_vm *vm, | |
983 | struct amdgpu_bo *bo); | |
984 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
985 | struct amdgpu_bo_va *bo_va, | |
986 | uint64_t addr, uint64_t offset, | |
987 | uint64_t size, uint32_t flags); | |
988 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
989 | struct amdgpu_bo_va *bo_va, | |
990 | uint64_t addr); | |
991 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
992 | struct amdgpu_bo_va *bo_va); | |
8b4fb00b | 993 | |
97b2e202 AD |
994 | /* |
995 | * context related structures | |
996 | */ | |
997 | ||
21c16bf6 | 998 | struct amdgpu_ctx_ring { |
91404fb2 | 999 | uint64_t sequence; |
37cd0ca2 | 1000 | struct fence **fences; |
91404fb2 | 1001 | struct amd_sched_entity entity; |
21c16bf6 CK |
1002 | }; |
1003 | ||
97b2e202 | 1004 | struct amdgpu_ctx { |
0b492a4c | 1005 | struct kref refcount; |
9cb7e5a9 | 1006 | struct amdgpu_device *adev; |
0b492a4c | 1007 | unsigned reset_counter; |
21c16bf6 | 1008 | spinlock_t ring_lock; |
37cd0ca2 | 1009 | struct fence **fences; |
21c16bf6 | 1010 | struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; |
97b2e202 AD |
1011 | }; |
1012 | ||
1013 | struct amdgpu_ctx_mgr { | |
0b492a4c AD |
1014 | struct amdgpu_device *adev; |
1015 | struct mutex lock; | |
1016 | /* protected by lock */ | |
1017 | struct idr ctx_handles; | |
97b2e202 AD |
1018 | }; |
1019 | ||
0b492a4c AD |
1020 | struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); |
1021 | int amdgpu_ctx_put(struct amdgpu_ctx *ctx); | |
1022 | ||
21c16bf6 | 1023 | uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, |
ce882e6d | 1024 | struct fence *fence); |
21c16bf6 CK |
1025 | struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, |
1026 | struct amdgpu_ring *ring, uint64_t seq); | |
1027 | ||
0b492a4c AD |
1028 | int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, |
1029 | struct drm_file *filp); | |
1030 | ||
efd4ccb5 CK |
1031 | void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); |
1032 | void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); | |
0b492a4c | 1033 | |
97b2e202 AD |
1034 | /* |
1035 | * file private structure | |
1036 | */ | |
1037 | ||
1038 | struct amdgpu_fpriv { | |
1039 | struct amdgpu_vm vm; | |
1040 | struct mutex bo_list_lock; | |
1041 | struct idr bo_list_handles; | |
0b492a4c | 1042 | struct amdgpu_ctx_mgr ctx_mgr; |
97b2e202 AD |
1043 | }; |
1044 | ||
1045 | /* | |
1046 | * residency list | |
1047 | */ | |
1048 | ||
1049 | struct amdgpu_bo_list { | |
1050 | struct mutex lock; | |
1051 | struct amdgpu_bo *gds_obj; | |
1052 | struct amdgpu_bo *gws_obj; | |
1053 | struct amdgpu_bo *oa_obj; | |
211dff55 | 1054 | unsigned first_userptr; |
97b2e202 AD |
1055 | unsigned num_entries; |
1056 | struct amdgpu_bo_list_entry *array; | |
1057 | }; | |
1058 | ||
1059 | struct amdgpu_bo_list * | |
1060 | amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); | |
636ce25c CK |
1061 | void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, |
1062 | struct list_head *validated); | |
97b2e202 AD |
1063 | void amdgpu_bo_list_put(struct amdgpu_bo_list *list); |
1064 | void amdgpu_bo_list_free(struct amdgpu_bo_list *list); | |
1065 | ||
1066 | /* | |
1067 | * GFX stuff | |
1068 | */ | |
1069 | #include "clearstate_defs.h" | |
1070 | ||
1071 | struct amdgpu_rlc { | |
1072 | /* for power gating */ | |
1073 | struct amdgpu_bo *save_restore_obj; | |
1074 | uint64_t save_restore_gpu_addr; | |
1075 | volatile uint32_t *sr_ptr; | |
1076 | const u32 *reg_list; | |
1077 | u32 reg_list_size; | |
1078 | /* for clear state */ | |
1079 | struct amdgpu_bo *clear_state_obj; | |
1080 | uint64_t clear_state_gpu_addr; | |
1081 | volatile uint32_t *cs_ptr; | |
1082 | const struct cs_section_def *cs_data; | |
1083 | u32 clear_state_size; | |
1084 | /* for cp tables */ | |
1085 | struct amdgpu_bo *cp_table_obj; | |
1086 | uint64_t cp_table_gpu_addr; | |
1087 | volatile uint32_t *cp_table_ptr; | |
1088 | u32 cp_table_size; | |
1089 | }; | |
1090 | ||
1091 | struct amdgpu_mec { | |
1092 | struct amdgpu_bo *hpd_eop_obj; | |
1093 | u64 hpd_eop_gpu_addr; | |
1094 | u32 num_pipe; | |
1095 | u32 num_mec; | |
1096 | u32 num_queue; | |
1097 | }; | |
1098 | ||
1099 | /* | |
1100 | * GPU scratch registers structures, functions & helpers | |
1101 | */ | |
1102 | struct amdgpu_scratch { | |
1103 | unsigned num_reg; | |
1104 | uint32_t reg_base; | |
1105 | bool free[32]; | |
1106 | uint32_t reg[32]; | |
1107 | }; | |
1108 | ||
1109 | /* | |
1110 | * GFX configurations | |
1111 | */ | |
1112 | struct amdgpu_gca_config { | |
1113 | unsigned max_shader_engines; | |
1114 | unsigned max_tile_pipes; | |
1115 | unsigned max_cu_per_sh; | |
1116 | unsigned max_sh_per_se; | |
1117 | unsigned max_backends_per_se; | |
1118 | unsigned max_texture_channel_caches; | |
1119 | unsigned max_gprs; | |
1120 | unsigned max_gs_threads; | |
1121 | unsigned max_hw_contexts; | |
1122 | unsigned sc_prim_fifo_size_frontend; | |
1123 | unsigned sc_prim_fifo_size_backend; | |
1124 | unsigned sc_hiz_tile_fifo_size; | |
1125 | unsigned sc_earlyz_tile_fifo_size; | |
1126 | ||
1127 | unsigned num_tile_pipes; | |
1128 | unsigned backend_enable_mask; | |
1129 | unsigned mem_max_burst_length_bytes; | |
1130 | unsigned mem_row_size_in_kb; | |
1131 | unsigned shader_engine_tile_size; | |
1132 | unsigned num_gpus; | |
1133 | unsigned multi_gpu_tile_size; | |
1134 | unsigned mc_arb_ramcfg; | |
1135 | unsigned gb_addr_config; | |
8f8e00c1 | 1136 | unsigned num_rbs; |
97b2e202 AD |
1137 | |
1138 | uint32_t tile_mode_array[32]; | |
1139 | uint32_t macrotile_mode_array[16]; | |
1140 | }; | |
1141 | ||
1142 | struct amdgpu_gfx { | |
1143 | struct mutex gpu_clock_mutex; | |
1144 | struct amdgpu_gca_config config; | |
1145 | struct amdgpu_rlc rlc; | |
1146 | struct amdgpu_mec mec; | |
1147 | struct amdgpu_scratch scratch; | |
1148 | const struct firmware *me_fw; /* ME firmware */ | |
1149 | uint32_t me_fw_version; | |
1150 | const struct firmware *pfp_fw; /* PFP firmware */ | |
1151 | uint32_t pfp_fw_version; | |
1152 | const struct firmware *ce_fw; /* CE firmware */ | |
1153 | uint32_t ce_fw_version; | |
1154 | const struct firmware *rlc_fw; /* RLC firmware */ | |
1155 | uint32_t rlc_fw_version; | |
1156 | const struct firmware *mec_fw; /* MEC firmware */ | |
1157 | uint32_t mec_fw_version; | |
1158 | const struct firmware *mec2_fw; /* MEC2 firmware */ | |
1159 | uint32_t mec2_fw_version; | |
02558a00 KW |
1160 | uint32_t me_feature_version; |
1161 | uint32_t ce_feature_version; | |
1162 | uint32_t pfp_feature_version; | |
351643d7 JZ |
1163 | uint32_t rlc_feature_version; |
1164 | uint32_t mec_feature_version; | |
1165 | uint32_t mec2_feature_version; | |
97b2e202 AD |
1166 | struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; |
1167 | unsigned num_gfx_rings; | |
1168 | struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; | |
1169 | unsigned num_compute_rings; | |
1170 | struct amdgpu_irq_src eop_irq; | |
1171 | struct amdgpu_irq_src priv_reg_irq; | |
1172 | struct amdgpu_irq_src priv_inst_irq; | |
1173 | /* gfx status */ | |
1174 | uint32_t gfx_current_status; | |
a101a899 KW |
1175 | /* ce ram size*/ |
1176 | unsigned ce_ram_size; | |
97b2e202 AD |
1177 | }; |
1178 | ||
b07c60c0 | 1179 | int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
97b2e202 | 1180 | unsigned size, struct amdgpu_ib *ib); |
cc55c45d | 1181 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f); |
b07c60c0 | 1182 | int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, |
336d1f5e | 1183 | struct amdgpu_ib *ib, struct fence *last_vm_update, |
ec72b800 | 1184 | struct fence **f); |
97b2e202 AD |
1185 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); |
1186 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); | |
1187 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); | |
97b2e202 | 1188 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); |
edff0e28 | 1189 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); |
9e5d5309 | 1190 | void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); |
97b2e202 | 1191 | void amdgpu_ring_commit(struct amdgpu_ring *ring); |
97b2e202 | 1192 | void amdgpu_ring_undo(struct amdgpu_ring *ring); |
97b2e202 AD |
1193 | unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, |
1194 | uint32_t **data); | |
1195 | int amdgpu_ring_restore(struct amdgpu_ring *ring, | |
1196 | unsigned size, uint32_t *data); | |
1197 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |
1198 | unsigned ring_size, u32 nop, u32 align_mask, | |
1199 | struct amdgpu_irq_src *irq_src, unsigned irq_type, | |
1200 | enum amdgpu_ring_type ring_type); | |
1201 | void amdgpu_ring_fini(struct amdgpu_ring *ring); | |
1202 | ||
1203 | /* | |
1204 | * CS. | |
1205 | */ | |
1206 | struct amdgpu_cs_chunk { | |
1207 | uint32_t chunk_id; | |
1208 | uint32_t length_dw; | |
1209 | uint32_t *kdata; | |
97b2e202 AD |
1210 | }; |
1211 | ||
1212 | struct amdgpu_cs_parser { | |
1213 | struct amdgpu_device *adev; | |
1214 | struct drm_file *filp; | |
3cb485f3 | 1215 | struct amdgpu_ctx *ctx; |
c3cca41e | 1216 | |
97b2e202 AD |
1217 | /* chunks */ |
1218 | unsigned nchunks; | |
1219 | struct amdgpu_cs_chunk *chunks; | |
97b2e202 | 1220 | |
50838c8c CK |
1221 | /* scheduler job object */ |
1222 | struct amdgpu_job *job; | |
97b2e202 | 1223 | |
c3cca41e CK |
1224 | /* buffer objects */ |
1225 | struct ww_acquire_ctx ticket; | |
1226 | struct amdgpu_bo_list *bo_list; | |
1227 | struct amdgpu_bo_list_entry vm_pd; | |
1228 | struct list_head validated; | |
1229 | struct fence *fence; | |
1230 | uint64_t bytes_moved_threshold; | |
1231 | uint64_t bytes_moved; | |
97b2e202 AD |
1232 | |
1233 | /* user fence */ | |
91acbeb6 | 1234 | struct amdgpu_bo_list_entry uf_entry; |
97b2e202 AD |
1235 | }; |
1236 | ||
bb977d37 CZ |
1237 | struct amdgpu_job { |
1238 | struct amd_sched_job base; | |
1239 | struct amdgpu_device *adev; | |
b07c60c0 | 1240 | struct amdgpu_ring *ring; |
e86f9cee | 1241 | struct amdgpu_sync sync; |
bb977d37 CZ |
1242 | struct amdgpu_ib *ibs; |
1243 | uint32_t num_ibs; | |
e2840221 | 1244 | void *owner; |
bb977d37 | 1245 | struct amdgpu_user_fence uf; |
bb977d37 | 1246 | }; |
a6db8a33 JZ |
1247 | #define to_amdgpu_job(sched_job) \ |
1248 | container_of((sched_job), struct amdgpu_job, base) | |
bb977d37 | 1249 | |
7270f839 CK |
1250 | static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, |
1251 | uint32_t ib_idx, int idx) | |
97b2e202 | 1252 | { |
50838c8c | 1253 | return p->job->ibs[ib_idx].ptr[idx]; |
97b2e202 AD |
1254 | } |
1255 | ||
7270f839 CK |
1256 | static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, |
1257 | uint32_t ib_idx, int idx, | |
1258 | uint32_t value) | |
1259 | { | |
50838c8c | 1260 | p->job->ibs[ib_idx].ptr[idx] = value; |
7270f839 CK |
1261 | } |
1262 | ||
97b2e202 AD |
1263 | /* |
1264 | * Writeback | |
1265 | */ | |
1266 | #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ | |
1267 | ||
1268 | struct amdgpu_wb { | |
1269 | struct amdgpu_bo *wb_obj; | |
1270 | volatile uint32_t *wb; | |
1271 | uint64_t gpu_addr; | |
1272 | u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ | |
1273 | unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; | |
1274 | }; | |
1275 | ||
1276 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); | |
1277 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); | |
1278 | ||
97b2e202 | 1279 | |
97b2e202 AD |
1280 | |
1281 | enum amdgpu_int_thermal_type { | |
1282 | THERMAL_TYPE_NONE, | |
1283 | THERMAL_TYPE_EXTERNAL, | |
1284 | THERMAL_TYPE_EXTERNAL_GPIO, | |
1285 | THERMAL_TYPE_RV6XX, | |
1286 | THERMAL_TYPE_RV770, | |
1287 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, | |
1288 | THERMAL_TYPE_EVERGREEN, | |
1289 | THERMAL_TYPE_SUMO, | |
1290 | THERMAL_TYPE_NI, | |
1291 | THERMAL_TYPE_SI, | |
1292 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, | |
1293 | THERMAL_TYPE_CI, | |
1294 | THERMAL_TYPE_KV, | |
1295 | }; | |
1296 | ||
1297 | enum amdgpu_dpm_auto_throttle_src { | |
1298 | AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, | |
1299 | AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL | |
1300 | }; | |
1301 | ||
1302 | enum amdgpu_dpm_event_src { | |
1303 | AMDGPU_DPM_EVENT_SRC_ANALOG = 0, | |
1304 | AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, | |
1305 | AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, | |
1306 | AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, | |
1307 | AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 | |
1308 | }; | |
1309 | ||
1310 | #define AMDGPU_MAX_VCE_LEVELS 6 | |
1311 | ||
1312 | enum amdgpu_vce_level { | |
1313 | AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ | |
1314 | AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ | |
1315 | AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ | |
1316 | AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ | |
1317 | AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ | |
1318 | AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ | |
1319 | }; | |
1320 | ||
1321 | struct amdgpu_ps { | |
1322 | u32 caps; /* vbios flags */ | |
1323 | u32 class; /* vbios flags */ | |
1324 | u32 class2; /* vbios flags */ | |
1325 | /* UVD clocks */ | |
1326 | u32 vclk; | |
1327 | u32 dclk; | |
1328 | /* VCE clocks */ | |
1329 | u32 evclk; | |
1330 | u32 ecclk; | |
1331 | bool vce_active; | |
1332 | enum amdgpu_vce_level vce_level; | |
1333 | /* asic priv */ | |
1334 | void *ps_priv; | |
1335 | }; | |
1336 | ||
1337 | struct amdgpu_dpm_thermal { | |
1338 | /* thermal interrupt work */ | |
1339 | struct work_struct work; | |
1340 | /* low temperature threshold */ | |
1341 | int min_temp; | |
1342 | /* high temperature threshold */ | |
1343 | int max_temp; | |
1344 | /* was last interrupt low to high or high to low */ | |
1345 | bool high_to_low; | |
1346 | /* interrupt source */ | |
1347 | struct amdgpu_irq_src irq; | |
1348 | }; | |
1349 | ||
1350 | enum amdgpu_clk_action | |
1351 | { | |
1352 | AMDGPU_SCLK_UP = 1, | |
1353 | AMDGPU_SCLK_DOWN | |
1354 | }; | |
1355 | ||
1356 | struct amdgpu_blacklist_clocks | |
1357 | { | |
1358 | u32 sclk; | |
1359 | u32 mclk; | |
1360 | enum amdgpu_clk_action action; | |
1361 | }; | |
1362 | ||
1363 | struct amdgpu_clock_and_voltage_limits { | |
1364 | u32 sclk; | |
1365 | u32 mclk; | |
1366 | u16 vddc; | |
1367 | u16 vddci; | |
1368 | }; | |
1369 | ||
1370 | struct amdgpu_clock_array { | |
1371 | u32 count; | |
1372 | u32 *values; | |
1373 | }; | |
1374 | ||
1375 | struct amdgpu_clock_voltage_dependency_entry { | |
1376 | u32 clk; | |
1377 | u16 v; | |
1378 | }; | |
1379 | ||
1380 | struct amdgpu_clock_voltage_dependency_table { | |
1381 | u32 count; | |
1382 | struct amdgpu_clock_voltage_dependency_entry *entries; | |
1383 | }; | |
1384 | ||
1385 | union amdgpu_cac_leakage_entry { | |
1386 | struct { | |
1387 | u16 vddc; | |
1388 | u32 leakage; | |
1389 | }; | |
1390 | struct { | |
1391 | u16 vddc1; | |
1392 | u16 vddc2; | |
1393 | u16 vddc3; | |
1394 | }; | |
1395 | }; | |
1396 | ||
1397 | struct amdgpu_cac_leakage_table { | |
1398 | u32 count; | |
1399 | union amdgpu_cac_leakage_entry *entries; | |
1400 | }; | |
1401 | ||
1402 | struct amdgpu_phase_shedding_limits_entry { | |
1403 | u16 voltage; | |
1404 | u32 sclk; | |
1405 | u32 mclk; | |
1406 | }; | |
1407 | ||
1408 | struct amdgpu_phase_shedding_limits_table { | |
1409 | u32 count; | |
1410 | struct amdgpu_phase_shedding_limits_entry *entries; | |
1411 | }; | |
1412 | ||
1413 | struct amdgpu_uvd_clock_voltage_dependency_entry { | |
1414 | u32 vclk; | |
1415 | u32 dclk; | |
1416 | u16 v; | |
1417 | }; | |
1418 | ||
1419 | struct amdgpu_uvd_clock_voltage_dependency_table { | |
1420 | u8 count; | |
1421 | struct amdgpu_uvd_clock_voltage_dependency_entry *entries; | |
1422 | }; | |
1423 | ||
1424 | struct amdgpu_vce_clock_voltage_dependency_entry { | |
1425 | u32 ecclk; | |
1426 | u32 evclk; | |
1427 | u16 v; | |
1428 | }; | |
1429 | ||
1430 | struct amdgpu_vce_clock_voltage_dependency_table { | |
1431 | u8 count; | |
1432 | struct amdgpu_vce_clock_voltage_dependency_entry *entries; | |
1433 | }; | |
1434 | ||
1435 | struct amdgpu_ppm_table { | |
1436 | u8 ppm_design; | |
1437 | u16 cpu_core_number; | |
1438 | u32 platform_tdp; | |
1439 | u32 small_ac_platform_tdp; | |
1440 | u32 platform_tdc; | |
1441 | u32 small_ac_platform_tdc; | |
1442 | u32 apu_tdp; | |
1443 | u32 dgpu_tdp; | |
1444 | u32 dgpu_ulv_power; | |
1445 | u32 tj_max; | |
1446 | }; | |
1447 | ||
1448 | struct amdgpu_cac_tdp_table { | |
1449 | u16 tdp; | |
1450 | u16 configurable_tdp; | |
1451 | u16 tdc; | |
1452 | u16 battery_power_limit; | |
1453 | u16 small_power_limit; | |
1454 | u16 low_cac_leakage; | |
1455 | u16 high_cac_leakage; | |
1456 | u16 maximum_power_delivery_limit; | |
1457 | }; | |
1458 | ||
1459 | struct amdgpu_dpm_dynamic_state { | |
1460 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; | |
1461 | struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; | |
1462 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; | |
1463 | struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; | |
1464 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; | |
1465 | struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; | |
1466 | struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; | |
1467 | struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; | |
1468 | struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; | |
1469 | struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; | |
1470 | struct amdgpu_clock_array valid_sclk_values; | |
1471 | struct amdgpu_clock_array valid_mclk_values; | |
1472 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; | |
1473 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; | |
1474 | u32 mclk_sclk_ratio; | |
1475 | u32 sclk_mclk_delta; | |
1476 | u16 vddc_vddci_delta; | |
1477 | u16 min_vddc_for_pcie_gen2; | |
1478 | struct amdgpu_cac_leakage_table cac_leakage_table; | |
1479 | struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; | |
1480 | struct amdgpu_ppm_table *ppm_table; | |
1481 | struct amdgpu_cac_tdp_table *cac_tdp_table; | |
1482 | }; | |
1483 | ||
1484 | struct amdgpu_dpm_fan { | |
1485 | u16 t_min; | |
1486 | u16 t_med; | |
1487 | u16 t_high; | |
1488 | u16 pwm_min; | |
1489 | u16 pwm_med; | |
1490 | u16 pwm_high; | |
1491 | u8 t_hyst; | |
1492 | u32 cycle_delay; | |
1493 | u16 t_max; | |
1494 | u8 control_mode; | |
1495 | u16 default_max_fan_pwm; | |
1496 | u16 default_fan_output_sensitivity; | |
1497 | u16 fan_output_sensitivity; | |
1498 | bool ucode_fan_control; | |
1499 | }; | |
1500 | ||
1501 | enum amdgpu_pcie_gen { | |
1502 | AMDGPU_PCIE_GEN1 = 0, | |
1503 | AMDGPU_PCIE_GEN2 = 1, | |
1504 | AMDGPU_PCIE_GEN3 = 2, | |
1505 | AMDGPU_PCIE_GEN_INVALID = 0xffff | |
1506 | }; | |
1507 | ||
1508 | enum amdgpu_dpm_forced_level { | |
1509 | AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, | |
1510 | AMDGPU_DPM_FORCED_LEVEL_LOW = 1, | |
1511 | AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, | |
f3898ea1 | 1512 | AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, |
97b2e202 AD |
1513 | }; |
1514 | ||
1515 | struct amdgpu_vce_state { | |
1516 | /* vce clocks */ | |
1517 | u32 evclk; | |
1518 | u32 ecclk; | |
1519 | /* gpu clocks */ | |
1520 | u32 sclk; | |
1521 | u32 mclk; | |
1522 | u8 clk_idx; | |
1523 | u8 pstate; | |
1524 | }; | |
1525 | ||
1526 | struct amdgpu_dpm_funcs { | |
1527 | int (*get_temperature)(struct amdgpu_device *adev); | |
1528 | int (*pre_set_power_state)(struct amdgpu_device *adev); | |
1529 | int (*set_power_state)(struct amdgpu_device *adev); | |
1530 | void (*post_set_power_state)(struct amdgpu_device *adev); | |
1531 | void (*display_configuration_changed)(struct amdgpu_device *adev); | |
1532 | u32 (*get_sclk)(struct amdgpu_device *adev, bool low); | |
1533 | u32 (*get_mclk)(struct amdgpu_device *adev, bool low); | |
1534 | void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); | |
1535 | void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); | |
1536 | int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); | |
1537 | bool (*vblank_too_short)(struct amdgpu_device *adev); | |
1538 | void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); | |
b7a07769 | 1539 | void (*powergate_vce)(struct amdgpu_device *adev, bool gate); |
97b2e202 AD |
1540 | void (*enable_bapm)(struct amdgpu_device *adev, bool enable); |
1541 | void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); | |
1542 | u32 (*get_fan_control_mode)(struct amdgpu_device *adev); | |
1543 | int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); | |
1544 | int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); | |
1545 | }; | |
1546 | ||
1547 | struct amdgpu_dpm { | |
1548 | struct amdgpu_ps *ps; | |
1549 | /* number of valid power states */ | |
1550 | int num_ps; | |
1551 | /* current power state that is active */ | |
1552 | struct amdgpu_ps *current_ps; | |
1553 | /* requested power state */ | |
1554 | struct amdgpu_ps *requested_ps; | |
1555 | /* boot up power state */ | |
1556 | struct amdgpu_ps *boot_ps; | |
1557 | /* default uvd power state */ | |
1558 | struct amdgpu_ps *uvd_ps; | |
1559 | /* vce requirements */ | |
1560 | struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; | |
1561 | enum amdgpu_vce_level vce_level; | |
3a2c788d RZ |
1562 | enum amd_pm_state_type state; |
1563 | enum amd_pm_state_type user_state; | |
97b2e202 AD |
1564 | u32 platform_caps; |
1565 | u32 voltage_response_time; | |
1566 | u32 backbias_response_time; | |
1567 | void *priv; | |
1568 | u32 new_active_crtcs; | |
1569 | int new_active_crtc_count; | |
1570 | u32 current_active_crtcs; | |
1571 | int current_active_crtc_count; | |
1572 | struct amdgpu_dpm_dynamic_state dyn_state; | |
1573 | struct amdgpu_dpm_fan fan; | |
1574 | u32 tdp_limit; | |
1575 | u32 near_tdp_limit; | |
1576 | u32 near_tdp_limit_adjusted; | |
1577 | u32 sq_ramping_threshold; | |
1578 | u32 cac_leakage; | |
1579 | u16 tdp_od_limit; | |
1580 | u32 tdp_adjustment; | |
1581 | u16 load_line_slope; | |
1582 | bool power_control; | |
1583 | bool ac_power; | |
1584 | /* special states active */ | |
1585 | bool thermal_active; | |
1586 | bool uvd_active; | |
1587 | bool vce_active; | |
1588 | /* thermal handling */ | |
1589 | struct amdgpu_dpm_thermal thermal; | |
1590 | /* forced levels */ | |
1591 | enum amdgpu_dpm_forced_level forced_level; | |
1592 | }; | |
1593 | ||
1594 | struct amdgpu_pm { | |
1595 | struct mutex mutex; | |
97b2e202 AD |
1596 | u32 current_sclk; |
1597 | u32 current_mclk; | |
1598 | u32 default_sclk; | |
1599 | u32 default_mclk; | |
1600 | struct amdgpu_i2c_chan *i2c_bus; | |
1601 | /* internal thermal controller on rv6xx+ */ | |
1602 | enum amdgpu_int_thermal_type int_thermal_type; | |
1603 | struct device *int_hwmon_dev; | |
1604 | /* fan control parameters */ | |
1605 | bool no_fan; | |
1606 | u8 fan_pulses_per_revolution; | |
1607 | u8 fan_min_rpm; | |
1608 | u8 fan_max_rpm; | |
1609 | /* dpm */ | |
1610 | bool dpm_enabled; | |
c86f5ebf | 1611 | bool sysfs_initialized; |
97b2e202 AD |
1612 | struct amdgpu_dpm dpm; |
1613 | const struct firmware *fw; /* SMC firmware */ | |
1614 | uint32_t fw_version; | |
1615 | const struct amdgpu_dpm_funcs *funcs; | |
d0dd7f0c AD |
1616 | uint32_t pcie_gen_mask; |
1617 | uint32_t pcie_mlw_mask; | |
7fb72a1f | 1618 | struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ |
97b2e202 AD |
1619 | }; |
1620 | ||
d0dd7f0c AD |
1621 | void amdgpu_get_pcie_info(struct amdgpu_device *adev); |
1622 | ||
97b2e202 AD |
1623 | /* |
1624 | * UVD | |
1625 | */ | |
1626 | #define AMDGPU_MAX_UVD_HANDLES 10 | |
1627 | #define AMDGPU_UVD_STACK_SIZE (1024*1024) | |
1628 | #define AMDGPU_UVD_HEAP_SIZE (1024*1024) | |
1629 | #define AMDGPU_UVD_FIRMWARE_OFFSET 256 | |
1630 | ||
1631 | struct amdgpu_uvd { | |
1632 | struct amdgpu_bo *vcpu_bo; | |
1633 | void *cpu_addr; | |
1634 | uint64_t gpu_addr; | |
97b2e202 AD |
1635 | atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; |
1636 | struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; | |
1637 | struct delayed_work idle_work; | |
1638 | const struct firmware *fw; /* UVD firmware */ | |
1639 | struct amdgpu_ring ring; | |
1640 | struct amdgpu_irq_src irq; | |
1641 | bool address_64_bit; | |
ead833ec | 1642 | struct amd_sched_entity entity; |
97b2e202 AD |
1643 | }; |
1644 | ||
1645 | /* | |
1646 | * VCE | |
1647 | */ | |
1648 | #define AMDGPU_MAX_VCE_HANDLES 16 | |
97b2e202 AD |
1649 | #define AMDGPU_VCE_FIRMWARE_OFFSET 256 |
1650 | ||
6a585777 AD |
1651 | #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) |
1652 | #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) | |
1653 | ||
97b2e202 AD |
1654 | struct amdgpu_vce { |
1655 | struct amdgpu_bo *vcpu_bo; | |
1656 | uint64_t gpu_addr; | |
1657 | unsigned fw_version; | |
1658 | unsigned fb_version; | |
1659 | atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; | |
1660 | struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; | |
f1689ec1 | 1661 | uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; |
97b2e202 AD |
1662 | struct delayed_work idle_work; |
1663 | const struct firmware *fw; /* VCE firmware */ | |
1664 | struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; | |
1665 | struct amdgpu_irq_src irq; | |
6a585777 | 1666 | unsigned harvest_config; |
c594989c | 1667 | struct amd_sched_entity entity; |
97b2e202 AD |
1668 | }; |
1669 | ||
1670 | /* | |
1671 | * SDMA | |
1672 | */ | |
c113ea1c | 1673 | struct amdgpu_sdma_instance { |
97b2e202 AD |
1674 | /* SDMA firmware */ |
1675 | const struct firmware *fw; | |
1676 | uint32_t fw_version; | |
cfa2104f | 1677 | uint32_t feature_version; |
97b2e202 AD |
1678 | |
1679 | struct amdgpu_ring ring; | |
18111de0 | 1680 | bool burst_nop; |
97b2e202 AD |
1681 | }; |
1682 | ||
c113ea1c AD |
1683 | struct amdgpu_sdma { |
1684 | struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; | |
1685 | struct amdgpu_irq_src trap_irq; | |
1686 | struct amdgpu_irq_src illegal_inst_irq; | |
1687 | int num_instances; | |
1688 | }; | |
1689 | ||
97b2e202 AD |
1690 | /* |
1691 | * Firmware | |
1692 | */ | |
1693 | struct amdgpu_firmware { | |
1694 | struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; | |
1695 | bool smu_load; | |
1696 | struct amdgpu_bo *fw_buf; | |
1697 | unsigned int fw_size; | |
1698 | }; | |
1699 | ||
1700 | /* | |
1701 | * Benchmarking | |
1702 | */ | |
1703 | void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); | |
1704 | ||
1705 | ||
1706 | /* | |
1707 | * Testing | |
1708 | */ | |
1709 | void amdgpu_test_moves(struct amdgpu_device *adev); | |
1710 | void amdgpu_test_ring_sync(struct amdgpu_device *adev, | |
1711 | struct amdgpu_ring *cpA, | |
1712 | struct amdgpu_ring *cpB); | |
1713 | void amdgpu_test_syncing(struct amdgpu_device *adev); | |
1714 | ||
1715 | /* | |
1716 | * MMU Notifier | |
1717 | */ | |
1718 | #if defined(CONFIG_MMU_NOTIFIER) | |
1719 | int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); | |
1720 | void amdgpu_mn_unregister(struct amdgpu_bo *bo); | |
1721 | #else | |
1d1106b0 | 1722 | static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) |
97b2e202 AD |
1723 | { |
1724 | return -ENODEV; | |
1725 | } | |
1d1106b0 | 1726 | static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} |
97b2e202 AD |
1727 | #endif |
1728 | ||
1729 | /* | |
1730 | * Debugfs | |
1731 | */ | |
1732 | struct amdgpu_debugfs { | |
1733 | struct drm_info_list *files; | |
1734 | unsigned num_files; | |
1735 | }; | |
1736 | ||
1737 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
1738 | struct drm_info_list *files, | |
1739 | unsigned nfiles); | |
1740 | int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); | |
1741 | ||
1742 | #if defined(CONFIG_DEBUG_FS) | |
1743 | int amdgpu_debugfs_init(struct drm_minor *minor); | |
1744 | void amdgpu_debugfs_cleanup(struct drm_minor *minor); | |
1745 | #endif | |
1746 | ||
1747 | /* | |
1748 | * amdgpu smumgr functions | |
1749 | */ | |
1750 | struct amdgpu_smumgr_funcs { | |
1751 | int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); | |
1752 | int (*request_smu_load_fw)(struct amdgpu_device *adev); | |
1753 | int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); | |
1754 | }; | |
1755 | ||
1756 | /* | |
1757 | * amdgpu smumgr | |
1758 | */ | |
1759 | struct amdgpu_smumgr { | |
1760 | struct amdgpu_bo *toc_buf; | |
1761 | struct amdgpu_bo *smu_buf; | |
1762 | /* asic priv smu data */ | |
1763 | void *priv; | |
1764 | spinlock_t smu_lock; | |
1765 | /* smumgr functions */ | |
1766 | const struct amdgpu_smumgr_funcs *smumgr_funcs; | |
1767 | /* ucode loading complete flag */ | |
1768 | uint32_t fw_flags; | |
1769 | }; | |
1770 | ||
1771 | /* | |
1772 | * ASIC specific register table accessible by UMD | |
1773 | */ | |
1774 | struct amdgpu_allowed_register_entry { | |
1775 | uint32_t reg_offset; | |
1776 | bool untouched; | |
1777 | bool grbm_indexed; | |
1778 | }; | |
1779 | ||
1780 | struct amdgpu_cu_info { | |
1781 | uint32_t number; /* total active CU number */ | |
1782 | uint32_t ao_cu_mask; | |
1783 | uint32_t bitmap[4][4]; | |
1784 | }; | |
1785 | ||
1786 | ||
1787 | /* | |
1788 | * ASIC specific functions. | |
1789 | */ | |
1790 | struct amdgpu_asic_funcs { | |
1791 | bool (*read_disabled_bios)(struct amdgpu_device *adev); | |
7946b878 AD |
1792 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, |
1793 | u8 *bios, u32 length_bytes); | |
97b2e202 AD |
1794 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, |
1795 | u32 sh_num, u32 reg_offset, u32 *value); | |
1796 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); | |
1797 | int (*reset)(struct amdgpu_device *adev); | |
1798 | /* wait for mc_idle */ | |
1799 | int (*wait_for_mc_idle)(struct amdgpu_device *adev); | |
1800 | /* get the reference clock */ | |
1801 | u32 (*get_xclk)(struct amdgpu_device *adev); | |
1802 | /* get the gpu clock counter */ | |
1803 | uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); | |
1804 | int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); | |
1805 | /* MM block clocks */ | |
1806 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); | |
1807 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); | |
1808 | }; | |
1809 | ||
1810 | /* | |
1811 | * IOCTL. | |
1812 | */ | |
1813 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
1814 | struct drm_file *filp); | |
1815 | int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, | |
1816 | struct drm_file *filp); | |
1817 | ||
1818 | int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, | |
1819 | struct drm_file *filp); | |
1820 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
1821 | struct drm_file *filp); | |
1822 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1823 | struct drm_file *filp); | |
1824 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1825 | struct drm_file *filp); | |
1826 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, | |
1827 | struct drm_file *filp); | |
1828 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
1829 | struct drm_file *filp); | |
1830 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
1831 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
1832 | ||
1833 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
1834 | struct drm_file *filp); | |
1835 | ||
1836 | /* VRAM scratch page for HDP bug, default vram page */ | |
1837 | struct amdgpu_vram_scratch { | |
1838 | struct amdgpu_bo *robj; | |
1839 | volatile uint32_t *ptr; | |
1840 | u64 gpu_addr; | |
1841 | }; | |
1842 | ||
1843 | /* | |
1844 | * ACPI | |
1845 | */ | |
1846 | struct amdgpu_atif_notification_cfg { | |
1847 | bool enabled; | |
1848 | int command_code; | |
1849 | }; | |
1850 | ||
1851 | struct amdgpu_atif_notifications { | |
1852 | bool display_switch; | |
1853 | bool expansion_mode_change; | |
1854 | bool thermal_state; | |
1855 | bool forced_power_state; | |
1856 | bool system_power_state; | |
1857 | bool display_conf_change; | |
1858 | bool px_gfx_switch; | |
1859 | bool brightness_change; | |
1860 | bool dgpu_display_event; | |
1861 | }; | |
1862 | ||
1863 | struct amdgpu_atif_functions { | |
1864 | bool system_params; | |
1865 | bool sbios_requests; | |
1866 | bool select_active_disp; | |
1867 | bool lid_state; | |
1868 | bool get_tv_standard; | |
1869 | bool set_tv_standard; | |
1870 | bool get_panel_expansion_mode; | |
1871 | bool set_panel_expansion_mode; | |
1872 | bool temperature_change; | |
1873 | bool graphics_device_types; | |
1874 | }; | |
1875 | ||
1876 | struct amdgpu_atif { | |
1877 | struct amdgpu_atif_notifications notifications; | |
1878 | struct amdgpu_atif_functions functions; | |
1879 | struct amdgpu_atif_notification_cfg notification_cfg; | |
1880 | struct amdgpu_encoder *encoder_for_bl; | |
1881 | }; | |
1882 | ||
1883 | struct amdgpu_atcs_functions { | |
1884 | bool get_ext_state; | |
1885 | bool pcie_perf_req; | |
1886 | bool pcie_dev_rdy; | |
1887 | bool pcie_bus_width; | |
1888 | }; | |
1889 | ||
1890 | struct amdgpu_atcs { | |
1891 | struct amdgpu_atcs_functions functions; | |
1892 | }; | |
1893 | ||
d03846af CZ |
1894 | /* |
1895 | * CGS | |
1896 | */ | |
1897 | void *amdgpu_cgs_create_device(struct amdgpu_device *adev); | |
1898 | void amdgpu_cgs_destroy_device(void *cgs_device); | |
1899 | ||
1900 | ||
a8fe58ce MB |
1901 | /* |
1902 | * CGS | |
1903 | */ | |
1904 | void *amdgpu_cgs_create_device(struct amdgpu_device *adev); | |
1905 | void amdgpu_cgs_destroy_device(void *cgs_device); | |
1906 | ||
1907 | ||
7e471e6f AD |
1908 | /* GPU virtualization */ |
1909 | struct amdgpu_virtualization { | |
1910 | bool supports_sr_iov; | |
1911 | }; | |
1912 | ||
97b2e202 AD |
1913 | /* |
1914 | * Core structure, functions and helpers. | |
1915 | */ | |
1916 | typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); | |
1917 | typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1918 | ||
1919 | typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1920 | typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); | |
1921 | ||
8faf0e08 AD |
1922 | struct amdgpu_ip_block_status { |
1923 | bool valid; | |
1924 | bool sw; | |
1925 | bool hw; | |
1926 | }; | |
1927 | ||
97b2e202 AD |
1928 | struct amdgpu_device { |
1929 | struct device *dev; | |
1930 | struct drm_device *ddev; | |
1931 | struct pci_dev *pdev; | |
97b2e202 | 1932 | |
a8fe58ce MB |
1933 | #ifdef CONFIG_DRM_AMD_ACP |
1934 | struct amdgpu_acp acp; | |
1935 | #endif | |
1936 | ||
97b2e202 | 1937 | /* ASIC */ |
2f7d10b3 | 1938 | enum amd_asic_type asic_type; |
97b2e202 AD |
1939 | uint32_t family; |
1940 | uint32_t rev_id; | |
1941 | uint32_t external_rev_id; | |
1942 | unsigned long flags; | |
1943 | int usec_timeout; | |
1944 | const struct amdgpu_asic_funcs *asic_funcs; | |
1945 | bool shutdown; | |
1946 | bool suspend; | |
1947 | bool need_dma32; | |
1948 | bool accel_working; | |
97b2e202 AD |
1949 | struct work_struct reset_work; |
1950 | struct notifier_block acpi_nb; | |
1951 | struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; | |
1952 | struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; | |
1953 | unsigned debugfs_count; | |
1954 | #if defined(CONFIG_DEBUG_FS) | |
1955 | struct dentry *debugfs_regs; | |
1956 | #endif | |
1957 | struct amdgpu_atif atif; | |
1958 | struct amdgpu_atcs atcs; | |
1959 | struct mutex srbm_mutex; | |
1960 | /* GRBM index mutex. Protects concurrent access to GRBM index */ | |
1961 | struct mutex grbm_idx_mutex; | |
1962 | struct dev_pm_domain vga_pm_domain; | |
1963 | bool have_disp_power_ref; | |
1964 | ||
1965 | /* BIOS */ | |
1966 | uint8_t *bios; | |
1967 | bool is_atom_bios; | |
1968 | uint16_t bios_header_start; | |
1969 | struct amdgpu_bo *stollen_vga_memory; | |
1970 | uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; | |
1971 | ||
1972 | /* Register/doorbell mmio */ | |
1973 | resource_size_t rmmio_base; | |
1974 | resource_size_t rmmio_size; | |
1975 | void __iomem *rmmio; | |
1976 | /* protects concurrent MM_INDEX/DATA based register access */ | |
1977 | spinlock_t mmio_idx_lock; | |
1978 | /* protects concurrent SMC based register access */ | |
1979 | spinlock_t smc_idx_lock; | |
1980 | amdgpu_rreg_t smc_rreg; | |
1981 | amdgpu_wreg_t smc_wreg; | |
1982 | /* protects concurrent PCIE register access */ | |
1983 | spinlock_t pcie_idx_lock; | |
1984 | amdgpu_rreg_t pcie_rreg; | |
1985 | amdgpu_wreg_t pcie_wreg; | |
1986 | /* protects concurrent UVD register access */ | |
1987 | spinlock_t uvd_ctx_idx_lock; | |
1988 | amdgpu_rreg_t uvd_ctx_rreg; | |
1989 | amdgpu_wreg_t uvd_ctx_wreg; | |
1990 | /* protects concurrent DIDT register access */ | |
1991 | spinlock_t didt_idx_lock; | |
1992 | amdgpu_rreg_t didt_rreg; | |
1993 | amdgpu_wreg_t didt_wreg; | |
1994 | /* protects concurrent ENDPOINT (audio) register access */ | |
1995 | spinlock_t audio_endpt_idx_lock; | |
1996 | amdgpu_block_rreg_t audio_endpt_rreg; | |
1997 | amdgpu_block_wreg_t audio_endpt_wreg; | |
1998 | void __iomem *rio_mem; | |
1999 | resource_size_t rio_mem_size; | |
2000 | struct amdgpu_doorbell doorbell; | |
2001 | ||
2002 | /* clock/pll info */ | |
2003 | struct amdgpu_clock clock; | |
2004 | ||
2005 | /* MC */ | |
2006 | struct amdgpu_mc mc; | |
2007 | struct amdgpu_gart gart; | |
2008 | struct amdgpu_dummy_page dummy_page; | |
2009 | struct amdgpu_vm_manager vm_manager; | |
2010 | ||
2011 | /* memory management */ | |
2012 | struct amdgpu_mman mman; | |
97b2e202 AD |
2013 | struct amdgpu_vram_scratch vram_scratch; |
2014 | struct amdgpu_wb wb; | |
2015 | atomic64_t vram_usage; | |
2016 | atomic64_t vram_vis_usage; | |
2017 | atomic64_t gtt_usage; | |
2018 | atomic64_t num_bytes_moved; | |
d94aed5a | 2019 | atomic_t gpu_reset_counter; |
97b2e202 AD |
2020 | |
2021 | /* display */ | |
2022 | struct amdgpu_mode_info mode_info; | |
2023 | struct work_struct hotplug_work; | |
2024 | struct amdgpu_irq_src crtc_irq; | |
2025 | struct amdgpu_irq_src pageflip_irq; | |
2026 | struct amdgpu_irq_src hpd_irq; | |
2027 | ||
2028 | /* rings */ | |
97b2e202 | 2029 | unsigned fence_context; |
97b2e202 AD |
2030 | unsigned num_rings; |
2031 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; | |
2032 | bool ib_pool_ready; | |
2033 | struct amdgpu_sa_manager ring_tmp_bo; | |
2034 | ||
2035 | /* interrupts */ | |
2036 | struct amdgpu_irq irq; | |
2037 | ||
1f7371b2 AD |
2038 | /* powerplay */ |
2039 | struct amd_powerplay powerplay; | |
e61710c5 | 2040 | bool pp_enabled; |
f3898ea1 | 2041 | bool pp_force_state_enabled; |
1f7371b2 | 2042 | |
97b2e202 AD |
2043 | /* dpm */ |
2044 | struct amdgpu_pm pm; | |
2045 | u32 cg_flags; | |
2046 | u32 pg_flags; | |
2047 | ||
2048 | /* amdgpu smumgr */ | |
2049 | struct amdgpu_smumgr smu; | |
2050 | ||
2051 | /* gfx */ | |
2052 | struct amdgpu_gfx gfx; | |
2053 | ||
2054 | /* sdma */ | |
c113ea1c | 2055 | struct amdgpu_sdma sdma; |
97b2e202 AD |
2056 | |
2057 | /* uvd */ | |
97b2e202 AD |
2058 | struct amdgpu_uvd uvd; |
2059 | ||
2060 | /* vce */ | |
2061 | struct amdgpu_vce vce; | |
2062 | ||
2063 | /* firmwares */ | |
2064 | struct amdgpu_firmware firmware; | |
2065 | ||
2066 | /* GDS */ | |
2067 | struct amdgpu_gds gds; | |
2068 | ||
2069 | const struct amdgpu_ip_block_version *ip_blocks; | |
2070 | int num_ip_blocks; | |
8faf0e08 | 2071 | struct amdgpu_ip_block_status *ip_block_status; |
97b2e202 AD |
2072 | struct mutex mn_lock; |
2073 | DECLARE_HASHTABLE(mn_hash, 7); | |
2074 | ||
2075 | /* tracking pinned memory */ | |
2076 | u64 vram_pin_size; | |
2077 | u64 gart_pin_size; | |
130e0371 OG |
2078 | |
2079 | /* amdkfd interface */ | |
2080 | struct kfd_dev *kfd; | |
23ca0e4e | 2081 | |
7e471e6f | 2082 | struct amdgpu_virtualization virtualization; |
97b2e202 AD |
2083 | }; |
2084 | ||
2085 | bool amdgpu_device_is_px(struct drm_device *dev); | |
2086 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2087 | struct drm_device *ddev, | |
2088 | struct pci_dev *pdev, | |
2089 | uint32_t flags); | |
2090 | void amdgpu_device_fini(struct amdgpu_device *adev); | |
2091 | int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); | |
2092 | ||
2093 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
2094 | bool always_indirect); | |
2095 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
2096 | bool always_indirect); | |
2097 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); | |
2098 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); | |
2099 | ||
2100 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); | |
2101 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); | |
2102 | ||
97b2e202 AD |
2103 | /* |
2104 | * Registers read & write functions. | |
2105 | */ | |
2106 | #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) | |
2107 | #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) | |
2108 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) | |
2109 | #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) | |
2110 | #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) | |
2111 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
2112 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
2113 | #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) | |
2114 | #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) | |
2115 | #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) | |
2116 | #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) | |
2117 | #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) | |
2118 | #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) | |
2119 | #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) | |
2120 | #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) | |
2121 | #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) | |
2122 | #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) | |
2123 | #define WREG32_P(reg, val, mask) \ | |
2124 | do { \ | |
2125 | uint32_t tmp_ = RREG32(reg); \ | |
2126 | tmp_ &= (mask); \ | |
2127 | tmp_ |= ((val) & ~(mask)); \ | |
2128 | WREG32(reg, tmp_); \ | |
2129 | } while (0) | |
2130 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) | |
2131 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) | |
2132 | #define WREG32_PLL_P(reg, val, mask) \ | |
2133 | do { \ | |
2134 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
2135 | tmp_ &= (mask); \ | |
2136 | tmp_ |= ((val) & ~(mask)); \ | |
2137 | WREG32_PLL(reg, tmp_); \ | |
2138 | } while (0) | |
2139 | #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) | |
2140 | #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) | |
2141 | #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) | |
2142 | ||
2143 | #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) | |
2144 | #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) | |
2145 | ||
2146 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT | |
2147 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK | |
2148 | ||
2149 | #define REG_SET_FIELD(orig_val, reg, field, field_val) \ | |
2150 | (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ | |
2151 | (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) | |
2152 | ||
2153 | #define REG_GET_FIELD(value, reg, field) \ | |
2154 | (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) | |
2155 | ||
2156 | /* | |
2157 | * BIOS helpers. | |
2158 | */ | |
2159 | #define RBIOS8(i) (adev->bios[i]) | |
2160 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
2161 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
2162 | ||
2163 | /* | |
2164 | * RING helpers. | |
2165 | */ | |
2166 | static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) | |
2167 | { | |
2168 | if (ring->count_dw <= 0) | |
86c2b790 | 2169 | DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); |
97b2e202 AD |
2170 | ring->ring[ring->wptr++] = v; |
2171 | ring->wptr &= ring->ptr_mask; | |
2172 | ring->count_dw--; | |
97b2e202 AD |
2173 | } |
2174 | ||
c113ea1c AD |
2175 | static inline struct amdgpu_sdma_instance * |
2176 | amdgpu_get_sdma_instance(struct amdgpu_ring *ring) | |
4b2f7e2c JZ |
2177 | { |
2178 | struct amdgpu_device *adev = ring->adev; | |
2179 | int i; | |
2180 | ||
c113ea1c AD |
2181 | for (i = 0; i < adev->sdma.num_instances; i++) |
2182 | if (&adev->sdma.instance[i].ring == ring) | |
4b2f7e2c JZ |
2183 | break; |
2184 | ||
2185 | if (i < AMDGPU_MAX_SDMA_INSTANCES) | |
c113ea1c | 2186 | return &adev->sdma.instance[i]; |
4b2f7e2c JZ |
2187 | else |
2188 | return NULL; | |
2189 | } | |
2190 | ||
97b2e202 AD |
2191 | /* |
2192 | * ASICs macro. | |
2193 | */ | |
2194 | #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) | |
2195 | #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) | |
2196 | #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) | |
2197 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) | |
2198 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) | |
2199 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) | |
2200 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) | |
2201 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) | |
7946b878 | 2202 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
97b2e202 AD |
2203 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
2204 | #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) | |
2205 | #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) | |
2206 | #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) | |
2207 | #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) | |
b07c9d2a | 2208 | #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags))) |
97b2e202 | 2209 | #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) |
97b2e202 AD |
2210 | #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) |
2211 | #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) | |
2212 | #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) | |
97b2e202 AD |
2213 | #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) |
2214 | #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) | |
2215 | #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) | |
2216 | #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) | |
b8c7b39e | 2217 | #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) |
97b2e202 | 2218 | #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) |
890ee23f | 2219 | #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) |
97b2e202 | 2220 | #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) |
d2edb07b | 2221 | #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) |
11afbde8 | 2222 | #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) |
9e5d5309 | 2223 | #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) |
97b2e202 AD |
2224 | #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) |
2225 | #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) | |
2226 | #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) | |
2227 | #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) | |
2228 | #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) | |
2229 | #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) | |
2230 | #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) | |
2231 | #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) | |
2232 | #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) | |
2233 | #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) | |
2234 | #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) | |
2235 | #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) | |
2236 | #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) | |
2237 | #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) | |
2238 | #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) | |
2239 | #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) | |
2240 | #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) | |
2241 | #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) | |
2242 | #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) | |
c7ae72c0 | 2243 | #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) |
6e7a3840 | 2244 | #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) |
97b2e202 AD |
2245 | #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) |
2246 | #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) | |
2247 | #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) | |
2248 | #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) | |
97b2e202 | 2249 | #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) |
97b2e202 | 2250 | #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) |
97b2e202 | 2251 | #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) |
3af76f23 RZ |
2252 | |
2253 | #define amdgpu_dpm_get_temperature(adev) \ | |
4b5ece24 | 2254 | ((adev)->pp_enabled ? \ |
e61710c5 | 2255 | (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ |
4b5ece24 | 2256 | (adev)->pm.funcs->get_temperature((adev))) |
3af76f23 RZ |
2257 | |
2258 | #define amdgpu_dpm_set_fan_control_mode(adev, m) \ | |
4b5ece24 | 2259 | ((adev)->pp_enabled ? \ |
e61710c5 | 2260 | (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ |
4b5ece24 | 2261 | (adev)->pm.funcs->set_fan_control_mode((adev), (m))) |
3af76f23 RZ |
2262 | |
2263 | #define amdgpu_dpm_get_fan_control_mode(adev) \ | |
4b5ece24 | 2264 | ((adev)->pp_enabled ? \ |
e61710c5 | 2265 | (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ |
4b5ece24 | 2266 | (adev)->pm.funcs->get_fan_control_mode((adev))) |
3af76f23 RZ |
2267 | |
2268 | #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ | |
4b5ece24 | 2269 | ((adev)->pp_enabled ? \ |
e61710c5 | 2270 | (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ |
4b5ece24 | 2271 | (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) |
3af76f23 RZ |
2272 | |
2273 | #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ | |
4b5ece24 | 2274 | ((adev)->pp_enabled ? \ |
e61710c5 | 2275 | (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ |
4b5ece24 | 2276 | (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) |
97b2e202 | 2277 | |
1b5708ff | 2278 | #define amdgpu_dpm_get_sclk(adev, l) \ |
4b5ece24 | 2279 | ((adev)->pp_enabled ? \ |
e61710c5 | 2280 | (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ |
4b5ece24 | 2281 | (adev)->pm.funcs->get_sclk((adev), (l))) |
1b5708ff RZ |
2282 | |
2283 | #define amdgpu_dpm_get_mclk(adev, l) \ | |
4b5ece24 | 2284 | ((adev)->pp_enabled ? \ |
e61710c5 | 2285 | (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ |
4b5ece24 | 2286 | (adev)->pm.funcs->get_mclk((adev), (l))) |
1b5708ff RZ |
2287 | |
2288 | ||
2289 | #define amdgpu_dpm_force_performance_level(adev, l) \ | |
4b5ece24 | 2290 | ((adev)->pp_enabled ? \ |
e61710c5 | 2291 | (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ |
4b5ece24 | 2292 | (adev)->pm.funcs->force_performance_level((adev), (l))) |
1b5708ff RZ |
2293 | |
2294 | #define amdgpu_dpm_powergate_uvd(adev, g) \ | |
4b5ece24 | 2295 | ((adev)->pp_enabled ? \ |
e61710c5 | 2296 | (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ |
4b5ece24 | 2297 | (adev)->pm.funcs->powergate_uvd((adev), (g))) |
1b5708ff RZ |
2298 | |
2299 | #define amdgpu_dpm_powergate_vce(adev, g) \ | |
4b5ece24 | 2300 | ((adev)->pp_enabled ? \ |
e61710c5 | 2301 | (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ |
4b5ece24 | 2302 | (adev)->pm.funcs->powergate_vce((adev), (g))) |
1b5708ff RZ |
2303 | |
2304 | #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ | |
4b5ece24 | 2305 | ((adev)->pp_enabled ? \ |
e61710c5 | 2306 | (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ |
4b5ece24 | 2307 | (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) |
1b5708ff RZ |
2308 | |
2309 | #define amdgpu_dpm_get_current_power_state(adev) \ | |
e61710c5 | 2310 | (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) |
1b5708ff RZ |
2311 | |
2312 | #define amdgpu_dpm_get_performance_level(adev) \ | |
e61710c5 | 2313 | (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) |
1b5708ff | 2314 | |
f3898ea1 EH |
2315 | #define amdgpu_dpm_get_pp_num_states(adev, data) \ |
2316 | (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) | |
2317 | ||
2318 | #define amdgpu_dpm_get_pp_table(adev, table) \ | |
2319 | (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) | |
2320 | ||
2321 | #define amdgpu_dpm_set_pp_table(adev, buf, size) \ | |
2322 | (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) | |
2323 | ||
2324 | #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ | |
2325 | (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) | |
2326 | ||
2327 | #define amdgpu_dpm_force_clock_level(adev, type, level) \ | |
2328 | (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) | |
2329 | ||
e61710c5 | 2330 | #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ |
1b5708ff | 2331 | (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) |
97b2e202 AD |
2332 | |
2333 | #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) | |
2334 | ||
2335 | /* Common functions */ | |
2336 | int amdgpu_gpu_reset(struct amdgpu_device *adev); | |
2337 | void amdgpu_pci_config_reset(struct amdgpu_device *adev); | |
2338 | bool amdgpu_card_posted(struct amdgpu_device *adev); | |
2339 | void amdgpu_update_display_priority(struct amdgpu_device *adev); | |
d5fc5e82 | 2340 | |
97b2e202 AD |
2341 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); |
2342 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, | |
2343 | u32 ip_instance, u32 ring, | |
2344 | struct amdgpu_ring **out_ring); | |
2345 | void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); | |
2346 | bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); | |
2f568dbd | 2347 | int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); |
97b2e202 AD |
2348 | int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
2349 | uint32_t flags); | |
cc325d19 | 2350 | struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); |
d7006964 CK |
2351 | bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, |
2352 | unsigned long end); | |
2f568dbd CK |
2353 | bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, |
2354 | int *last_invalidated); | |
97b2e202 AD |
2355 | bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); |
2356 | uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, | |
2357 | struct ttm_mem_reg *mem); | |
2358 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); | |
2359 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); | |
2360 | void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); | |
2361 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
2362 | const u32 *registers, | |
2363 | const u32 array_size); | |
2364 | ||
2365 | bool amdgpu_device_is_px(struct drm_device *dev); | |
2366 | /* atpx handler */ | |
2367 | #if defined(CONFIG_VGA_SWITCHEROO) | |
2368 | void amdgpu_register_atpx_handler(void); | |
2369 | void amdgpu_unregister_atpx_handler(void); | |
2370 | #else | |
2371 | static inline void amdgpu_register_atpx_handler(void) {} | |
2372 | static inline void amdgpu_unregister_atpx_handler(void) {} | |
2373 | #endif | |
2374 | ||
2375 | /* | |
2376 | * KMS | |
2377 | */ | |
2378 | extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; | |
2379 | extern int amdgpu_max_kms_ioctl; | |
2380 | ||
2381 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
2382 | int amdgpu_driver_unload_kms(struct drm_device *dev); | |
2383 | void amdgpu_driver_lastclose_kms(struct drm_device *dev); | |
2384 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
2385 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
2386 | struct drm_file *file_priv); | |
2387 | void amdgpu_driver_preclose_kms(struct drm_device *dev, | |
2388 | struct drm_file *file_priv); | |
2389 | int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); | |
2390 | int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); | |
88e72717 TR |
2391 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); |
2392 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
2393 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
2394 | int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, | |
97b2e202 AD |
2395 | int *max_error, |
2396 | struct timeval *vblank_time, | |
2397 | unsigned flags); | |
2398 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, | |
2399 | unsigned long arg); | |
2400 | ||
97b2e202 AD |
2401 | /* |
2402 | * functions used by amdgpu_encoder.c | |
2403 | */ | |
2404 | struct amdgpu_afmt_acr { | |
2405 | u32 clock; | |
2406 | ||
2407 | int n_32khz; | |
2408 | int cts_32khz; | |
2409 | ||
2410 | int n_44_1khz; | |
2411 | int cts_44_1khz; | |
2412 | ||
2413 | int n_48khz; | |
2414 | int cts_48khz; | |
2415 | ||
2416 | }; | |
2417 | ||
2418 | struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); | |
2419 | ||
2420 | /* amdgpu_acpi.c */ | |
2421 | #if defined(CONFIG_ACPI) | |
2422 | int amdgpu_acpi_init(struct amdgpu_device *adev); | |
2423 | void amdgpu_acpi_fini(struct amdgpu_device *adev); | |
2424 | bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); | |
2425 | int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, | |
2426 | u8 perf_req, bool advertise); | |
2427 | int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); | |
2428 | #else | |
2429 | static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } | |
2430 | static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } | |
2431 | #endif | |
2432 | ||
2433 | struct amdgpu_bo_va_mapping * | |
2434 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
2435 | uint64_t addr, struct amdgpu_bo **bo); | |
2436 | ||
2437 | #include "amdgpu_object.h" | |
2438 | ||
2439 | #endif |