[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_acp.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include <linux/irqdomain.h>
#include <linux/pci.h>
#include <linux/pm_domain.h>
#include <linux/platform_device.h>
#include <sound/designware_i2s.h>
#include <sound/pcm.h>

#include "amdgpu.h"
#include "atom.h"
#include "amdgpu_acp.h"

#include "acp_gfx_if.h"

#define ACP_TILE_ON_MASK                	0x03
#define ACP_TILE_OFF_MASK               	0x02
#define ACP_TILE_ON_RETAIN_REG_MASK     	0x1f
#define ACP_TILE_OFF_RETAIN_REG_MASK    	0x20

#define ACP_TILE_P1_MASK                	0x3e
#define ACP_TILE_P2_MASK                	0x3d
#define ACP_TILE_DSP0_MASK              	0x3b
#define ACP_TILE_DSP1_MASK              	0x37

#define ACP_TILE_DSP2_MASK              	0x2f

#define ACP_DMA_REGS_END			0x146c0
#define ACP_I2S_PLAY_REGS_START			0x14840
#define ACP_I2S_PLAY_REGS_END			0x148b4
#define ACP_I2S_CAP_REGS_START			0x148b8
#define ACP_I2S_CAP_REGS_END			0x1496c

#define ACP_I2S_COMP1_CAP_REG_OFFSET		0xac
#define ACP_I2S_COMP2_CAP_REG_OFFSET		0xa8
#define ACP_I2S_COMP1_PLAY_REG_OFFSET		0x6c
#define ACP_I2S_COMP2_PLAY_REG_OFFSET		0x68
#define ACP_BT_PLAY_REGS_START			0x14970
#define ACP_BT_PLAY_REGS_END			0x14a24
#define ACP_BT_COMP1_REG_OFFSET			0xac
#define ACP_BT_COMP2_REG_OFFSET			0xa8

#define mmACP_PGFSM_RETAIN_REG			0x51c9
#define mmACP_PGFSM_CONFIG_REG			0x51ca
#define mmACP_PGFSM_READ_REG_0			0x51cc

#define mmACP_MEM_SHUT_DOWN_REQ_LO		0x51f8
#define mmACP_MEM_SHUT_DOWN_REQ_HI		0x51f9
#define mmACP_MEM_SHUT_DOWN_STS_LO		0x51fa
#define mmACP_MEM_SHUT_DOWN_STS_HI		0x51fb

#define mmACP_CONTROL				0x5131
#define mmACP_STATUS				0x5133
#define mmACP_SOFT_RESET			0x5134
#define ACP_CONTROL__ClkEn_MASK 		0x1
#define ACP_SOFT_RESET__SoftResetAud_MASK 	0x100
#define ACP_SOFT_RESET__SoftResetAudDone_MASK	0x1000000
#define ACP_CLOCK_EN_TIME_OUT_VALUE		0x000000FF
#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE	0x000000FF

#define ACP_TIMEOUT_LOOP			0x000000FF
#define ACP_DEVS				4
#define ACP_SRC_ID				162

enum {
	ACP_TILE_P1 = 0,
	ACP_TILE_P2,
	ACP_TILE_DSP0,
	ACP_TILE_DSP1,
	ACP_TILE_DSP2,
};

static int acp_sw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	adev->acp.parent = adev->dev;

	adev->acp.cgs_device =
		amdgpu_cgs_create_device(adev);
	if (!adev->acp.cgs_device)
		return -EINVAL;

	return 0;
}

static int acp_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (adev->acp.cgs_device)
		amdgpu_cgs_destroy_device(adev->acp.cgs_device);

	return 0;
}

struct acp_pm_domain {
	void *adev;
	struct generic_pm_domain gpd;
};

static int acp_poweroff(struct generic_pm_domain *genpd)
{
	struct acp_pm_domain *apd;
	struct amdgpu_device *adev;

	apd = container_of(genpd, struct acp_pm_domain, gpd);
	if (apd != NULL) {
		adev = apd->adev;
	/* call smu to POWER GATE ACP block
	 * smu will
	 * 1. turn off the acp clock
	 * 2. power off the acp tiles
	 * 3. check and enter ulv state
	 */
		if (adev->powerplay.pp_funcs &&
			adev->powerplay.pp_funcs->set_powergating_by_smu)
			amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
	}
	return 0;
}

static int acp_poweron(struct generic_pm_domain *genpd)
{
	struct acp_pm_domain *apd;
	struct amdgpu_device *adev;

	apd = container_of(genpd, struct acp_pm_domain, gpd);
	if (apd != NULL) {
		adev = apd->adev;
	/* call smu to UNGATE ACP block
	 * smu will
	 * 1. exit ulv
	 * 2. turn on acp clock
	 * 3. power on acp tiles
	 */
		if (adev->powerplay.pp_funcs->set_powergating_by_smu)
			amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
	}
	return 0;
}

static struct device *get_mfd_cell_dev(const char *device_name, int r)
{
	char auto_dev_name[25];
	struct device *dev;

	snprintf(auto_dev_name, sizeof(auto_dev_name),
		 "%s.%d.auto", device_name, r);
	dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
	dev_info(dev, "device %s added to pm domain\n", auto_dev_name);

	return dev;
}

/**
 * acp_hw_init - start and test ACP block
 *
 * @adev: amdgpu_device pointer
 *
 */
static int acp_hw_init(void *handle)
{
	int r, i;
	uint64_t acp_base;
	u32 val = 0;
	u32 count = 0;
	struct device *dev;
	struct i2s_platform_data *i2s_pdata = NULL;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	const struct amdgpu_ip_block *ip_block =
		amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);

	if (!ip_block)
		return -EINVAL;

	r = amd_acp_hw_init(adev->acp.cgs_device,
			    ip_block->version->major, ip_block->version->minor);
	/* -ENODEV means board uses AZ rather than ACP */
	if (r == -ENODEV) {
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
		return 0;
	} else if (r) {
		return r;
	}

	if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
		return -EINVAL;

	acp_base = adev->rmmio_base;


	adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
	if (adev->acp.acp_genpd == NULL)
		return -ENOMEM;

	adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
	adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
	adev->acp.acp_genpd->gpd.power_on = acp_poweron;


	adev->acp.acp_genpd->adev = adev;

	pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);

	adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
							GFP_KERNEL);

	if (adev->acp.acp_cell == NULL) {
		r = -ENOMEM;
		goto failure;
	}

	adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
	if (adev->acp.acp_res == NULL) {
		r = -ENOMEM;
		goto failure;
	}

	i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
	if (i2s_pdata == NULL) {
		r = -ENOMEM;
		goto failure;
	}

	switch (adev->asic_type) {
	case CHIP_STONEY:
		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
			DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
		break;
	default:
		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
	}
	i2s_pdata[0].cap = DWC_I2S_PLAY;
	i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
	i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
	i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
	switch (adev->asic_type) {
	case CHIP_STONEY:
		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
			DW_I2S_QUIRK_COMP_PARAM1 |
			DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
		break;
	default:
		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
			DW_I2S_QUIRK_COMP_PARAM1;
	}

	i2s_pdata[1].cap = DWC_I2S_RECORD;
	i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
	i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
	i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;

	i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
	switch (adev->asic_type) {
	case CHIP_STONEY:
		i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
		break;
	default:
		break;
	}

	i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
	i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
	i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
	i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;

	adev->acp.acp_res[0].name = "acp2x_dma";
	adev->acp.acp_res[0].flags = IORESOURCE_MEM;
	adev->acp.acp_res[0].start = acp_base;
	adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;

	adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
	adev->acp.acp_res[1].flags = IORESOURCE_MEM;
	adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
	adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;

	adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
	adev->acp.acp_res[2].flags = IORESOURCE_MEM;
	adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
	adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;

	adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
	adev->acp.acp_res[3].flags = IORESOURCE_MEM;
	adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
	adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;

	adev->acp.acp_res[4].name = "acp2x_dma_irq";
	adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
	adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
	adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;

	adev->acp.acp_cell[0].name = "acp_audio_dma";
	adev->acp.acp_cell[0].num_resources = 5;
	adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
	adev->acp.acp_cell[0].platform_data = &adev->asic_type;
	adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);

	adev->acp.acp_cell[1].name = "designware-i2s";
	adev->acp.acp_cell[1].num_resources = 1;
	adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
	adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
	adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);

	adev->acp.acp_cell[2].name = "designware-i2s";
	adev->acp.acp_cell[2].num_resources = 1;
	adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
	adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
	adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);

	adev->acp.acp_cell[3].name = "designware-i2s";
	adev->acp.acp_cell[3].num_resources = 1;
	adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
	adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
	adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);

	r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
								ACP_DEVS);
	if (r)
		goto failure;

	for (i = 0; i < ACP_DEVS ; i++) {
		dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
		r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
		if (r) {
			dev_err(dev, "Failed to add dev to genpd\n");
			goto failure;
		}
	}


	/* Assert Soft reset of ACP */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);

	val |= ACP_SOFT_RESET__SoftResetAud_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);

	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	while (true) {
		val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
		if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
		    (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
			break;
		if (--count == 0) {
			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
			r = -ETIMEDOUT;
			goto failure;
		}
		udelay(100);
	}
	/* Enable clock to ACP and wait until the clock is enabled */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
	val = val | ACP_CONTROL__ClkEn_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);

	count = ACP_CLOCK_EN_TIME_OUT_VALUE;

	while (true) {
		val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
		if (val & (u32) 0x1)
			break;
		if (--count == 0) {
			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
			r = -ETIMEDOUT;
			goto failure;
		}
		udelay(100);
	}
	/* Deassert the SOFT RESET flags */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
	return 0;

failure:
	kfree(i2s_pdata);
	kfree(adev->acp.acp_res);
	kfree(adev->acp.acp_cell);
	kfree(adev->acp.acp_genpd);
	return r;
}

/**
 * acp_hw_fini - stop the hardware block
 *
 * @adev: amdgpu_device pointer
 *
 */
static int acp_hw_fini(void *handle)
{
	int i, ret;
	u32 val = 0;
	u32 count = 0;
	struct device *dev;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* return early if no ACP */
	if (!adev->acp.acp_genpd) {
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
		return 0;
	}

	/* Assert Soft reset of ACP */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);

	val |= ACP_SOFT_RESET__SoftResetAud_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);

	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	while (true) {
		val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
		if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
		    (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
			break;
		if (--count == 0) {
			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
			return -ETIMEDOUT;
		}
		udelay(100);
	}
	/* Disable ACP clock */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
	val &= ~ACP_CONTROL__ClkEn_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);

	count = ACP_CLOCK_EN_TIME_OUT_VALUE;

	while (true) {
		val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
		if (val & (u32) 0x1)
			break;
		if (--count == 0) {
			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
			return -ETIMEDOUT;
		}
		udelay(100);
	}

	for (i = 0; i < ACP_DEVS ; i++) {
		dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
		ret = pm_genpd_remove_device(dev);
		/* If removal fails, dont giveup and try rest */
		if (ret)
			dev_err(dev, "remove dev from genpd failed\n");
	}

	mfd_remove_devices(adev->acp.parent);
	kfree(adev->acp.acp_res);
	kfree(adev->acp.acp_genpd);
	kfree(adev->acp.acp_cell);

	return 0;
}

static int acp_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* power up on suspend */
	if (!adev->acp.acp_cell)
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
	return 0;
}

static int acp_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* power down again on resume */
	if (!adev->acp.acp_cell)
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
	return 0;
}

static int acp_early_init(void *handle)
{
	return 0;
}

static bool acp_is_idle(void *handle)
{
	return true;
}

static int acp_wait_for_idle(void *handle)
{
	return 0;
}

static int acp_soft_reset(void *handle)
{
	return 0;
}

static int acp_set_clockgating_state(void *handle,
				     enum amd_clockgating_state state)
{
	return 0;
}

static int acp_set_powergating_state(void *handle,
				     enum amd_powergating_state state)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	bool enable = (state == AMD_PG_STATE_GATE);

	if (adev->powerplay.pp_funcs &&
		adev->powerplay.pp_funcs->set_powergating_by_smu)
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);

	return 0;
}

static const struct amd_ip_funcs acp_ip_funcs = {
	.name = "acp_ip",
	.early_init = acp_early_init,
	.late_init = NULL,
	.sw_init = acp_sw_init,
	.sw_fini = acp_sw_fini,
	.hw_init = acp_hw_init,
	.hw_fini = acp_hw_fini,
	.suspend = acp_suspend,
	.resume = acp_resume,
	.is_idle = acp_is_idle,
	.wait_for_idle = acp_wait_for_idle,
	.soft_reset = acp_soft_reset,
	.set_clockgating_state = acp_set_clockgating_state,
	.set_powergating_state = acp_set_powergating_state,
};

const struct amdgpu_ip_block_version acp_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_ACP,
	.major = 2,
	.minor = 2,
	.rev = 0,
	.funcs = &acp_ip_funcs,
};
Commit	Line	Data
a8fe58ce MB	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include <linux/irqdomain.h>
841d0023	27	#include <linux/pci.h>
25030321	28	#include <linux/pm_domain.h>
a8fe58ce MB	29	#include <linux/platform_device.h>
	30	#include <sound/designware_i2s.h>
	31	#include <sound/pcm.h>
	32
	33	#include "amdgpu.h"
	34	#include "atom.h"
	35	#include "amdgpu_acp.h"
	36
	37	#include "acp_gfx_if.h"
	38
37c5f2c9 AA	39	#define ACP_TILE_ON_MASK 0x03
	40	#define ACP_TILE_OFF_MASK 0x02
	41	#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
	42	#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
	43
	44	#define ACP_TILE_P1_MASK 0x3e
	45	#define ACP_TILE_P2_MASK 0x3d
	46	#define ACP_TILE_DSP0_MASK 0x3b
	47	#define ACP_TILE_DSP1_MASK 0x37
	48
	49	#define ACP_TILE_DSP2_MASK 0x2f
	50
	51	#define ACP_DMA_REGS_END 0x146c0
	52	#define ACP_I2S_PLAY_REGS_START 0x14840
	53	#define ACP_I2S_PLAY_REGS_END 0x148b4
	54	#define ACP_I2S_CAP_REGS_START 0x148b8
	55	#define ACP_I2S_CAP_REGS_END 0x1496c
	56
	57	#define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
	58	#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
	59	#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
	60	#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
2d95ceb4 VM	61	#define ACP_BT_PLAY_REGS_START 0x14970
	62	#define ACP_BT_PLAY_REGS_END 0x14a24
	63	#define ACP_BT_COMP1_REG_OFFSET 0xac
	64	#define ACP_BT_COMP2_REG_OFFSET 0xa8
37c5f2c9 AA	65
	66	#define mmACP_PGFSM_RETAIN_REG 0x51c9
	67	#define mmACP_PGFSM_CONFIG_REG 0x51ca
	68	#define mmACP_PGFSM_READ_REG_0 0x51cc
	69
	70	#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
	71	#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
	72	#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
	73	#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
	74
	75	#define mmACP_CONTROL 0x5131
	76	#define mmACP_STATUS 0x5133
	77	#define mmACP_SOFT_RESET 0x5134
	78	#define ACP_CONTROL__ClkEn_MASK 0x1
	79	#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
	80	#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
	81	#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
	82	#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
	83
	84	#define ACP_TIMEOUT_LOOP 0x000000FF
2d95ceb4	85	#define ACP_DEVS 4
37c5f2c9	86	#define ACP_SRC_ID 162
a8fe58ce MB	87
	88	enum {
	89	ACP_TILE_P1 = 0,
	90	ACP_TILE_P2,
	91	ACP_TILE_DSP0,
	92	ACP_TILE_DSP1,
	93	ACP_TILE_DSP2,
	94	};
	95
	96	static int acp_sw_init(void *handle)
	97	{
	98	struct amdgpu_device adev = (struct amdgpu_device )handle;
	99
	100	adev->acp.parent = adev->dev;
	101
	102	adev->acp.cgs_device =
	103	amdgpu_cgs_create_device(adev);
	104	if (!adev->acp.cgs_device)
	105	return -EINVAL;
	106
	107	return 0;
	108	}
	109
	110	static int acp_sw_fini(void *handle)
	111	{
	112	struct amdgpu_device adev = (struct amdgpu_device )handle;
	113
	114	if (adev->acp.cgs_device)
	115	amdgpu_cgs_destroy_device(adev->acp.cgs_device);
	116
	117	return 0;
	118	}
	119
25030321	120	struct acp_pm_domain {
3a54d2c8	121	void *adev;
25030321 MSB	122	struct generic_pm_domain gpd;
	123	};
	124
	125	static int acp_poweroff(struct generic_pm_domain *genpd)
	126	{
25030321	127	struct acp_pm_domain *apd;
3a54d2c8	128	struct amdgpu_device *adev;
25030321 MSB	129
	130	apd = container_of(genpd, struct acp_pm_domain, gpd);
	131	if (apd != NULL) {
3a54d2c8 RZ	132	adev = apd->adev;
	133	/* call smu to POWER GATE ACP block
	134	* smu will
	135	* 1. turn off the acp clock
	136	* 2. power off the acp tiles
	137	* 3. check and enter ulv state
	138	*/
7179d240 RZ	139	if (adev->powerplay.pp_funcs &&
7179d240 RZ	140	adev->powerplay.pp_funcs->set_powergating_by_smu)
3a54d2c8	141	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
25030321 MSB	142	}
	143	return 0;
	144	}
	145
	146	static int acp_poweron(struct generic_pm_domain *genpd)
	147	{
25030321	148	struct acp_pm_domain *apd;
3a54d2c8	149	struct amdgpu_device *adev;
25030321 MSB	150
	151	apd = container_of(genpd, struct acp_pm_domain, gpd);
	152	if (apd != NULL) {
3a54d2c8 RZ	153	adev = apd->adev;
	154	/* call smu to UNGATE ACP block
	155	* smu will
	156	* 1. exit ulv
	157	* 2. turn on acp clock
	158	* 3. power on acp tiles
	159	*/
	160	if (adev->powerplay.pp_funcs->set_powergating_by_smu)
	161	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
25030321 MSB	162	}
	163	return 0;
	164	}
	165
	166	static struct device get_mfd_cell_dev(const char device_name, int r)
	167	{
	168	char auto_dev_name[25];
25030321 MSB	169	struct device *dev;
25030321 MSB	170
a65ecc40 DC	171	snprintf(auto_dev_name, sizeof(auto_dev_name),
a65ecc40 DC	172	"%s.%d.auto", device_name, r);
25030321 MSB	173	dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
	174	dev_info(dev, "device %s added to pm domain\n", auto_dev_name);
	175
	176	return dev;
	177	}
	178
a8fe58ce MB	179	/**
	180	* acp_hw_init - start and test ACP block
	181	*
	182	* @adev: amdgpu_device pointer
	183	*
	184	*/
	185	static int acp_hw_init(void *handle)
	186	{
25030321	187	int r, i;
a8fe58ce	188	uint64_t acp_base;
37c5f2c9 AA	189	u32 val = 0;
37c5f2c9 AA	190	u32 count = 0;
25030321	191	struct device *dev;
57be09c6	192	struct i2s_platform_data *i2s_pdata = NULL;
a8fe58ce MB	193
	194	struct amdgpu_device adev = (struct amdgpu_device )handle;
	195
a1255107	196	const struct amdgpu_ip_block *ip_block =
2990a1fc	197	amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
a8fe58ce	198
a1255107	199	if (!ip_block)
a8fe58ce MB	200	return -EINVAL;
	201
	202	r = amd_acp_hw_init(adev->acp.cgs_device,
a1255107	203	ip_block->version->major, ip_block->version->minor);
a8fe58ce	204	/* -ENODEV means board uses AZ rather than ACP */
be2d6aa5 RZ	205	if (r == -ENODEV) {
be2d6aa5 RZ	206	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
a8fe58ce	207	return 0;
be2d6aa5	208	} else if (r) {
a8fe58ce	209	return r;
be2d6aa5	210	}
a8fe58ce	211
d32d6617 RZ	212	if (adev->rmmio_size == 0 \|\| adev->rmmio_size < 0x5289)
	213	return -EINVAL;
	214
	215	acp_base = adev->rmmio_base;
	216
a8fe58ce	217
1062ddb6 VM	218	adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
	219	if (adev->acp.acp_genpd == NULL)
	220	return -ENOMEM;
25030321	221
1062ddb6 VM	222	adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
	223	adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
	224	adev->acp.acp_genpd->gpd.power_on = acp_poweron;
25030321	225
25030321	226
3a54d2c8	227	adev->acp.acp_genpd->adev = adev;
1062ddb6 VM	228
1062ddb6 VM	229	pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
25030321	230
6396bb22	231	adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
a8fe58ce MB	232	GFP_KERNEL);
a8fe58ce MB	233
57be09c6 NE	234	if (adev->acp.acp_cell == NULL) {
	235	r = -ENOMEM;
	236	goto failure;
	237	}
a8fe58ce	238
2d95ceb4	239	adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
a8fe58ce	240	if (adev->acp.acp_res == NULL) {
57be09c6 NE	241	r = -ENOMEM;
57be09c6 NE	242	goto failure;
a8fe58ce MB	243	}
a8fe58ce MB	244
2d95ceb4	245	i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
a8fe58ce	246	if (i2s_pdata == NULL) {
57be09c6 NE	247	r = -ENOMEM;
57be09c6 NE	248	goto failure;
a8fe58ce MB	249	}
a8fe58ce MB	250
81454cad VM	251	switch (adev->asic_type) {
	252	case CHIP_STONEY:
	253	i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET \|
	254	DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
	255	break;
	256	default:
	257	i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
	258	}
a8fe58ce MB	259	i2s_pdata[0].cap = DWC_I2S_PLAY;
	260	i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
	261	i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
	262	i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
81454cad VM	263	switch (adev->asic_type) {
	264	case CHIP_STONEY:
	265	i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET \|
	266	DW_I2S_QUIRK_COMP_PARAM1 \|
	267	DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
	268	break;
	269	default:
	270	i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET \|
	271	DW_I2S_QUIRK_COMP_PARAM1;
	272	}
a8fe58ce	273
a8fe58ce MB	274	i2s_pdata[1].cap = DWC_I2S_RECORD;
	275	i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
	276	i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
	277	i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
	278
2d95ceb4 VM	279	i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
	280	switch (adev->asic_type) {
	281	case CHIP_STONEY:
	282	i2s_pdata[2].quirks \|= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
	283	break;
	284	default:
	285	break;
	286	}
	287
	288	i2s_pdata[2].cap = DWC_I2S_PLAY \| DWC_I2S_RECORD;
	289	i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
	290	i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
	291	i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
	292
a8fe58ce MB	293	adev->acp.acp_res[0].name = "acp2x_dma";
	294	adev->acp.acp_res[0].flags = IORESOURCE_MEM;
	295	adev->acp.acp_res[0].start = acp_base;
	296	adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
	297
	298	adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
	299	adev->acp.acp_res[1].flags = IORESOURCE_MEM;
	300	adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
	301	adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
	302
	303	adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
	304	adev->acp.acp_res[2].flags = IORESOURCE_MEM;
	305	adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
	306	adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
	307
2d95ceb4 VM	308	adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
	309	adev->acp.acp_res[3].flags = IORESOURCE_MEM;
	310	adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
	311	adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
	312
	313	adev->acp.acp_res[4].name = "acp2x_dma_irq";
	314	adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
	315	adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
	316	adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
a8fe58ce MB	317
a8fe58ce MB	318	adev->acp.acp_cell[0].name = "acp_audio_dma";
2d95ceb4	319	adev->acp.acp_cell[0].num_resources = 5;
a8fe58ce	320	adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
1fd16f36 VM	321	adev->acp.acp_cell[0].platform_data = &adev->asic_type;
1fd16f36 VM	322	adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
a8fe58ce MB	323
	324	adev->acp.acp_cell[1].name = "designware-i2s";
	325	adev->acp.acp_cell[1].num_resources = 1;
	326	adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
	327	adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
	328	adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
	329
	330	adev->acp.acp_cell[2].name = "designware-i2s";
	331	adev->acp.acp_cell[2].num_resources = 1;
	332	adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
	333	adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
	334	adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
	335
2d95ceb4 VM	336	adev->acp.acp_cell[3].name = "designware-i2s";
	337	adev->acp.acp_cell[3].num_resources = 1;
	338	adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
	339	adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
	340	adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
	341
a8fe58ce MB	342	r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
	343	ACP_DEVS);
	344	if (r)
57be09c6	345	goto failure;
a8fe58ce	346
1062ddb6 VM	347	for (i = 0; i < ACP_DEVS ; i++) {
	348	dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
	349	r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
	350	if (r) {
	351	dev_err(dev, "Failed to add dev to genpd\n");
57be09c6	352	goto failure;
25030321 MSB	353	}
	354	}
	355
1062ddb6	356
37c5f2c9 AA	357	/* Assert Soft reset of ACP */
	358	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	359
	360	val \|= ACP_SOFT_RESET__SoftResetAud_MASK;
	361	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
	362
	363	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	364	while (true) {
	365	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	366	if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
	367	(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
	368	break;
	369	if (--count == 0) {
	370	dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
57be09c6 NE	371	r = -ETIMEDOUT;
57be09c6 NE	372	goto failure;
37c5f2c9 AA	373	}
	374	udelay(100);
	375	}
	376	/* Enable clock to ACP and wait until the clock is enabled */
	377	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
	378	val = val \| ACP_CONTROL__ClkEn_MASK;
	379	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
	380
	381	count = ACP_CLOCK_EN_TIME_OUT_VALUE;
	382
	383	while (true) {
	384	val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
	385	if (val & (u32) 0x1)
	386	break;
	387	if (--count == 0) {
	388	dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
57be09c6 NE	389	r = -ETIMEDOUT;
57be09c6 NE	390	goto failure;
37c5f2c9 AA	391	}
	392	udelay(100);
	393	}
	394	/* Deassert the SOFT RESET flags */
	395	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	396	val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
	397	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
a8fe58ce	398	return 0;
57be09c6 NE	399
	400	failure:
	401	kfree(i2s_pdata);
	402	kfree(adev->acp.acp_res);
	403	kfree(adev->acp.acp_cell);
	404	kfree(adev->acp.acp_genpd);
	405	return r;
a8fe58ce MB	406	}
	407
	408	/**
	409	* acp_hw_fini - stop the hardware block
	410	*
	411	* @adev: amdgpu_device pointer
	412	*
	413	*/
	414	static int acp_hw_fini(void *handle)
	415	{
25030321	416	int i, ret;
37c5f2c9 AA	417	u32 val = 0;
37c5f2c9 AA	418	u32 count = 0;
25030321	419	struct device *dev;
a8fe58ce MB	420	struct amdgpu_device adev = (struct amdgpu_device )handle;
a8fe58ce MB	421
757124d9	422	/* return early if no ACP */
1062ddb6	423	if (!adev->acp.acp_genpd) {
be2d6aa5	424	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
757124d9	425	return 0;
be2d6aa5	426	}
757124d9	427
37c5f2c9 AA	428	/* Assert Soft reset of ACP */
	429	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	430
	431	val \|= ACP_SOFT_RESET__SoftResetAud_MASK;
	432	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
	433
	434	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	435	while (true) {
	436	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	437	if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
	438	(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
	439	break;
	440	if (--count == 0) {
	441	dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
	442	return -ETIMEDOUT;
	443	}
	444	udelay(100);
	445	}
	446	/* Disable ACP clock */
	447	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
	448	val &= ~ACP_CONTROL__ClkEn_MASK;
	449	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
	450
	451	count = ACP_CLOCK_EN_TIME_OUT_VALUE;
	452
	453	while (true) {
	454	val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
	455	if (val & (u32) 0x1)
	456	break;
	457	if (--count == 0) {
	458	dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
	459	return -ETIMEDOUT;
	460	}
	461	udelay(100);
	462	}
	463
1062ddb6 VM	464	for (i = 0; i < ACP_DEVS ; i++) {
	465	dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
	466	ret = pm_genpd_remove_device(dev);
	467	/* If removal fails, dont giveup and try rest */
	468	if (ret)
	469	dev_err(dev, "remove dev from genpd failed\n");
25030321 MSB	470	}
25030321 MSB	471
a8fe58ce MB	472	mfd_remove_devices(adev->acp.parent);
a8fe58ce MB	473	kfree(adev->acp.acp_res);
1062ddb6	474	kfree(adev->acp.acp_genpd);
a8fe58ce MB	475	kfree(adev->acp.acp_cell);
	476
	477	return 0;
	478	}
	479
	480	static int acp_suspend(void *handle)
	481	{
be2d6aa5 RZ	482	struct amdgpu_device adev = (struct amdgpu_device )handle;
	483
	484	/* power up on suspend */
	485	if (!adev->acp.acp_cell)
	486	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
a8fe58ce MB	487	return 0;
	488	}
	489
	490	static int acp_resume(void *handle)
	491	{
be2d6aa5 RZ	492	struct amdgpu_device adev = (struct amdgpu_device )handle;
	493
	494	/* power down again on resume */
	495	if (!adev->acp.acp_cell)
	496	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
a8fe58ce MB	497	return 0;
	498	}
	499
	500	static int acp_early_init(void *handle)
	501	{
	502	return 0;
	503	}
	504
	505	static bool acp_is_idle(void *handle)
	506	{
	507	return true;
	508	}
	509
	510	static int acp_wait_for_idle(void *handle)
	511	{
	512	return 0;
	513	}
	514
	515	static int acp_soft_reset(void *handle)
	516	{
	517	return 0;
	518	}
	519
a8fe58ce MB	520	static int acp_set_clockgating_state(void *handle,
	521	enum amd_clockgating_state state)
	522	{
	523	return 0;
	524	}
	525
	526	static int acp_set_powergating_state(void *handle,
	527	enum amd_powergating_state state)
	528	{
c36628d8	529	struct amdgpu_device adev = (struct amdgpu_device )handle;
a9d4fe2f	530	bool enable = (state == AMD_PG_STATE_GATE);
c36628d8	531
7179d240 RZ	532	if (adev->powerplay.pp_funcs &&
7179d240 RZ	533	adev->powerplay.pp_funcs->set_powergating_by_smu)
c36628d8 RZ	534	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
c36628d8 RZ	535
a8fe58ce MB	536	return 0;
	537	}
	538
a1255107	539	static const struct amd_ip_funcs acp_ip_funcs = {
88a907d6	540	.name = "acp_ip",
a8fe58ce MB	541	.early_init = acp_early_init,
	542	.late_init = NULL,
	543	.sw_init = acp_sw_init,
	544	.sw_fini = acp_sw_fini,
	545	.hw_init = acp_hw_init,
	546	.hw_fini = acp_hw_fini,
	547	.suspend = acp_suspend,
	548	.resume = acp_resume,
	549	.is_idle = acp_is_idle,
	550	.wait_for_idle = acp_wait_for_idle,
	551	.soft_reset = acp_soft_reset,
a8fe58ce MB	552	.set_clockgating_state = acp_set_clockgating_state,
	553	.set_powergating_state = acp_set_powergating_state,
	554	};
a1255107 AD	555
	556	const struct amdgpu_ip_block_version acp_ip_block =
	557	{
	558	.type = AMD_IP_BLOCK_TYPE_ACP,
	559	.major = 2,
	560	.minor = 2,
	561	.rev = 0,
	562	.funcs = &acp_ip_funcs,
	563	};