]>
Commit | Line | Data |
---|---|---|
130e0371 OG |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #include "amdgpu_amdkfd.h" | |
2f7d10b3 | 24 | #include "amd_shared.h" |
130e0371 OG |
25 | #include <drm/drmP.h> |
26 | #include "amdgpu.h" | |
2db0cdbe | 27 | #include "amdgpu_gfx.h" |
130e0371 OG |
28 | #include <linux/module.h> |
29 | ||
130e0371 | 30 | const struct kgd2kfd_calls *kgd2kfd; |
8eabaf54 | 31 | bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**); |
130e0371 | 32 | |
efb1c658 | 33 | int amdgpu_amdkfd_init(void) |
130e0371 | 34 | { |
efb1c658 OG |
35 | int ret; |
36 | ||
130e0371 | 37 | #if defined(CONFIG_HSA_AMD_MODULE) |
8eabaf54 | 38 | int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**); |
130e0371 OG |
39 | |
40 | kgd2kfd_init_p = symbol_request(kgd2kfd_init); | |
41 | ||
42 | if (kgd2kfd_init_p == NULL) | |
efb1c658 OG |
43 | return -ENOENT; |
44 | ||
45 | ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd); | |
46 | if (ret) { | |
47 | symbol_put(kgd2kfd_init); | |
48 | kgd2kfd = NULL; | |
49 | } | |
50 | ||
51 | #elif defined(CONFIG_HSA_AMD) | |
52 | ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd); | |
53 | if (ret) | |
54 | kgd2kfd = NULL; | |
55 | ||
56 | #else | |
57 | ret = -ENOENT; | |
130e0371 | 58 | #endif |
efb1c658 OG |
59 | |
60 | return ret; | |
130e0371 OG |
61 | } |
62 | ||
5c33f214 FK |
63 | void amdgpu_amdkfd_fini(void) |
64 | { | |
65 | if (kgd2kfd) { | |
66 | kgd2kfd->exit(); | |
67 | symbol_put(kgd2kfd_init); | |
68 | } | |
69 | } | |
70 | ||
71 | void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) | |
130e0371 | 72 | { |
5c33f214 FK |
73 | const struct kfd2kgd_calls *kfd2kgd; |
74 | ||
75 | if (!kgd2kfd) | |
76 | return; | |
77 | ||
dc102c43 | 78 | switch (adev->asic_type) { |
41548ef7 | 79 | #ifdef CONFIG_DRM_AMDGPU_CIK |
130e0371 | 80 | case CHIP_KAVERI: |
32c22e99 OG |
81 | kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions(); |
82 | break; | |
41548ef7 | 83 | #endif |
ff758a12 BG |
84 | case CHIP_CARRIZO: |
85 | kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions(); | |
86 | break; | |
130e0371 | 87 | default: |
9953b72f | 88 | dev_dbg(adev->dev, "kfd not supported on this ASIC\n"); |
5c33f214 | 89 | return; |
130e0371 OG |
90 | } |
91 | ||
5c33f214 FK |
92 | adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev, |
93 | adev->pdev, kfd2kgd); | |
130e0371 OG |
94 | } |
95 | ||
22cb0164 AD |
96 | /** |
97 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
98 | * setup amdkfd | |
99 | * | |
100 | * @adev: amdgpu_device pointer | |
101 | * @aperture_base: output returning doorbell aperture base physical address | |
102 | * @aperture_size: output returning doorbell aperture size in bytes | |
103 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
104 | * | |
105 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
106 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
107 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
108 | */ | |
109 | static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
110 | phys_addr_t *aperture_base, | |
111 | size_t *aperture_size, | |
112 | size_t *start_offset) | |
113 | { | |
114 | /* | |
115 | * The first num_doorbells are used by amdgpu. | |
116 | * amdkfd takes whatever's left in the aperture. | |
117 | */ | |
118 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
119 | *aperture_base = adev->doorbell.base; | |
120 | *aperture_size = adev->doorbell.size; | |
121 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
122 | } else { | |
123 | *aperture_base = 0; | |
124 | *aperture_size = 0; | |
125 | *start_offset = 0; | |
126 | } | |
127 | } | |
128 | ||
dc102c43 | 129 | void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) |
130e0371 | 130 | { |
d0b63bb3 AR |
131 | int i; |
132 | int last_valid_bit; | |
dc102c43 | 133 | if (adev->kfd) { |
130e0371 OG |
134 | struct kgd2kfd_shared_resources gpu_resources = { |
135 | .compute_vmid_bitmap = 0xFF00, | |
d0b63bb3 AR |
136 | .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, |
137 | .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe | |
130e0371 OG |
138 | }; |
139 | ||
d0b63bb3 AR |
140 | /* this is going to have a few of the MSBs set that we need to |
141 | * clear */ | |
142 | bitmap_complement(gpu_resources.queue_bitmap, | |
143 | adev->gfx.mec.queue_bitmap, | |
144 | KGD_MAX_QUEUES); | |
145 | ||
7b2124a5 AR |
146 | /* remove the KIQ bit as well */ |
147 | if (adev->gfx.kiq.ring.ready) | |
2db0cdbe AD |
148 | clear_bit(amdgpu_gfx_queue_to_bit(adev, |
149 | adev->gfx.kiq.ring.me - 1, | |
150 | adev->gfx.kiq.ring.pipe, | |
151 | adev->gfx.kiq.ring.queue), | |
7b2124a5 AR |
152 | gpu_resources.queue_bitmap); |
153 | ||
d0b63bb3 AR |
154 | /* According to linux/bitmap.h we shouldn't use bitmap_clear if |
155 | * nbits is not compile time constant */ | |
3447d220 | 156 | last_valid_bit = 1 /* only first MEC can have compute queues */ |
d0b63bb3 AR |
157 | * adev->gfx.mec.num_pipe_per_mec |
158 | * adev->gfx.mec.num_queue_per_pipe; | |
159 | for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) | |
160 | clear_bit(i, gpu_resources.queue_bitmap); | |
161 | ||
dc102c43 | 162 | amdgpu_doorbell_get_kfd_info(adev, |
130e0371 OG |
163 | &gpu_resources.doorbell_physical_address, |
164 | &gpu_resources.doorbell_aperture_size, | |
165 | &gpu_resources.doorbell_start_offset); | |
166 | ||
dc102c43 | 167 | kgd2kfd->device_init(adev->kfd, &gpu_resources); |
130e0371 OG |
168 | } |
169 | } | |
170 | ||
dc102c43 | 171 | void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev) |
130e0371 | 172 | { |
dc102c43 AR |
173 | if (adev->kfd) { |
174 | kgd2kfd->device_exit(adev->kfd); | |
175 | adev->kfd = NULL; | |
130e0371 OG |
176 | } |
177 | } | |
178 | ||
dc102c43 | 179 | void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, |
130e0371 OG |
180 | const void *ih_ring_entry) |
181 | { | |
dc102c43 AR |
182 | if (adev->kfd) |
183 | kgd2kfd->interrupt(adev->kfd, ih_ring_entry); | |
130e0371 OG |
184 | } |
185 | ||
dc102c43 | 186 | void amdgpu_amdkfd_suspend(struct amdgpu_device *adev) |
130e0371 | 187 | { |
dc102c43 AR |
188 | if (adev->kfd) |
189 | kgd2kfd->suspend(adev->kfd); | |
130e0371 OG |
190 | } |
191 | ||
dc102c43 | 192 | int amdgpu_amdkfd_resume(struct amdgpu_device *adev) |
130e0371 OG |
193 | { |
194 | int r = 0; | |
195 | ||
dc102c43 AR |
196 | if (adev->kfd) |
197 | r = kgd2kfd->resume(adev->kfd); | |
130e0371 OG |
198 | |
199 | return r; | |
200 | } | |
201 | ||
130e0371 OG |
202 | int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, |
203 | void **mem_obj, uint64_t *gpu_addr, | |
204 | void **cpu_ptr) | |
205 | { | |
dc102c43 | 206 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; |
130e0371 OG |
207 | struct kgd_mem **mem = (struct kgd_mem **) mem_obj; |
208 | int r; | |
209 | ||
210 | BUG_ON(kgd == NULL); | |
211 | BUG_ON(gpu_addr == NULL); | |
212 | BUG_ON(cpu_ptr == NULL); | |
213 | ||
214 | *mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL); | |
215 | if ((*mem) == NULL) | |
216 | return -ENOMEM; | |
217 | ||
dc102c43 | 218 | r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, |
2046d46d YZ |
219 | AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, 0, |
220 | &(*mem)->bo); | |
130e0371 | 221 | if (r) { |
dc102c43 | 222 | dev_err(adev->dev, |
130e0371 OG |
223 | "failed to allocate BO for amdkfd (%d)\n", r); |
224 | return r; | |
225 | } | |
226 | ||
227 | /* map the buffer */ | |
228 | r = amdgpu_bo_reserve((*mem)->bo, true); | |
229 | if (r) { | |
dc102c43 | 230 | dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); |
130e0371 OG |
231 | goto allocate_mem_reserve_bo_failed; |
232 | } | |
233 | ||
234 | r = amdgpu_bo_pin((*mem)->bo, AMDGPU_GEM_DOMAIN_GTT, | |
235 | &(*mem)->gpu_addr); | |
236 | if (r) { | |
dc102c43 | 237 | dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); |
130e0371 OG |
238 | goto allocate_mem_pin_bo_failed; |
239 | } | |
240 | *gpu_addr = (*mem)->gpu_addr; | |
241 | ||
242 | r = amdgpu_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr); | |
243 | if (r) { | |
dc102c43 | 244 | dev_err(adev->dev, |
130e0371 OG |
245 | "(%d) failed to map bo to kernel for amdkfd\n", r); |
246 | goto allocate_mem_kmap_bo_failed; | |
247 | } | |
248 | *cpu_ptr = (*mem)->cpu_ptr; | |
249 | ||
250 | amdgpu_bo_unreserve((*mem)->bo); | |
251 | ||
252 | return 0; | |
253 | ||
254 | allocate_mem_kmap_bo_failed: | |
255 | amdgpu_bo_unpin((*mem)->bo); | |
256 | allocate_mem_pin_bo_failed: | |
257 | amdgpu_bo_unreserve((*mem)->bo); | |
258 | allocate_mem_reserve_bo_failed: | |
259 | amdgpu_bo_unref(&(*mem)->bo); | |
260 | ||
261 | return r; | |
262 | } | |
263 | ||
264 | void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) | |
265 | { | |
266 | struct kgd_mem *mem = (struct kgd_mem *) mem_obj; | |
267 | ||
268 | BUG_ON(mem == NULL); | |
269 | ||
270 | amdgpu_bo_reserve(mem->bo, true); | |
271 | amdgpu_bo_kunmap(mem->bo); | |
272 | amdgpu_bo_unpin(mem->bo); | |
273 | amdgpu_bo_unreserve(mem->bo); | |
274 | amdgpu_bo_unref(&(mem->bo)); | |
275 | kfree(mem); | |
276 | } | |
277 | ||
278 | uint64_t get_vmem_size(struct kgd_dev *kgd) | |
279 | { | |
dc102c43 | 280 | struct amdgpu_device *adev = |
130e0371 OG |
281 | (struct amdgpu_device *)kgd; |
282 | ||
283 | BUG_ON(kgd == NULL); | |
284 | ||
dc102c43 | 285 | return adev->mc.real_vram_size; |
130e0371 OG |
286 | } |
287 | ||
288 | uint64_t get_gpu_clock_counter(struct kgd_dev *kgd) | |
289 | { | |
dc102c43 | 290 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; |
130e0371 | 291 | |
dc102c43 AR |
292 | if (adev->gfx.funcs->get_gpu_clock_counter) |
293 | return adev->gfx.funcs->get_gpu_clock_counter(adev); | |
130e0371 OG |
294 | return 0; |
295 | } | |
296 | ||
297 | uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd) | |
298 | { | |
dc102c43 | 299 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; |
130e0371 | 300 | |
a9efcc19 FK |
301 | /* the sclk is in quantas of 10kHz */ |
302 | if (amdgpu_sriov_vf(adev)) | |
303 | return adev->clock.default_sclk / 100; | |
304 | ||
305 | return amdgpu_dpm_get_sclk(adev, false) / 100; | |
130e0371 | 306 | } |
ebdebf42 FC |
307 | |
308 | void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) | |
309 | { | |
310 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; | |
311 | struct amdgpu_cu_info acu_info = adev->gfx.cu_info; | |
312 | ||
313 | memset(cu_info, 0, sizeof(*cu_info)); | |
314 | if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) | |
315 | return; | |
316 | ||
317 | cu_info->cu_active_number = acu_info.number; | |
318 | cu_info->cu_ao_mask = acu_info.ao_cu_mask; | |
319 | memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], | |
320 | sizeof(acu_info.bitmap)); | |
321 | cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; | |
322 | cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; | |
323 | cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; | |
324 | cu_info->simd_per_cu = acu_info.simd_per_cu; | |
325 | cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; | |
326 | cu_info->wave_front_size = acu_info.wave_front_size; | |
327 | cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; | |
328 | cu_info->lds_size = acu_info.lds_size; | |
329 | } |