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Commit | Line | Data |
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130e0371 OG |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #include "amdgpu_amdkfd.h" | |
2f7d10b3 | 24 | #include "amd_shared.h" |
130e0371 OG |
25 | #include <drm/drmP.h> |
26 | #include "amdgpu.h" | |
2db0cdbe | 27 | #include "amdgpu_gfx.h" |
130e0371 | 28 | #include <linux/module.h> |
1dde0ea9 | 29 | #include <linux/dma-buf.h> |
130e0371 | 30 | |
155494db FK |
31 | static const unsigned int compute_vmid_bitmap = 0xFF00; |
32 | ||
611736d8 FK |
33 | /* Total memory size in system memory and all GPU VRAM. Used to |
34 | * estimate worst case amount of memory to reserve for page tables | |
35 | */ | |
36 | uint64_t amdgpu_amdkfd_total_mem_size; | |
37 | ||
efb1c658 | 38 | int amdgpu_amdkfd_init(void) |
130e0371 | 39 | { |
611736d8 | 40 | struct sysinfo si; |
efb1c658 OG |
41 | int ret; |
42 | ||
611736d8 FK |
43 | si_meminfo(&si); |
44 | amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh; | |
45 | amdgpu_amdkfd_total_mem_size *= si.mem_unit; | |
46 | ||
82b7b619 | 47 | #ifdef CONFIG_HSA_AMD |
308176d6 | 48 | ret = kgd2kfd_init(); |
82b7b619 | 49 | amdgpu_amdkfd_gpuvm_init_mem_limits(); |
efb1c658 OG |
50 | #else |
51 | ret = -ENOENT; | |
130e0371 | 52 | #endif |
fcdfa432 | 53 | |
efb1c658 | 54 | return ret; |
130e0371 OG |
55 | } |
56 | ||
5c33f214 FK |
57 | void amdgpu_amdkfd_fini(void) |
58 | { | |
8e07e267 | 59 | kgd2kfd_exit(); |
5c33f214 FK |
60 | } |
61 | ||
62 | void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) | |
130e0371 | 63 | { |
5c33f214 FK |
64 | const struct kfd2kgd_calls *kfd2kgd; |
65 | ||
dc102c43 | 66 | switch (adev->asic_type) { |
41548ef7 | 67 | #ifdef CONFIG_DRM_AMDGPU_CIK |
130e0371 | 68 | case CHIP_KAVERI: |
30d13424 | 69 | case CHIP_HAWAII: |
32c22e99 OG |
70 | kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions(); |
71 | break; | |
41548ef7 | 72 | #endif |
ff758a12 | 73 | case CHIP_CARRIZO: |
30d13424 FK |
74 | case CHIP_TONGA: |
75 | case CHIP_FIJI: | |
76 | case CHIP_POLARIS10: | |
77 | case CHIP_POLARIS11: | |
846a44d7 | 78 | case CHIP_POLARIS12: |
ff758a12 BG |
79 | kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions(); |
80 | break; | |
d5a114a6 | 81 | case CHIP_VEGA10: |
846a44d7 | 82 | case CHIP_VEGA12: |
ba0f2841 | 83 | case CHIP_VEGA20: |
d5a114a6 FK |
84 | case CHIP_RAVEN: |
85 | kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions(); | |
86 | break; | |
130e0371 | 87 | default: |
c3032fd9 | 88 | dev_info(adev->dev, "kfd not supported on this ASIC\n"); |
5c33f214 | 89 | return; |
130e0371 OG |
90 | } |
91 | ||
8e07e267 AL |
92 | adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, |
93 | adev->pdev, kfd2kgd); | |
611736d8 FK |
94 | |
95 | if (adev->kfd.dev) | |
96 | amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; | |
130e0371 OG |
97 | } |
98 | ||
22cb0164 AD |
99 | /** |
100 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
101 | * setup amdkfd | |
102 | * | |
103 | * @adev: amdgpu_device pointer | |
104 | * @aperture_base: output returning doorbell aperture base physical address | |
105 | * @aperture_size: output returning doorbell aperture size in bytes | |
106 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
107 | * | |
108 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
109 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
110 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
111 | */ | |
112 | static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
113 | phys_addr_t *aperture_base, | |
114 | size_t *aperture_size, | |
115 | size_t *start_offset) | |
116 | { | |
117 | /* | |
118 | * The first num_doorbells are used by amdgpu. | |
119 | * amdkfd takes whatever's left in the aperture. | |
120 | */ | |
121 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
122 | *aperture_base = adev->doorbell.base; | |
123 | *aperture_size = adev->doorbell.size; | |
124 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
125 | } else { | |
126 | *aperture_base = 0; | |
127 | *aperture_size = 0; | |
128 | *start_offset = 0; | |
129 | } | |
130 | } | |
131 | ||
dc102c43 | 132 | void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) |
130e0371 | 133 | { |
234441dd | 134 | int i; |
d0b63bb3 | 135 | int last_valid_bit; |
611736d8 FK |
136 | |
137 | if (adev->kfd.dev) { | |
130e0371 | 138 | struct kgd2kfd_shared_resources gpu_resources = { |
155494db | 139 | .compute_vmid_bitmap = compute_vmid_bitmap, |
d0b63bb3 | 140 | .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, |
155494db FK |
141 | .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, |
142 | .gpuvm_size = min(adev->vm_manager.max_pfn | |
143 | << AMDGPU_GPU_PAGE_SHIFT, | |
ad9a5b78 | 144 | AMDGPU_GMC_HOLE_START), |
234441dd YZ |
145 | .drm_render_minor = adev->ddev->render->index, |
146 | .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, | |
147 | ||
130e0371 OG |
148 | }; |
149 | ||
d0b63bb3 AR |
150 | /* this is going to have a few of the MSBs set that we need to |
151 | * clear */ | |
152 | bitmap_complement(gpu_resources.queue_bitmap, | |
153 | adev->gfx.mec.queue_bitmap, | |
154 | KGD_MAX_QUEUES); | |
155 | ||
7b2124a5 | 156 | /* remove the KIQ bit as well */ |
c66ed765 | 157 | if (adev->gfx.kiq.ring.sched.ready) |
2db0cdbe AD |
158 | clear_bit(amdgpu_gfx_queue_to_bit(adev, |
159 | adev->gfx.kiq.ring.me - 1, | |
160 | adev->gfx.kiq.ring.pipe, | |
161 | adev->gfx.kiq.ring.queue), | |
7b2124a5 AR |
162 | gpu_resources.queue_bitmap); |
163 | ||
d0b63bb3 AR |
164 | /* According to linux/bitmap.h we shouldn't use bitmap_clear if |
165 | * nbits is not compile time constant */ | |
3447d220 | 166 | last_valid_bit = 1 /* only first MEC can have compute queues */ |
d0b63bb3 AR |
167 | * adev->gfx.mec.num_pipe_per_mec |
168 | * adev->gfx.mec.num_queue_per_pipe; | |
169 | for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) | |
170 | clear_bit(i, gpu_resources.queue_bitmap); | |
171 | ||
dc102c43 | 172 | amdgpu_doorbell_get_kfd_info(adev, |
130e0371 OG |
173 | &gpu_resources.doorbell_physical_address, |
174 | &gpu_resources.doorbell_aperture_size, | |
175 | &gpu_resources.doorbell_start_offset); | |
c5892230 | 176 | |
1f86805a YZ |
177 | /* Since SOC15, BIF starts to statically use the |
178 | * lower 12 bits of doorbell addresses for routing | |
179 | * based on settings in registers like | |
180 | * SDMA0_DOORBELL_RANGE etc.. | |
181 | * In order to route a doorbell to CP engine, the lower | |
182 | * 12 bits of its address has to be outside the range | |
183 | * set for SDMA, VCN, and IH blocks. | |
c5892230 | 184 | */ |
234441dd YZ |
185 | if (adev->asic_type >= CHIP_VEGA10) { |
186 | gpu_resources.non_cp_doorbells_start = | |
187 | adev->doorbell_index.first_non_cp; | |
188 | gpu_resources.non_cp_doorbells_end = | |
189 | adev->doorbell_index.last_non_cp; | |
190 | } | |
130e0371 | 191 | |
8e07e267 | 192 | kgd2kfd_device_init(adev->kfd.dev, &gpu_resources); |
130e0371 OG |
193 | } |
194 | } | |
195 | ||
dc102c43 | 196 | void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev) |
130e0371 | 197 | { |
611736d8 | 198 | if (adev->kfd.dev) { |
8e07e267 | 199 | kgd2kfd_device_exit(adev->kfd.dev); |
611736d8 | 200 | adev->kfd.dev = NULL; |
130e0371 OG |
201 | } |
202 | } | |
203 | ||
dc102c43 | 204 | void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, |
130e0371 OG |
205 | const void *ih_ring_entry) |
206 | { | |
611736d8 | 207 | if (adev->kfd.dev) |
8e07e267 | 208 | kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); |
130e0371 OG |
209 | } |
210 | ||
dc102c43 | 211 | void amdgpu_amdkfd_suspend(struct amdgpu_device *adev) |
130e0371 | 212 | { |
611736d8 | 213 | if (adev->kfd.dev) |
8e07e267 | 214 | kgd2kfd_suspend(adev->kfd.dev); |
130e0371 OG |
215 | } |
216 | ||
dc102c43 | 217 | int amdgpu_amdkfd_resume(struct amdgpu_device *adev) |
130e0371 OG |
218 | { |
219 | int r = 0; | |
220 | ||
611736d8 | 221 | if (adev->kfd.dev) |
8e07e267 | 222 | r = kgd2kfd_resume(adev->kfd.dev); |
130e0371 OG |
223 | |
224 | return r; | |
225 | } | |
226 | ||
5c6dd71e SL |
227 | int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) |
228 | { | |
229 | int r = 0; | |
230 | ||
611736d8 | 231 | if (adev->kfd.dev) |
8e07e267 | 232 | r = kgd2kfd_pre_reset(adev->kfd.dev); |
5c6dd71e SL |
233 | |
234 | return r; | |
235 | } | |
236 | ||
237 | int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) | |
238 | { | |
239 | int r = 0; | |
240 | ||
611736d8 | 241 | if (adev->kfd.dev) |
8e07e267 | 242 | r = kgd2kfd_post_reset(adev->kfd.dev); |
5c6dd71e SL |
243 | |
244 | return r; | |
245 | } | |
246 | ||
24da5a9c SL |
247 | void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd) |
248 | { | |
249 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; | |
250 | ||
12938fad CK |
251 | if (amdgpu_device_should_recover_gpu(adev)) |
252 | amdgpu_device_gpu_recover(adev, NULL); | |
24da5a9c SL |
253 | } |
254 | ||
7cd52c91 AL |
255 | int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, |
256 | void **mem_obj, uint64_t *gpu_addr, | |
257 | void **cpu_ptr, bool mqd_gfx9) | |
130e0371 | 258 | { |
dc102c43 | 259 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; |
473fee47 | 260 | struct amdgpu_bo *bo = NULL; |
3216c6b7 | 261 | struct amdgpu_bo_param bp; |
130e0371 | 262 | int r; |
473fee47 | 263 | void *cpu_ptr_tmp = NULL; |
130e0371 | 264 | |
3216c6b7 CZ |
265 | memset(&bp, 0, sizeof(bp)); |
266 | bp.size = size; | |
267 | bp.byte_align = PAGE_SIZE; | |
268 | bp.domain = AMDGPU_GEM_DOMAIN_GTT; | |
269 | bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; | |
270 | bp.type = ttm_bo_type_kernel; | |
271 | bp.resv = NULL; | |
15426dbb YZ |
272 | |
273 | if (mqd_gfx9) | |
274 | bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9; | |
275 | ||
3216c6b7 | 276 | r = amdgpu_bo_create(adev, &bp, &bo); |
130e0371 | 277 | if (r) { |
dc102c43 | 278 | dev_err(adev->dev, |
130e0371 OG |
279 | "failed to allocate BO for amdkfd (%d)\n", r); |
280 | return r; | |
281 | } | |
282 | ||
283 | /* map the buffer */ | |
473fee47 | 284 | r = amdgpu_bo_reserve(bo, true); |
130e0371 | 285 | if (r) { |
dc102c43 | 286 | dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); |
130e0371 OG |
287 | goto allocate_mem_reserve_bo_failed; |
288 | } | |
289 | ||
7b7c6c81 | 290 | r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); |
130e0371 | 291 | if (r) { |
dc102c43 | 292 | dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); |
130e0371 OG |
293 | goto allocate_mem_pin_bo_failed; |
294 | } | |
130e0371 | 295 | |
bb812f1e JZ |
296 | r = amdgpu_ttm_alloc_gart(&bo->tbo); |
297 | if (r) { | |
298 | dev_err(adev->dev, "%p bind failed\n", bo); | |
299 | goto allocate_mem_kmap_bo_failed; | |
300 | } | |
301 | ||
473fee47 | 302 | r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); |
130e0371 | 303 | if (r) { |
dc102c43 | 304 | dev_err(adev->dev, |
130e0371 OG |
305 | "(%d) failed to map bo to kernel for amdkfd\n", r); |
306 | goto allocate_mem_kmap_bo_failed; | |
307 | } | |
130e0371 | 308 | |
473fee47 | 309 | *mem_obj = bo; |
7b7c6c81 | 310 | *gpu_addr = amdgpu_bo_gpu_offset(bo); |
473fee47 YZ |
311 | *cpu_ptr = cpu_ptr_tmp; |
312 | ||
313 | amdgpu_bo_unreserve(bo); | |
130e0371 OG |
314 | |
315 | return 0; | |
316 | ||
317 | allocate_mem_kmap_bo_failed: | |
473fee47 | 318 | amdgpu_bo_unpin(bo); |
130e0371 | 319 | allocate_mem_pin_bo_failed: |
473fee47 | 320 | amdgpu_bo_unreserve(bo); |
130e0371 | 321 | allocate_mem_reserve_bo_failed: |
473fee47 | 322 | amdgpu_bo_unref(&bo); |
130e0371 OG |
323 | |
324 | return r; | |
325 | } | |
326 | ||
7cd52c91 | 327 | void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) |
130e0371 | 328 | { |
473fee47 YZ |
329 | struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; |
330 | ||
331 | amdgpu_bo_reserve(bo, true); | |
332 | amdgpu_bo_kunmap(bo); | |
333 | amdgpu_bo_unpin(bo); | |
334 | amdgpu_bo_unreserve(bo); | |
335 | amdgpu_bo_unref(&(bo)); | |
130e0371 OG |
336 | } |
337 | ||
7cd52c91 AL |
338 | void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, |
339 | struct kfd_local_mem_info *mem_info) | |
30f1c042 HK |
340 | { |
341 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; | |
342 | uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask : | |
343 | ~((1ULL << 32) - 1); | |
770d13b1 | 344 | resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size; |
30f1c042 HK |
345 | |
346 | memset(mem_info, 0, sizeof(*mem_info)); | |
770d13b1 CK |
347 | if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) { |
348 | mem_info->local_mem_size_public = adev->gmc.visible_vram_size; | |
349 | mem_info->local_mem_size_private = adev->gmc.real_vram_size - | |
350 | adev->gmc.visible_vram_size; | |
30f1c042 HK |
351 | } else { |
352 | mem_info->local_mem_size_public = 0; | |
770d13b1 | 353 | mem_info->local_mem_size_private = adev->gmc.real_vram_size; |
30f1c042 | 354 | } |
770d13b1 | 355 | mem_info->vram_width = adev->gmc.vram_width; |
30f1c042 | 356 | |
fb8baefc | 357 | pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n", |
770d13b1 | 358 | &adev->gmc.aper_base, &aper_limit, |
30f1c042 HK |
359 | mem_info->local_mem_size_public, |
360 | mem_info->local_mem_size_private); | |
361 | ||
362 | if (amdgpu_sriov_vf(adev)) | |
363 | mem_info->mem_clk_max = adev->clock.default_mclk / 100; | |
7ba01f9e | 364 | else if (adev->powerplay.pp_funcs) |
30f1c042 | 365 | mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; |
7ba01f9e SL |
366 | else |
367 | mem_info->mem_clk_max = 100; | |
30f1c042 HK |
368 | } |
369 | ||
7cd52c91 | 370 | uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd) |
130e0371 | 371 | { |
dc102c43 | 372 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; |
130e0371 | 373 | |
dc102c43 AR |
374 | if (adev->gfx.funcs->get_gpu_clock_counter) |
375 | return adev->gfx.funcs->get_gpu_clock_counter(adev); | |
130e0371 OG |
376 | return 0; |
377 | } | |
378 | ||
7cd52c91 | 379 | uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd) |
130e0371 | 380 | { |
dc102c43 | 381 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; |
130e0371 | 382 | |
a9efcc19 FK |
383 | /* the sclk is in quantas of 10kHz */ |
384 | if (amdgpu_sriov_vf(adev)) | |
385 | return adev->clock.default_sclk / 100; | |
7ba01f9e SL |
386 | else if (adev->powerplay.pp_funcs) |
387 | return amdgpu_dpm_get_sclk(adev, false) / 100; | |
388 | else | |
389 | return 100; | |
130e0371 | 390 | } |
ebdebf42 | 391 | |
7cd52c91 | 392 | void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) |
ebdebf42 FC |
393 | { |
394 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; | |
395 | struct amdgpu_cu_info acu_info = adev->gfx.cu_info; | |
396 | ||
397 | memset(cu_info, 0, sizeof(*cu_info)); | |
398 | if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) | |
399 | return; | |
400 | ||
401 | cu_info->cu_active_number = acu_info.number; | |
402 | cu_info->cu_ao_mask = acu_info.ao_cu_mask; | |
403 | memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], | |
404 | sizeof(acu_info.bitmap)); | |
405 | cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; | |
406 | cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; | |
407 | cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; | |
408 | cu_info->simd_per_cu = acu_info.simd_per_cu; | |
409 | cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; | |
410 | cu_info->wave_front_size = acu_info.wave_front_size; | |
411 | cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; | |
412 | cu_info->lds_size = acu_info.lds_size; | |
413 | } | |
9f0a0b41 | 414 | |
1dde0ea9 FK |
415 | int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, |
416 | struct kgd_dev **dma_buf_kgd, | |
417 | uint64_t *bo_size, void *metadata_buffer, | |
418 | size_t buffer_size, uint32_t *metadata_size, | |
419 | uint32_t *flags) | |
420 | { | |
421 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; | |
422 | struct dma_buf *dma_buf; | |
423 | struct drm_gem_object *obj; | |
424 | struct amdgpu_bo *bo; | |
425 | uint64_t metadata_flags; | |
426 | int r = -EINVAL; | |
427 | ||
428 | dma_buf = dma_buf_get(dma_buf_fd); | |
429 | if (IS_ERR(dma_buf)) | |
430 | return PTR_ERR(dma_buf); | |
431 | ||
432 | if (dma_buf->ops != &amdgpu_dmabuf_ops) | |
433 | /* Can't handle non-graphics buffers */ | |
434 | goto out_put; | |
435 | ||
436 | obj = dma_buf->priv; | |
437 | if (obj->dev->driver != adev->ddev->driver) | |
438 | /* Can't handle buffers from different drivers */ | |
439 | goto out_put; | |
440 | ||
441 | adev = obj->dev->dev_private; | |
442 | bo = gem_to_amdgpu_bo(obj); | |
443 | if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | | |
444 | AMDGPU_GEM_DOMAIN_GTT))) | |
445 | /* Only VRAM and GTT BOs are supported */ | |
446 | goto out_put; | |
447 | ||
448 | r = 0; | |
449 | if (dma_buf_kgd) | |
450 | *dma_buf_kgd = (struct kgd_dev *)adev; | |
451 | if (bo_size) | |
452 | *bo_size = amdgpu_bo_size(bo); | |
453 | if (metadata_size) | |
454 | *metadata_size = bo->metadata_size; | |
455 | if (metadata_buffer) | |
456 | r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, | |
457 | metadata_size, &metadata_flags); | |
458 | if (flags) { | |
459 | *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? | |
460 | ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT; | |
461 | ||
462 | if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) | |
463 | *flags |= ALLOC_MEM_FLAGS_PUBLIC; | |
464 | } | |
465 | ||
466 | out_put: | |
467 | dma_buf_put(dma_buf); | |
468 | return r; | |
469 | } | |
470 | ||
9f0a0b41 KR |
471 | uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd) |
472 | { | |
473 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; | |
474 | ||
475 | return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); | |
476 | } | |
155494db | 477 | |
db8b62c0 SL |
478 | uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd) |
479 | { | |
480 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; | |
481 | ||
482 | return adev->gmc.xgmi.hive_id; | |
483 | } | |
484 | ||
4c660c8f FK |
485 | int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, |
486 | uint32_t vmid, uint64_t gpu_addr, | |
487 | uint32_t *ib_cmd, uint32_t ib_len) | |
488 | { | |
489 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; | |
490 | struct amdgpu_job *job; | |
491 | struct amdgpu_ib *ib; | |
492 | struct amdgpu_ring *ring; | |
493 | struct dma_fence *f = NULL; | |
494 | int ret; | |
495 | ||
496 | switch (engine) { | |
497 | case KGD_ENGINE_MEC1: | |
498 | ring = &adev->gfx.compute_ring[0]; | |
499 | break; | |
500 | case KGD_ENGINE_SDMA1: | |
501 | ring = &adev->sdma.instance[0].ring; | |
502 | break; | |
503 | case KGD_ENGINE_SDMA2: | |
504 | ring = &adev->sdma.instance[1].ring; | |
505 | break; | |
506 | default: | |
507 | pr_err("Invalid engine in IB submission: %d\n", engine); | |
508 | ret = -EINVAL; | |
509 | goto err; | |
510 | } | |
511 | ||
512 | ret = amdgpu_job_alloc(adev, 1, &job, NULL); | |
513 | if (ret) | |
514 | goto err; | |
515 | ||
516 | ib = &job->ibs[0]; | |
517 | memset(ib, 0, sizeof(struct amdgpu_ib)); | |
518 | ||
519 | ib->gpu_addr = gpu_addr; | |
520 | ib->ptr = ib_cmd; | |
521 | ib->length_dw = ib_len; | |
522 | /* This works for NO_HWS. TODO: need to handle without knowing VMID */ | |
523 | job->vmid = vmid; | |
524 | ||
525 | ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); | |
526 | if (ret) { | |
527 | DRM_ERROR("amdgpu: failed to schedule IB.\n"); | |
528 | goto err_ib_sched; | |
529 | } | |
530 | ||
531 | ret = dma_fence_wait(f, false); | |
532 | ||
533 | err_ib_sched: | |
534 | dma_fence_put(f); | |
535 | amdgpu_job_free(job); | |
536 | err: | |
537 | return ret; | |
538 | } | |
539 | ||
01c097db FK |
540 | void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) |
541 | { | |
542 | struct amdgpu_device *adev = (struct amdgpu_device *)kgd; | |
543 | ||
919a52fc FK |
544 | if (adev->powerplay.pp_funcs && |
545 | adev->powerplay.pp_funcs->switch_power_profile) | |
546 | amdgpu_dpm_switch_power_profile(adev, | |
547 | PP_SMC_POWER_PROFILE_COMPUTE, | |
548 | !idle); | |
01c097db FK |
549 | } |
550 | ||
155494db FK |
551 | bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) |
552 | { | |
611736d8 | 553 | if (adev->kfd.dev) { |
155494db FK |
554 | if ((1 << vmid) & compute_vmid_bitmap) |
555 | return true; | |
556 | } | |
557 | ||
558 | return false; | |
559 | } | |
fcdfa432 | 560 | |
82b7b619 | 561 | #ifndef CONFIG_HSA_AMD |
fcdfa432 OG |
562 | bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) |
563 | { | |
564 | return false; | |
565 | } | |
566 | ||
4f01b73e | 567 | void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo) |
fcdfa432 OG |
568 | { |
569 | } | |
570 | ||
571 | void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, | |
572 | struct amdgpu_vm *vm) | |
573 | { | |
574 | } | |
575 | ||
576 | struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) | |
577 | { | |
578 | return NULL; | |
579 | } | |
580 | ||
581 | int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) | |
582 | { | |
583 | return 0; | |
584 | } | |
585 | ||
586 | struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void) | |
587 | { | |
588 | return NULL; | |
589 | } | |
590 | ||
591 | struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void) | |
592 | { | |
593 | return NULL; | |
594 | } | |
595 | ||
596 | struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void) | |
597 | { | |
598 | return NULL; | |
599 | } | |
2d3d25b6 AL |
600 | |
601 | struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, | |
602 | const struct kfd2kgd_calls *f2g) | |
603 | { | |
604 | return NULL; | |
605 | } | |
606 | ||
607 | bool kgd2kfd_device_init(struct kfd_dev *kfd, | |
608 | const struct kgd2kfd_shared_resources *gpu_resources) | |
609 | { | |
610 | return false; | |
611 | } | |
612 | ||
613 | void kgd2kfd_device_exit(struct kfd_dev *kfd) | |
614 | { | |
615 | } | |
616 | ||
617 | void kgd2kfd_exit(void) | |
618 | { | |
619 | } | |
620 | ||
621 | void kgd2kfd_suspend(struct kfd_dev *kfd) | |
622 | { | |
623 | } | |
624 | ||
625 | int kgd2kfd_resume(struct kfd_dev *kfd) | |
626 | { | |
627 | return 0; | |
628 | } | |
629 | ||
630 | int kgd2kfd_pre_reset(struct kfd_dev *kfd) | |
631 | { | |
632 | return 0; | |
633 | } | |
634 | ||
635 | int kgd2kfd_post_reset(struct kfd_dev *kfd) | |
636 | { | |
637 | return 0; | |
638 | } | |
639 | ||
640 | void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) | |
641 | { | |
642 | } | |
9b54d201 EH |
643 | |
644 | void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) | |
645 | { | |
646 | } | |
fcdfa432 | 647 | #endif |