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32c22e99 OG |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #include <linux/fdtable.h> | |
24 | #include <linux/uaccess.h> | |
25 | #include <linux/firmware.h> | |
26 | #include <drm/drmP.h> | |
27 | #include "amdgpu.h" | |
28 | #include "amdgpu_amdkfd.h" | |
29 | #include "cikd.h" | |
30 | #include "cik_sdma.h" | |
31 | #include "amdgpu_ucode.h" | |
32 | #include "gca/gfx_7_2_d.h" | |
33 | #include "gca/gfx_7_2_enum.h" | |
34 | #include "gca/gfx_7_2_sh_mask.h" | |
35 | #include "oss/oss_2_0_d.h" | |
36 | #include "oss/oss_2_0_sh_mask.h" | |
37 | #include "gmc/gmc_7_1_d.h" | |
38 | #include "gmc/gmc_7_1_sh_mask.h" | |
39 | #include "cik_structs.h" | |
40 | ||
41 | #define CIK_PIPE_PER_MEC (4) | |
42 | ||
43 | enum { | |
44 | MAX_TRAPID = 8, /* 3 bits in the bitfield. */ | |
45 | MAX_WATCH_ADDRESSES = 4 | |
46 | }; | |
47 | ||
48 | enum { | |
49 | ADDRESS_WATCH_REG_ADDR_HI = 0, | |
50 | ADDRESS_WATCH_REG_ADDR_LO, | |
51 | ADDRESS_WATCH_REG_CNTL, | |
52 | ADDRESS_WATCH_REG_MAX | |
53 | }; | |
54 | ||
55 | /* not defined in the CI/KV reg file */ | |
56 | enum { | |
57 | ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL, | |
58 | ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF, | |
59 | ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000, | |
60 | /* extend the mask to 26 bits to match the low address field */ | |
61 | ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6, | |
62 | ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF | |
63 | }; | |
64 | ||
65 | static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = { | |
66 | mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL, | |
67 | mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL, | |
68 | mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL, | |
69 | mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL | |
70 | }; | |
71 | ||
72 | union TCP_WATCH_CNTL_BITS { | |
73 | struct { | |
74 | uint32_t mask:24; | |
75 | uint32_t vmid:4; | |
76 | uint32_t atc:1; | |
77 | uint32_t mode:2; | |
78 | uint32_t valid:1; | |
79 | } bitfields, bits; | |
80 | uint32_t u32All; | |
81 | signed int i32All; | |
82 | float f32All; | |
83 | }; | |
84 | ||
85 | /* | |
86 | * Register access functions | |
87 | */ | |
88 | ||
89 | static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, | |
90 | uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, | |
91 | uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases); | |
92 | ||
93 | static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, | |
94 | unsigned int vmid); | |
95 | ||
96 | static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, | |
97 | uint32_t hpd_size, uint64_t hpd_gpu_addr); | |
98 | static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); | |
99 | static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, | |
100 | uint32_t queue_id, uint32_t __user *wptr); | |
101 | static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); | |
102 | static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, | |
103 | uint32_t pipe_id, uint32_t queue_id); | |
104 | ||
105 | static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, | |
1d602430 | 106 | unsigned int utimeout, uint32_t pipe_id, |
32c22e99 OG |
107 | uint32_t queue_id); |
108 | static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); | |
109 | static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, | |
1d602430 | 110 | unsigned int utimeout); |
32c22e99 OG |
111 | static int kgd_address_watch_disable(struct kgd_dev *kgd); |
112 | static int kgd_address_watch_execute(struct kgd_dev *kgd, | |
113 | unsigned int watch_point_id, | |
114 | uint32_t cntl_val, | |
115 | uint32_t addr_hi, | |
116 | uint32_t addr_lo); | |
117 | static int kgd_wave_control_execute(struct kgd_dev *kgd, | |
118 | uint32_t gfx_index_val, | |
119 | uint32_t sq_cmd); | |
120 | static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, | |
121 | unsigned int watch_point_id, | |
122 | unsigned int reg_offset); | |
123 | ||
124 | static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid); | |
125 | static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, | |
126 | uint8_t vmid); | |
127 | static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid); | |
128 | ||
129 | static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); | |
130 | ||
131 | static const struct kfd2kgd_calls kfd2kgd = { | |
132 | .init_gtt_mem_allocation = alloc_gtt_mem, | |
133 | .free_gtt_mem = free_gtt_mem, | |
134 | .get_vmem_size = get_vmem_size, | |
135 | .get_gpu_clock_counter = get_gpu_clock_counter, | |
136 | .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, | |
137 | .program_sh_mem_settings = kgd_program_sh_mem_settings, | |
138 | .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, | |
139 | .init_pipeline = kgd_init_pipeline, | |
140 | .init_interrupts = kgd_init_interrupts, | |
141 | .hqd_load = kgd_hqd_load, | |
142 | .hqd_sdma_load = kgd_hqd_sdma_load, | |
143 | .hqd_is_occupied = kgd_hqd_is_occupied, | |
144 | .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, | |
145 | .hqd_destroy = kgd_hqd_destroy, | |
146 | .hqd_sdma_destroy = kgd_hqd_sdma_destroy, | |
147 | .address_watch_disable = kgd_address_watch_disable, | |
148 | .address_watch_execute = kgd_address_watch_execute, | |
149 | .wave_control_execute = kgd_wave_control_execute, | |
150 | .address_watch_get_offset = kgd_address_watch_get_offset, | |
151 | .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid, | |
152 | .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid, | |
153 | .write_vmid_invalidate_request = write_vmid_invalidate_request, | |
154 | .get_fw_version = get_fw_version | |
155 | }; | |
156 | ||
f785d987 | 157 | struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void) |
32c22e99 OG |
158 | { |
159 | return (struct kfd2kgd_calls *)&kfd2kgd; | |
160 | } | |
161 | ||
162 | static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) | |
163 | { | |
164 | return (struct amdgpu_device *)kgd; | |
165 | } | |
166 | ||
167 | static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, | |
168 | uint32_t queue, uint32_t vmid) | |
169 | { | |
170 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
171 | uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); | |
172 | ||
173 | mutex_lock(&adev->srbm_mutex); | |
174 | WREG32(mmSRBM_GFX_CNTL, value); | |
175 | } | |
176 | ||
177 | static void unlock_srbm(struct kgd_dev *kgd) | |
178 | { | |
179 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
180 | ||
181 | WREG32(mmSRBM_GFX_CNTL, 0); | |
182 | mutex_unlock(&adev->srbm_mutex); | |
183 | } | |
184 | ||
185 | static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, | |
186 | uint32_t queue_id) | |
187 | { | |
188 | uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1; | |
189 | uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC); | |
190 | ||
191 | lock_srbm(kgd, mec, pipe, queue_id, 0); | |
192 | } | |
193 | ||
194 | static void release_queue(struct kgd_dev *kgd) | |
195 | { | |
196 | unlock_srbm(kgd); | |
197 | } | |
198 | ||
199 | static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, | |
200 | uint32_t sh_mem_config, | |
201 | uint32_t sh_mem_ape1_base, | |
202 | uint32_t sh_mem_ape1_limit, | |
203 | uint32_t sh_mem_bases) | |
204 | { | |
205 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
206 | ||
207 | lock_srbm(kgd, 0, 0, 0, vmid); | |
208 | ||
209 | WREG32(mmSH_MEM_CONFIG, sh_mem_config); | |
210 | WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); | |
211 | WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); | |
212 | WREG32(mmSH_MEM_BASES, sh_mem_bases); | |
213 | ||
214 | unlock_srbm(kgd); | |
215 | } | |
216 | ||
217 | static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, | |
218 | unsigned int vmid) | |
219 | { | |
220 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
221 | ||
222 | /* | |
223 | * We have to assume that there is no outstanding mapping. | |
224 | * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because | |
225 | * a mapping is in progress or because a mapping finished and the | |
226 | * SW cleared it. So the protocol is to always wait & clear. | |
227 | */ | |
228 | uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | | |
229 | ATC_VMID0_PASID_MAPPING__VALID_MASK; | |
230 | ||
231 | WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); | |
232 | ||
233 | while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) | |
234 | cpu_relax(); | |
235 | WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); | |
236 | ||
237 | /* Mapping vmid to pasid also for IH block */ | |
238 | WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
243 | static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, | |
244 | uint32_t hpd_size, uint64_t hpd_gpu_addr) | |
245 | { | |
246 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
247 | ||
248 | uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1; | |
249 | uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC); | |
250 | ||
251 | lock_srbm(kgd, mec, pipe, 0, 0); | |
252 | WREG32(mmCP_HPD_EOP_BASE_ADDR, lower_32_bits(hpd_gpu_addr >> 8)); | |
253 | WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(hpd_gpu_addr >> 8)); | |
254 | WREG32(mmCP_HPD_EOP_VMID, 0); | |
255 | WREG32(mmCP_HPD_EOP_CONTROL, hpd_size); | |
256 | unlock_srbm(kgd); | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) | |
262 | { | |
263 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
264 | uint32_t mec; | |
265 | uint32_t pipe; | |
266 | ||
267 | mec = (pipe_id / CIK_PIPE_PER_MEC) + 1; | |
268 | pipe = (pipe_id % CIK_PIPE_PER_MEC); | |
269 | ||
270 | lock_srbm(kgd, mec, pipe, 0, 0); | |
271 | ||
272 | WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | | |
273 | CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); | |
274 | ||
275 | unlock_srbm(kgd); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m) | |
281 | { | |
282 | uint32_t retval; | |
283 | ||
284 | retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + | |
285 | m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET; | |
286 | ||
287 | pr_debug("kfd: sdma base address: 0x%x\n", retval); | |
288 | ||
289 | return retval; | |
290 | } | |
291 | ||
292 | static inline struct cik_mqd *get_mqd(void *mqd) | |
293 | { | |
294 | return (struct cik_mqd *)mqd; | |
295 | } | |
296 | ||
297 | static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) | |
298 | { | |
299 | return (struct cik_sdma_rlc_registers *)mqd; | |
300 | } | |
301 | ||
302 | static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, | |
303 | uint32_t queue_id, uint32_t __user *wptr) | |
304 | { | |
305 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
306 | uint32_t wptr_shadow, is_wptr_shadow_valid; | |
307 | struct cik_mqd *m; | |
308 | ||
309 | m = get_mqd(mqd); | |
310 | ||
311 | is_wptr_shadow_valid = !get_user(wptr_shadow, wptr); | |
312 | ||
313 | acquire_queue(kgd, pipe_id, queue_id); | |
314 | WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo); | |
315 | WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi); | |
316 | WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control); | |
317 | ||
318 | WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo); | |
319 | WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi); | |
320 | WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control); | |
321 | ||
322 | WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control); | |
323 | WREG32(mmCP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo); | |
324 | WREG32(mmCP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi); | |
325 | ||
326 | WREG32(mmCP_HQD_IB_RPTR, m->cp_hqd_ib_rptr); | |
327 | ||
328 | WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state); | |
329 | WREG32(mmCP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd); | |
330 | WREG32(mmCP_HQD_MSG_TYPE, m->cp_hqd_msg_type); | |
331 | ||
332 | WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, m->cp_hqd_atomic0_preop_lo); | |
333 | WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, m->cp_hqd_atomic0_preop_hi); | |
334 | WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, m->cp_hqd_atomic1_preop_lo); | |
335 | WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, m->cp_hqd_atomic1_preop_hi); | |
336 | ||
337 | WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo); | |
338 | WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, | |
339 | m->cp_hqd_pq_rptr_report_addr_hi); | |
340 | ||
341 | WREG32(mmCP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr); | |
342 | ||
343 | WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, m->cp_hqd_pq_wptr_poll_addr_lo); | |
344 | WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, m->cp_hqd_pq_wptr_poll_addr_hi); | |
345 | ||
346 | WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control); | |
347 | ||
348 | WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid); | |
349 | ||
350 | WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum); | |
351 | ||
352 | WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority); | |
353 | WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority); | |
354 | ||
355 | WREG32(mmCP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr); | |
356 | ||
357 | if (is_wptr_shadow_valid) | |
358 | WREG32(mmCP_HQD_PQ_WPTR, wptr_shadow); | |
359 | ||
360 | WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active); | |
361 | release_queue(kgd); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd) | |
367 | { | |
368 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
369 | struct cik_sdma_rlc_registers *m; | |
370 | uint32_t sdma_base_addr; | |
371 | ||
372 | m = get_sdma_mqd(mqd); | |
373 | sdma_base_addr = get_sdma_base_addr(m); | |
374 | ||
375 | WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, | |
376 | m->sdma_rlc_virtual_addr); | |
377 | ||
378 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, | |
379 | m->sdma_rlc_rb_base); | |
380 | ||
381 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, | |
382 | m->sdma_rlc_rb_base_hi); | |
383 | ||
384 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, | |
385 | m->sdma_rlc_rb_rptr_addr_lo); | |
386 | ||
387 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, | |
388 | m->sdma_rlc_rb_rptr_addr_hi); | |
389 | ||
390 | WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, | |
391 | m->sdma_rlc_doorbell); | |
392 | ||
393 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, | |
394 | m->sdma_rlc_rb_cntl); | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, | |
400 | uint32_t pipe_id, uint32_t queue_id) | |
401 | { | |
402 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
403 | uint32_t act; | |
404 | bool retval = false; | |
405 | uint32_t low, high; | |
406 | ||
407 | acquire_queue(kgd, pipe_id, queue_id); | |
408 | act = RREG32(mmCP_HQD_ACTIVE); | |
409 | if (act) { | |
410 | low = lower_32_bits(queue_address >> 8); | |
411 | high = upper_32_bits(queue_address >> 8); | |
412 | ||
413 | if (low == RREG32(mmCP_HQD_PQ_BASE) && | |
414 | high == RREG32(mmCP_HQD_PQ_BASE_HI)) | |
415 | retval = true; | |
416 | } | |
417 | release_queue(kgd); | |
418 | return retval; | |
419 | } | |
420 | ||
421 | static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) | |
422 | { | |
423 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
424 | struct cik_sdma_rlc_registers *m; | |
425 | uint32_t sdma_base_addr; | |
426 | uint32_t sdma_rlc_rb_cntl; | |
427 | ||
428 | m = get_sdma_mqd(mqd); | |
429 | sdma_base_addr = get_sdma_base_addr(m); | |
430 | ||
431 | sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); | |
432 | ||
433 | if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) | |
434 | return true; | |
435 | ||
436 | return false; | |
437 | } | |
438 | ||
439 | static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, | |
1d602430 | 440 | unsigned int utimeout, uint32_t pipe_id, |
32c22e99 OG |
441 | uint32_t queue_id) |
442 | { | |
443 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
444 | uint32_t temp; | |
1d602430 | 445 | int timeout = utimeout; |
32c22e99 OG |
446 | |
447 | acquire_queue(kgd, pipe_id, queue_id); | |
448 | WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0); | |
449 | ||
450 | WREG32(mmCP_HQD_DEQUEUE_REQUEST, reset_type); | |
451 | ||
452 | while (true) { | |
453 | temp = RREG32(mmCP_HQD_ACTIVE); | |
e8a64b20 | 454 | if (temp & CP_HQD_ACTIVE__ACTIVE_MASK) |
32c22e99 | 455 | break; |
1d602430 EC |
456 | if (timeout <= 0) { |
457 | pr_err("kfd: cp queue preemption time out.\n"); | |
32c22e99 OG |
458 | release_queue(kgd); |
459 | return -ETIME; | |
460 | } | |
461 | msleep(20); | |
462 | timeout -= 20; | |
463 | } | |
464 | ||
465 | release_queue(kgd); | |
466 | return 0; | |
467 | } | |
468 | ||
469 | static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, | |
1d602430 | 470 | unsigned int utimeout) |
32c22e99 OG |
471 | { |
472 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
473 | struct cik_sdma_rlc_registers *m; | |
474 | uint32_t sdma_base_addr; | |
475 | uint32_t temp; | |
1d602430 | 476 | int timeout = utimeout; |
32c22e99 OG |
477 | |
478 | m = get_sdma_mqd(mqd); | |
479 | sdma_base_addr = get_sdma_base_addr(m); | |
480 | ||
481 | temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); | |
482 | temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; | |
483 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); | |
484 | ||
485 | while (true) { | |
486 | temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); | |
487 | if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT) | |
488 | break; | |
1d602430 | 489 | if (timeout <= 0) |
32c22e99 OG |
490 | return -ETIME; |
491 | msleep(20); | |
492 | timeout -= 20; | |
493 | } | |
494 | ||
495 | WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); | |
496 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0); | |
497 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0); | |
498 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0); | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
503 | static int kgd_address_watch_disable(struct kgd_dev *kgd) | |
504 | { | |
505 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
506 | union TCP_WATCH_CNTL_BITS cntl; | |
507 | unsigned int i; | |
508 | ||
509 | cntl.u32All = 0; | |
510 | ||
511 | cntl.bitfields.valid = 0; | |
512 | cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; | |
513 | cntl.bitfields.atc = 1; | |
514 | ||
515 | /* Turning off this address until we set all the registers */ | |
516 | for (i = 0; i < MAX_WATCH_ADDRESSES; i++) | |
517 | WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX + | |
518 | ADDRESS_WATCH_REG_CNTL], cntl.u32All); | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | static int kgd_address_watch_execute(struct kgd_dev *kgd, | |
524 | unsigned int watch_point_id, | |
525 | uint32_t cntl_val, | |
526 | uint32_t addr_hi, | |
527 | uint32_t addr_lo) | |
528 | { | |
529 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
530 | union TCP_WATCH_CNTL_BITS cntl; | |
531 | ||
532 | cntl.u32All = cntl_val; | |
533 | ||
534 | /* Turning off this watch point until we set all the registers */ | |
535 | cntl.bitfields.valid = 0; | |
536 | WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + | |
537 | ADDRESS_WATCH_REG_CNTL], cntl.u32All); | |
538 | ||
539 | WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + | |
540 | ADDRESS_WATCH_REG_ADDR_HI], addr_hi); | |
541 | ||
542 | WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + | |
543 | ADDRESS_WATCH_REG_ADDR_LO], addr_lo); | |
544 | ||
545 | /* Enable the watch point */ | |
546 | cntl.bitfields.valid = 1; | |
547 | ||
548 | WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + | |
549 | ADDRESS_WATCH_REG_CNTL], cntl.u32All); | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | static int kgd_wave_control_execute(struct kgd_dev *kgd, | |
555 | uint32_t gfx_index_val, | |
556 | uint32_t sq_cmd) | |
557 | { | |
558 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | |
559 | uint32_t data; | |
560 | ||
561 | mutex_lock(&adev->grbm_idx_mutex); | |
562 | ||
563 | WREG32(mmGRBM_GFX_INDEX, gfx_index_val); | |
564 | WREG32(mmSQ_CMD, sq_cmd); | |
565 | ||
566 | /* Restore the GRBM_GFX_INDEX register */ | |
567 | ||
568 | data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | | |
569 | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | | |
570 | GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; | |
571 | ||
572 | WREG32(mmGRBM_GFX_INDEX, data); | |
573 | ||
574 | mutex_unlock(&adev->grbm_idx_mutex); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, | |
580 | unsigned int watch_point_id, | |
581 | unsigned int reg_offset) | |
582 | { | |
583 | return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset]; | |
584 | } | |
585 | ||
586 | static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, | |
587 | uint8_t vmid) | |
588 | { | |
589 | uint32_t reg; | |
590 | struct amdgpu_device *adev = (struct amdgpu_device *) kgd; | |
591 | ||
592 | reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); | |
593 | return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; | |
594 | } | |
595 | ||
596 | static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, | |
597 | uint8_t vmid) | |
598 | { | |
599 | uint32_t reg; | |
600 | struct amdgpu_device *adev = (struct amdgpu_device *) kgd; | |
601 | ||
602 | reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); | |
603 | return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; | |
604 | } | |
605 | ||
606 | static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) | |
607 | { | |
608 | struct amdgpu_device *adev = (struct amdgpu_device *) kgd; | |
609 | ||
610 | WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); | |
611 | } | |
612 | ||
613 | static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) | |
614 | { | |
615 | struct amdgpu_device *adev = (struct amdgpu_device *) kgd; | |
616 | const union amdgpu_firmware_header *hdr; | |
617 | ||
618 | BUG_ON(kgd == NULL); | |
619 | ||
620 | switch (type) { | |
621 | case KGD_ENGINE_PFP: | |
622 | hdr = (const union amdgpu_firmware_header *) | |
623 | adev->gfx.pfp_fw->data; | |
624 | break; | |
625 | ||
626 | case KGD_ENGINE_ME: | |
627 | hdr = (const union amdgpu_firmware_header *) | |
628 | adev->gfx.me_fw->data; | |
629 | break; | |
630 | ||
631 | case KGD_ENGINE_CE: | |
632 | hdr = (const union amdgpu_firmware_header *) | |
633 | adev->gfx.ce_fw->data; | |
634 | break; | |
635 | ||
636 | case KGD_ENGINE_MEC1: | |
637 | hdr = (const union amdgpu_firmware_header *) | |
638 | adev->gfx.mec_fw->data; | |
639 | break; | |
640 | ||
641 | case KGD_ENGINE_MEC2: | |
642 | hdr = (const union amdgpu_firmware_header *) | |
643 | adev->gfx.mec2_fw->data; | |
644 | break; | |
645 | ||
646 | case KGD_ENGINE_RLC: | |
647 | hdr = (const union amdgpu_firmware_header *) | |
648 | adev->gfx.rlc_fw->data; | |
649 | break; | |
650 | ||
651 | case KGD_ENGINE_SDMA1: | |
652 | hdr = (const union amdgpu_firmware_header *) | |
c113ea1c | 653 | adev->sdma.instance[0].fw->data; |
32c22e99 OG |
654 | break; |
655 | ||
656 | case KGD_ENGINE_SDMA2: | |
657 | hdr = (const union amdgpu_firmware_header *) | |
c113ea1c | 658 | adev->sdma.instance[1].fw->data; |
32c22e99 OG |
659 | break; |
660 | ||
661 | default: | |
662 | return 0; | |
663 | } | |
664 | ||
665 | if (hdr == NULL) | |
666 | return 0; | |
667 | ||
668 | /* Only 12 bit in use*/ | |
669 | return hdr->common.ucode_version; | |
670 | } | |
671 |