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drm/amdgpu: add amdgpu_vm_entries_mask v2
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd_gfx_v7.c
CommitLineData
32c22e99
OG		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/fdtable.h>
24#include <linux/uaccess.h>
25#include <linux/firmware.h>
26#include <drm/drmP.h>
27#include "amdgpu.h"
28#include "amdgpu_amdkfd.h"
29#include "cikd.h"
30#include "cik_sdma.h"
31#include "amdgpu_ucode.h"
97bf47b2 32#include "gfx_v7_0.h"
32c22e99
OG		 33#include "gca/gfx_7_2_d.h"
34#include "gca/gfx_7_2_enum.h"
35#include "gca/gfx_7_2_sh_mask.h"
36#include "oss/oss_2_0_d.h"
37#include "oss/oss_2_0_sh_mask.h"
38#include "gmc/gmc_7_1_d.h"
39#include "gmc/gmc_7_1_sh_mask.h"
40#include "cik_structs.h"
41
70539bd7
FK		 42enum hqd_dequeue_request_type {
43 NO_ACTION = 0,
44 DRAIN_PIPE,
45 RESET_WAVES
46};
47
32c22e99
OG		 48enum {
49 MAX_TRAPID = 8, /* 3 bits in the bitfield. */
50 MAX_WATCH_ADDRESSES = 4
51};
52
53enum {
54 ADDRESS_WATCH_REG_ADDR_HI = 0,
55 ADDRESS_WATCH_REG_ADDR_LO,
56 ADDRESS_WATCH_REG_CNTL,
57 ADDRESS_WATCH_REG_MAX
58};
59
60/* not defined in the CI/KV reg file */
61enum {
62 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
63 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
64 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
65 /* extend the mask to 26 bits to match the low address field */
66 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
67 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
68};
69
70static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
71 mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
72 mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
73 mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
74 mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
75};
76
77union TCP_WATCH_CNTL_BITS {
78 struct {
79 uint32_t mask:24;
80 uint32_t vmid:4;
81 uint32_t atc:1;
82 uint32_t mode:2;
83 uint32_t valid:1;
84 } bitfields, bits;
85 uint32_t u32All;
86 signed int i32All;
87 float f32All;
88};
89
90/*
91 * Register access functions
92 */
93
94static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
95 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
96 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
97
98static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
99 unsigned int vmid);
100
32c22e99
OG		 101static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
102static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
70539bd7
FK		 103 uint32_t queue_id, uint32_t __user *wptr,
104 uint32_t wptr_shift, uint32_t wptr_mask,
105 struct mm_struct *mm);
80c195f5
FK		 106static int kgd_hqd_dump(struct kgd_dev *kgd,
107 uint32_t pipe_id, uint32_t queue_id,
108 uint32_t (**dump)[2], uint32_t *n_regs);
7ce66118
FK		 109static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
110 uint32_t __user *wptr, struct mm_struct *mm);
80c195f5
FK		 111static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
112 uint32_t engine_id, uint32_t queue_id,
113 uint32_t (**dump)[2], uint32_t *n_regs);
32c22e99
OG		 114static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
115 uint32_t pipe_id, uint32_t queue_id);
116
70539bd7
FK		 117static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
118 enum kfd_preempt_type reset_type,
1d602430 119 unsigned int utimeout, uint32_t pipe_id,
32c22e99
OG		 120 uint32_t queue_id);
121static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
122static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
1d602430 123 unsigned int utimeout);
32c22e99
OG		 124static int kgd_address_watch_disable(struct kgd_dev *kgd);
125static int kgd_address_watch_execute(struct kgd_dev *kgd,
126 unsigned int watch_point_id,
127 uint32_t cntl_val,
128 uint32_t addr_hi,
129 uint32_t addr_lo);
130static int kgd_wave_control_execute(struct kgd_dev *kgd,
131 uint32_t gfx_index_val,
132 uint32_t sq_cmd);
133static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
134 unsigned int watch_point_id,
135 unsigned int reg_offset);
136
137static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
138static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
139 uint8_t vmid);
32c22e99
OG		 140
141static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
09e56abb
MR		 142static void set_scratch_backing_va(struct kgd_dev *kgd,
143 uint64_t va, uint32_t vmid);
a46a2cd1
FK		 144static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
145 uint32_t page_table_base);
146static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
147static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
58e69886 148static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd);
32c22e99 149
fb31a0c9
YZ		 150/* Because of REG_GET_FIELD() being used, we put this function in the
151 * asic specific file.
152 */
153static int get_tile_config(struct kgd_dev *kgd,
154 struct tile_config *config)
155{
156 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
157
158 config->gb_addr_config = adev->gfx.config.gb_addr_config;
159 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
160 MC_ARB_RAMCFG, NOOFBANK);
161 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
162 MC_ARB_RAMCFG, NOOFRANKS);
163
164 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
165 config->num_tile_configs =
166 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
167 config->macro_tile_config_ptr =
168 adev->gfx.config.macrotile_mode_array;
169 config->num_macro_tile_configs =
170 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
171
172 return 0;
173}
174
32c22e99
OG		 175static const struct kfd2kgd_calls kfd2kgd = {
176 .init_gtt_mem_allocation = alloc_gtt_mem,
177 .free_gtt_mem = free_gtt_mem,
30f1c042 178 .get_local_mem_info = get_local_mem_info,
32c22e99
OG		 179 .get_gpu_clock_counter = get_gpu_clock_counter,
180 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
620f774f
CK		 181 .alloc_pasid = amdgpu_pasid_alloc,
182 .free_pasid = amdgpu_pasid_free,
32c22e99
OG		 183 .program_sh_mem_settings = kgd_program_sh_mem_settings,
184 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
32c22e99
OG		 185 .init_interrupts = kgd_init_interrupts,
186 .hqd_load = kgd_hqd_load,
187 .hqd_sdma_load = kgd_hqd_sdma_load,
80c195f5
FK		 188 .hqd_dump = kgd_hqd_dump,
189 .hqd_sdma_dump = kgd_hqd_sdma_dump,
32c22e99
OG		 190 .hqd_is_occupied = kgd_hqd_is_occupied,
191 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
192 .hqd_destroy = kgd_hqd_destroy,
193 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
194 .address_watch_disable = kgd_address_watch_disable,
195 .address_watch_execute = kgd_address_watch_execute,
196 .wave_control_execute = kgd_wave_control_execute,
197 .address_watch_get_offset = kgd_address_watch_get_offset,
198 .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
199 .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
09e56abb
MR		 200 .get_fw_version = get_fw_version,
201 .set_scratch_backing_va = set_scratch_backing_va,
fb31a0c9 202 .get_tile_config = get_tile_config,
9f0a0b41 203 .get_cu_info = get_cu_info,
a46a2cd1
FK		 204 .get_vram_usage = amdgpu_amdkfd_get_vram_usage,
205 .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
ede0dd86 206 .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
a46a2cd1 207 .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
bf47afba 208 .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
a46a2cd1
FK		 209 .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
210 .set_vm_context_page_table_base = set_vm_context_page_table_base,
211 .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
212 .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu,
213 .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu,
214 .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu,
215 .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory,
216 .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel,
217 .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos,
218 .invalidate_tlbs = invalidate_tlbs,
219 .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
4c660c8f 220 .submit_ib = amdgpu_amdkfd_submit_ib,
58e69886 221 .get_vm_fault_info = amdgpu_amdkfd_gpuvm_get_vm_fault_info,
24da5a9c 222 .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
01c097db
FK		 223 .gpu_recover = amdgpu_amdkfd_gpu_reset,
224 .set_compute_idle = amdgpu_amdkfd_set_compute_idle
32c22e99
OG		 225};
226
f785d987 227struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
32c22e99
OG		 228{
229 return (struct kfd2kgd_calls *)&kfd2kgd;
230}
231
232static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
233{
234 return (struct amdgpu_device *)kgd;
235}
236
237static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
238 uint32_t queue, uint32_t vmid)
239{
240 struct amdgpu_device *adev = get_amdgpu_device(kgd);
241 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
242
243 mutex_lock(&adev->srbm_mutex);
244 WREG32(mmSRBM_GFX_CNTL, value);
245}
246
247static void unlock_srbm(struct kgd_dev *kgd)
248{
249 struct amdgpu_device *adev = get_amdgpu_device(kgd);
250
251 WREG32(mmSRBM_GFX_CNTL, 0);
252 mutex_unlock(&adev->srbm_mutex);
253}
254
255static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
256 uint32_t queue_id)
257{
5e709562
AR		 258 struct amdgpu_device *adev = get_amdgpu_device(kgd);
259
438e29a2 260 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
5e709562 261 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
32c22e99
OG		 262
263 lock_srbm(kgd, mec, pipe, queue_id, 0);
264}
265
266static void release_queue(struct kgd_dev *kgd)
267{
268 unlock_srbm(kgd);
269}
270
271static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
272 uint32_t sh_mem_config,
273 uint32_t sh_mem_ape1_base,
274 uint32_t sh_mem_ape1_limit,
275 uint32_t sh_mem_bases)
276{
277 struct amdgpu_device *adev = get_amdgpu_device(kgd);
278
279 lock_srbm(kgd, 0, 0, 0, vmid);
280
281 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
282 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
283 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
284 WREG32(mmSH_MEM_BASES, sh_mem_bases);
285
286 unlock_srbm(kgd);
287}
288
289static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
290 unsigned int vmid)
291{
292 struct amdgpu_device *adev = get_amdgpu_device(kgd);
293
294 /*
295 * We have to assume that there is no outstanding mapping.
296 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
297 * a mapping is in progress or because a mapping finished and the
298 * SW cleared it. So the protocol is to always wait & clear.
299 */
300 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
301 ATC_VMID0_PASID_MAPPING__VALID_MASK;
302
303 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
304
305 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
306 cpu_relax();
307 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
308
309 /* Mapping vmid to pasid also for IH block */
310 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
311
312 return 0;
313}
314
32c22e99
OG		 315static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
316{
317 struct amdgpu_device *adev = get_amdgpu_device(kgd);
318 uint32_t mec;
319 uint32_t pipe;
320
5e709562
AR		 321 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
322 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
32c22e99
OG		 323
324 lock_srbm(kgd, mec, pipe, 0, 0);
325
326 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
327 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
328
329 unlock_srbm(kgd);
330
331 return 0;
332}
333
334static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
335{
336 uint32_t retval;
337
338 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
339 m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
340
341 pr_debug("kfd: sdma base address: 0x%x\n", retval);
342
343 return retval;
344}
345
346static inline struct cik_mqd *get_mqd(void *mqd)
347{
348 return (struct cik_mqd *)mqd;
349}
350
351static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
352{
353 return (struct cik_sdma_rlc_registers *)mqd;
354}
355
356static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
70539bd7
FK		 357 uint32_t queue_id, uint32_t __user *wptr,
358 uint32_t wptr_shift, uint32_t wptr_mask,
359 struct mm_struct *mm)
32c22e99
OG		 360{
361 struct amdgpu_device *adev = get_amdgpu_device(kgd);
32c22e99 362 struct cik_mqd *m;
70539bd7
FK		 363 uint32_t *mqd_hqd;
364 uint32_t reg, wptr_val, data;
a50ecc54 365 bool valid_wptr = false;
32c22e99
OG		 366
367 m = get_mqd(mqd);
368
97bf47b2 369 acquire_queue(kgd, pipe_id, queue_id);
70539bd7
FK		 370
371 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */
372 mqd_hqd = &m->cp_mqd_base_addr_lo;
373
374 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
375 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
376
377 /* Copy userspace write pointer value to register.
378 * Activate doorbell logic to monitor subsequent changes.
379 */
380 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
381 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
382 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
383
a50ecc54 384 /* read_user_ptr may take the mm->mmap_sem.
385 * release srbm_mutex to avoid circular dependency between
386 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
387 */
388 release_queue(kgd);
389 valid_wptr = read_user_wptr(mm, wptr, wptr_val);
390 acquire_queue(kgd, pipe_id, queue_id);
391 if (valid_wptr)
70539bd7
FK		 392 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
393
394 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
395 WREG32(mmCP_HQD_ACTIVE, data);
396
32c22e99
OG		 397 release_queue(kgd);
398
399 return 0;
400}
401
80c195f5
FK		 402static int kgd_hqd_dump(struct kgd_dev *kgd,
403 uint32_t pipe_id, uint32_t queue_id,
404 uint32_t (**dump)[2], uint32_t *n_regs)
405{
406 struct amdgpu_device *adev = get_amdgpu_device(kgd);
407 uint32_t i = 0, reg;
408#define HQD_N_REGS (35+4)
409#define DUMP_REG(addr) do { \
410 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
411 break; \
412 (*dump)[i][0] = (addr) << 2; \
413 (*dump)[i++][1] = RREG32(addr); \
414 } while (0)
415
6da2ec56 416 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
80c195f5
FK		 417 if (*dump == NULL)
418 return -ENOMEM;
419
420 acquire_queue(kgd, pipe_id, queue_id);
421
422 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
423 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
424 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
425 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
426
427 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
428 DUMP_REG(reg);
429
430 release_queue(kgd);
431
432 WARN_ON_ONCE(i != HQD_N_REGS);
433 *n_regs = i;
434
435 return 0;
436}
437
7ce66118
FK		 438static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
439 uint32_t __user *wptr, struct mm_struct *mm)
32c22e99
OG		 440{
441 struct amdgpu_device *adev = get_amdgpu_device(kgd);
442 struct cik_sdma_rlc_registers *m;
cf21654b 443 unsigned long end_jiffies;
32c22e99 444 uint32_t sdma_base_addr;
cf21654b 445 uint32_t data;
32c22e99
OG		 446
447 m = get_sdma_mqd(mqd);
448 sdma_base_addr = get_sdma_base_addr(m);
449
cf21654b
FK		 450 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
451 m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
32c22e99 452
cf21654b
FK		 453 end_jiffies = msecs_to_jiffies(2000) + jiffies;
454 while (true) {
455 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
456 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
457 break;
458 if (time_after(jiffies, end_jiffies))
459 return -ETIME;
460 usleep_range(500, 1000);
461 }
462 if (m->sdma_engine_id) {
463 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
464 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
465 RESUME_CTX, 0);
466 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
467 } else {
468 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
469 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
470 RESUME_CTX, 0);
471 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
472 }
32c22e99 473
fd0f0762
FK		 474 data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
475 ENABLE, 1);
476 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
477 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
478
479 if (read_user_wptr(mm, wptr, data))
480 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
481 else
482 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
483 m->sdma_rlc_rb_rptr);
484
cf21654b
FK		 485 WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
486 m->sdma_rlc_virtual_addr);
487 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
32c22e99
OG		 488 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
489 m->sdma_rlc_rb_base_hi);
32c22e99
OG		 490 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
491 m->sdma_rlc_rb_rptr_addr_lo);
32c22e99
OG		 492 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
493 m->sdma_rlc_rb_rptr_addr_hi);
fd0f0762
FK		 494
495 data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
496 RB_ENABLE, 1);
497 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
32c22e99
OG		 498
499 return 0;
500}
501
80c195f5
FK		 502static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
503 uint32_t engine_id, uint32_t queue_id,
504 uint32_t (**dump)[2], uint32_t *n_regs)
505{
506 struct amdgpu_device *adev = get_amdgpu_device(kgd);
507 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
508 queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
509 uint32_t i = 0, reg;
510#undef HQD_N_REGS
511#define HQD_N_REGS (19+4)
512
6da2ec56 513 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
80c195f5
FK		 514 if (*dump == NULL)
515 return -ENOMEM;
516
517 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
518 DUMP_REG(sdma_offset + reg);
519 for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
520 reg++)
521 DUMP_REG(sdma_offset + reg);
522
523 WARN_ON_ONCE(i != HQD_N_REGS);
524 *n_regs = i;
525
526 return 0;
527}
528
32c22e99
OG		 529static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
530 uint32_t pipe_id, uint32_t queue_id)
531{
532 struct amdgpu_device *adev = get_amdgpu_device(kgd);
533 uint32_t act;
534 bool retval = false;
535 uint32_t low, high;
536
537 acquire_queue(kgd, pipe_id, queue_id);
538 act = RREG32(mmCP_HQD_ACTIVE);
539 if (act) {
540 low = lower_32_bits(queue_address >> 8);
541 high = upper_32_bits(queue_address >> 8);
542
543 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
544 high == RREG32(mmCP_HQD_PQ_BASE_HI))
545 retval = true;
546 }
547 release_queue(kgd);
548 return retval;
549}
550
551static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
552{
553 struct amdgpu_device *adev = get_amdgpu_device(kgd);
554 struct cik_sdma_rlc_registers *m;
555 uint32_t sdma_base_addr;
556 uint32_t sdma_rlc_rb_cntl;
557
558 m = get_sdma_mqd(mqd);
559 sdma_base_addr = get_sdma_base_addr(m);
560
561 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
562
563 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
564 return true;
565
566 return false;
567}
568
70539bd7
FK		 569static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
570 enum kfd_preempt_type reset_type,
1d602430 571 unsigned int utimeout, uint32_t pipe_id,
32c22e99
OG		 572 uint32_t queue_id)
573{
574 struct amdgpu_device *adev = get_amdgpu_device(kgd);
575 uint32_t temp;
70539bd7
FK		 576 enum hqd_dequeue_request_type type;
577 unsigned long flags, end_jiffies;
578 int retry;
32c22e99 579
1b0bfcff
SL		 580 if (adev->in_gpu_reset)
581 return -EIO;
582
32c22e99
OG		 583 acquire_queue(kgd, pipe_id, queue_id);
584 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
585
70539bd7
FK		 586 switch (reset_type) {
587 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
588 type = DRAIN_PIPE;
589 break;
590 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
591 type = RESET_WAVES;
592 break;
593 default:
594 type = DRAIN_PIPE;
595 break;
596 }
32c22e99 597
70539bd7
FK		 598 /* Workaround: If IQ timer is active and the wait time is close to or
599 * equal to 0, dequeueing is not safe. Wait until either the wait time
600 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
601 * cleared before continuing. Also, ensure wait times are set to at
602 * least 0x3.
603 */
604 local_irq_save(flags);
605 preempt_disable();
606 retry = 5000; /* wait for 500 usecs at maximum */
607 while (true) {
608 temp = RREG32(mmCP_HQD_IQ_TIMER);
609 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
610 pr_debug("HW is processing IQ\n");
611 goto loop;
612 }
613 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
614 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
615 == 3) /* SEM-rearm is safe */
616 break;
617 /* Wait time 3 is safe for CP, but our MMIO read/write
618 * time is close to 1 microsecond, so check for 10 to
619 * leave more buffer room
620 */
621 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
622 >= 10)
623 break;
624 pr_debug("IQ timer is active\n");
625 } else
626 break;
627loop:
628 if (!retry) {
629 pr_err("CP HQD IQ timer status time out\n");
630 break;
631 }
632 ndelay(100);
633 --retry;
634 }
635 retry = 1000;
636 while (true) {
637 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
638 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
639 break;
640 pr_debug("Dequeue request is pending\n");
641
642 if (!retry) {
643 pr_err("CP HQD dequeue request time out\n");
644 break;
645 }
646 ndelay(100);
647 --retry;
648 }
649 local_irq_restore(flags);
650 preempt_enable();
651
652 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
653
654 end_jiffies = (utimeout * HZ / 1000) + jiffies;
32c22e99
OG		 655 while (true) {
656 temp = RREG32(mmCP_HQD_ACTIVE);
70539bd7 657 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
32c22e99 658 break;
70539bd7
FK		 659 if (time_after(jiffies, end_jiffies)) {
660 pr_err("cp queue preemption time out\n");
32c22e99
OG		 661 release_queue(kgd);
662 return -ETIME;
663 }
70539bd7 664 usleep_range(500, 1000);
32c22e99
OG		 665 }
666
667 release_queue(kgd);
668 return 0;
669}
670
671static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
1d602430 672 unsigned int utimeout)
32c22e99
OG		 673{
674 struct amdgpu_device *adev = get_amdgpu_device(kgd);
675 struct cik_sdma_rlc_registers *m;
676 uint32_t sdma_base_addr;
677 uint32_t temp;
fd0f0762 678 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
32c22e99
OG		 679
680 m = get_sdma_mqd(mqd);
681 sdma_base_addr = get_sdma_base_addr(m);
682
683 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
684 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
685 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
686
687 while (true) {
688 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
689 if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
690 break;
fd0f0762 691 if (time_after(jiffies, end_jiffies))
32c22e99 692 return -ETIME;
fd0f0762 693 usleep_range(500, 1000);
32c22e99
OG		 694 }
695
696 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
cf21654b
FK		 697 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
698 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
699 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
32c22e99 700
fd0f0762
FK		 701 m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
702
32c22e99
OG		 703 return 0;
704}
705
706static int kgd_address_watch_disable(struct kgd_dev *kgd)
707{
708 struct amdgpu_device *adev = get_amdgpu_device(kgd);
709 union TCP_WATCH_CNTL_BITS cntl;
710 unsigned int i;
711
712 cntl.u32All = 0;
713
714 cntl.bitfields.valid = 0;
715 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
716 cntl.bitfields.atc = 1;
717
718 /* Turning off this address until we set all the registers */
719 for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
720 WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
721 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
722
723 return 0;
724}
725
726static int kgd_address_watch_execute(struct kgd_dev *kgd,
727 unsigned int watch_point_id,
728 uint32_t cntl_val,
729 uint32_t addr_hi,
730 uint32_t addr_lo)
731{
732 struct amdgpu_device *adev = get_amdgpu_device(kgd);
733 union TCP_WATCH_CNTL_BITS cntl;
734
735 cntl.u32All = cntl_val;
736
737 /* Turning off this watch point until we set all the registers */
738 cntl.bitfields.valid = 0;
739 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
740 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
741
742 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
743 ADDRESS_WATCH_REG_ADDR_HI], addr_hi);
744
745 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
746 ADDRESS_WATCH_REG_ADDR_LO], addr_lo);
747
748 /* Enable the watch point */
749 cntl.bitfields.valid = 1;
750
751 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
752 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
753
754 return 0;
755}
756
757static int kgd_wave_control_execute(struct kgd_dev *kgd,
758 uint32_t gfx_index_val,
759 uint32_t sq_cmd)
760{
761 struct amdgpu_device *adev = get_amdgpu_device(kgd);
762 uint32_t data;
763
764 mutex_lock(&adev->grbm_idx_mutex);
765
766 WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
767 WREG32(mmSQ_CMD, sq_cmd);
768
769 /* Restore the GRBM_GFX_INDEX register */
770
771 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK |
772 GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
773 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
774
775 WREG32(mmGRBM_GFX_INDEX, data);
776
777 mutex_unlock(&adev->grbm_idx_mutex);
778
779 return 0;
780}
781
782static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
783 unsigned int watch_point_id,
784 unsigned int reg_offset)
785{
786 return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
787}
788
789static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
790 uint8_t vmid)
791{
792 uint32_t reg;
793 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
794
795 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
796 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
797}
798
799static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
800 uint8_t vmid)
801{
802 uint32_t reg;
803 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
804
805 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
2f901c25 806 return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
32c22e99
OG		 807}
808
09e56abb
MR		 809static void set_scratch_backing_va(struct kgd_dev *kgd,
810 uint64_t va, uint32_t vmid)
811{
812 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
813
814 lock_srbm(kgd, 0, 0, 0, vmid);
815 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
816 unlock_srbm(kgd);
817}
818
32c22e99
OG		 819static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
820{
821 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
822 const union amdgpu_firmware_header *hdr;
823
32c22e99
OG		 824 switch (type) {
825 case KGD_ENGINE_PFP:
826 hdr = (const union amdgpu_firmware_header *)
8eabaf54 827 adev->gfx.pfp_fw->data;
32c22e99
OG		 828 break;
829
830 case KGD_ENGINE_ME:
831 hdr = (const union amdgpu_firmware_header *)
8eabaf54 832 adev->gfx.me_fw->data;
32c22e99
OG		 833 break;
834
835 case KGD_ENGINE_CE:
836 hdr = (const union amdgpu_firmware_header *)
8eabaf54 837 adev->gfx.ce_fw->data;
32c22e99
OG		 838 break;
839
840 case KGD_ENGINE_MEC1:
841 hdr = (const union amdgpu_firmware_header *)
8eabaf54 842 adev->gfx.mec_fw->data;
32c22e99
OG		 843 break;
844
845 case KGD_ENGINE_MEC2:
846 hdr = (const union amdgpu_firmware_header *)
8eabaf54 847 adev->gfx.mec2_fw->data;
32c22e99
OG		 848 break;
849
850 case KGD_ENGINE_RLC:
851 hdr = (const union amdgpu_firmware_header *)
8eabaf54 852 adev->gfx.rlc_fw->data;
32c22e99
OG		 853 break;
854
855 case KGD_ENGINE_SDMA1:
856 hdr = (const union amdgpu_firmware_header *)
8eabaf54 857 adev->sdma.instance[0].fw->data;
32c22e99
OG		 858 break;
859
860 case KGD_ENGINE_SDMA2:
861 hdr = (const union amdgpu_firmware_header *)
8eabaf54 862 adev->sdma.instance[1].fw->data;
32c22e99
OG		 863 break;
864
865 default:
866 return 0;
867 }
868
869 if (hdr == NULL)
870 return 0;
871
872 /* Only 12 bit in use*/
873 return hdr->common.ucode_version;
874}
875
a46a2cd1
FK		 876static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
877 uint32_t page_table_base)
878{
879 struct amdgpu_device *adev = get_amdgpu_device(kgd);
880
881 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
882 pr_err("trying to set page table base for wrong VMID\n");
883 return;
884 }
885 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
886}
887
888static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
889{
890 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
891 int vmid;
892 unsigned int tmp;
893
bff418a2
SL		 894 if (adev->in_gpu_reset)
895 return -EIO;
896
a46a2cd1
FK		 897 for (vmid = 0; vmid < 16; vmid++) {
898 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
899 continue;
900
901 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
902 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
903 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
904 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
905 RREG32(mmVM_INVALIDATE_RESPONSE);
906 break;
907 }
908 }
909
910 return 0;
911}
912
913static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
914{
915 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
916
917 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
918 pr_err("non kfd vmid\n");
919 return 0;
920 }
921
922 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
923 RREG32(mmVM_INVALIDATE_RESPONSE);
924 return 0;
925}
58e69886
LX		 926
927 /**
928 * read_vmid_from_vmfault_reg - read vmid from register
929 *
930 * adev: amdgpu_device pointer
931 * @vmid: vmid pointer
932 * read vmid from register (CIK).
933 */
934static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd)
935{
936 struct amdgpu_device *adev = get_amdgpu_device(kgd);
937
938 uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
939
940 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
941}
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