[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd_gfx_v7.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/fdtable.h>
#include <linux/uaccess.h>
#include <linux/firmware.h>
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_amdkfd.h"
#include "cikd.h"
#include "cik_sdma.h"
#include "amdgpu_ucode.h"
#include "gfx_v7_0.h"
#include "gca/gfx_7_2_d.h"
#include "gca/gfx_7_2_enum.h"
#include "gca/gfx_7_2_sh_mask.h"
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"
#include "gmc/gmc_7_1_d.h"
#include "gmc/gmc_7_1_sh_mask.h"
#include "cik_structs.h"

#define CIK_PIPE_PER_MEC	(4)

enum {
	MAX_TRAPID = 8,		/* 3 bits in the bitfield. */
	MAX_WATCH_ADDRESSES = 4
};

enum {
	ADDRESS_WATCH_REG_ADDR_HI = 0,
	ADDRESS_WATCH_REG_ADDR_LO,
	ADDRESS_WATCH_REG_CNTL,
	ADDRESS_WATCH_REG_MAX
};

/*  not defined in the CI/KV reg file  */
enum {
	ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
	ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
	ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
	/* extend the mask to 26 bits to match the low address field */
	ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
	ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
};

static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
	mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
	mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
	mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
	mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
};

union TCP_WATCH_CNTL_BITS {
	struct {
		uint32_t mask:24;
		uint32_t vmid:4;
		uint32_t atc:1;
		uint32_t mode:2;
		uint32_t valid:1;
	} bitfields, bits;
	uint32_t u32All;
	signed int i32All;
	float f32All;
};

/*
 * Register access functions
 */

static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
		uint32_t sh_mem_config,	uint32_t sh_mem_ape1_base,
		uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);

static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
					unsigned int vmid);

static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
				uint32_t hpd_size, uint64_t hpd_gpu_addr);
static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
			uint32_t queue_id, uint32_t __user *wptr);
static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
				uint32_t pipe_id, uint32_t queue_id);

static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
				unsigned int utimeout, uint32_t pipe_id,
				uint32_t queue_id);
static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
				unsigned int utimeout);
static int kgd_address_watch_disable(struct kgd_dev *kgd);
static int kgd_address_watch_execute(struct kgd_dev *kgd,
					unsigned int watch_point_id,
					uint32_t cntl_val,
					uint32_t addr_hi,
					uint32_t addr_lo);
static int kgd_wave_control_execute(struct kgd_dev *kgd,
					uint32_t gfx_index_val,
					uint32_t sq_cmd);
static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
					unsigned int watch_point_id,
					unsigned int reg_offset);

static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
							uint8_t vmid);
static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);

static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);

static const struct kfd2kgd_calls kfd2kgd = {
	.init_gtt_mem_allocation = alloc_gtt_mem,
	.free_gtt_mem = free_gtt_mem,
	.get_vmem_size = get_vmem_size,
	.get_gpu_clock_counter = get_gpu_clock_counter,
	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
	.program_sh_mem_settings = kgd_program_sh_mem_settings,
	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
	.init_pipeline = kgd_init_pipeline,
	.init_interrupts = kgd_init_interrupts,
	.hqd_load = kgd_hqd_load,
	.hqd_sdma_load = kgd_hqd_sdma_load,
	.hqd_is_occupied = kgd_hqd_is_occupied,
	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
	.hqd_destroy = kgd_hqd_destroy,
	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
	.address_watch_disable = kgd_address_watch_disable,
	.address_watch_execute = kgd_address_watch_execute,
	.wave_control_execute = kgd_wave_control_execute,
	.address_watch_get_offset = kgd_address_watch_get_offset,
	.get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
	.get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
	.write_vmid_invalidate_request = write_vmid_invalidate_request,
	.get_fw_version = get_fw_version
};

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
{
	return (struct kfd2kgd_calls *)&kfd2kgd;
}

static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
{
	return (struct amdgpu_device *)kgd;
}

static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
			uint32_t queue, uint32_t vmid)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);

	mutex_lock(&adev->srbm_mutex);
	WREG32(mmSRBM_GFX_CNTL, value);
}

static void unlock_srbm(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	WREG32(mmSRBM_GFX_CNTL, 0);
	mutex_unlock(&adev->srbm_mutex);
}

static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
				uint32_t queue_id)
{
	uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);

	lock_srbm(kgd, mec, pipe, queue_id, 0);
}

static void release_queue(struct kgd_dev *kgd)
{
	unlock_srbm(kgd);
}

static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
					uint32_t sh_mem_config,
					uint32_t sh_mem_ape1_base,
					uint32_t sh_mem_ape1_limit,
					uint32_t sh_mem_bases)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	lock_srbm(kgd, 0, 0, 0, vmid);

	WREG32(mmSH_MEM_CONFIG, sh_mem_config);
	WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
	WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
	WREG32(mmSH_MEM_BASES, sh_mem_bases);

	unlock_srbm(kgd);
}

static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
					unsigned int vmid)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	/*
	 * We have to assume that there is no outstanding mapping.
	 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
	 * a mapping is in progress or because a mapping finished and the
	 * SW cleared it. So the protocol is to always wait & clear.
	 */
	uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
			ATC_VMID0_PASID_MAPPING__VALID_MASK;

	WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);

	while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
		cpu_relax();
	WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);

	/* Mapping vmid to pasid also for IH block */
	WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);

	return 0;
}

static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
				uint32_t hpd_size, uint64_t hpd_gpu_addr)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);

	lock_srbm(kgd, mec, pipe, 0, 0);
	WREG32(mmCP_HPD_EOP_BASE_ADDR, lower_32_bits(hpd_gpu_addr >> 8));
	WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(hpd_gpu_addr >> 8));
	WREG32(mmCP_HPD_EOP_VMID, 0);
	WREG32(mmCP_HPD_EOP_CONTROL, hpd_size);
	unlock_srbm(kgd);

	return 0;
}

static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	uint32_t mec;
	uint32_t pipe;

	mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
	pipe = (pipe_id % CIK_PIPE_PER_MEC);

	lock_srbm(kgd, mec, pipe, 0, 0);

	WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
			CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);

	unlock_srbm(kgd);

	return 0;
}

static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
{
	uint32_t retval;

	retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
			m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;

	pr_debug("kfd: sdma base address: 0x%x\n", retval);

	return retval;
}

static inline struct cik_mqd *get_mqd(void *mqd)
{
	return (struct cik_mqd *)mqd;
}

static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
{
	return (struct cik_sdma_rlc_registers *)mqd;
}

static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
			uint32_t queue_id, uint32_t __user *wptr)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	uint32_t wptr_shadow, is_wptr_shadow_valid;
	struct cik_mqd *m;

	m = get_mqd(mqd);

	is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
	if (is_wptr_shadow_valid)
		m->cp_hqd_pq_wptr = wptr_shadow;

	acquire_queue(kgd, pipe_id, queue_id);
	gfx_v7_0_mqd_commit(adev, m);
	release_queue(kgd);

	return 0;
}

static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	struct cik_sdma_rlc_registers *m;
	uint32_t sdma_base_addr;

	m = get_sdma_mqd(mqd);
	sdma_base_addr = get_sdma_base_addr(m);

	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
			m->sdma_rlc_virtual_addr);

	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE,
			m->sdma_rlc_rb_base);

	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
			m->sdma_rlc_rb_base_hi);

	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
			m->sdma_rlc_rb_rptr_addr_lo);

	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
			m->sdma_rlc_rb_rptr_addr_hi);

	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
			m->sdma_rlc_doorbell);

	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
			m->sdma_rlc_rb_cntl);

	return 0;
}

static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
				uint32_t pipe_id, uint32_t queue_id)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	uint32_t act;
	bool retval = false;
	uint32_t low, high;

	acquire_queue(kgd, pipe_id, queue_id);
	act = RREG32(mmCP_HQD_ACTIVE);
	if (act) {
		low = lower_32_bits(queue_address >> 8);
		high = upper_32_bits(queue_address >> 8);

		if (low == RREG32(mmCP_HQD_PQ_BASE) &&
				high == RREG32(mmCP_HQD_PQ_BASE_HI))
			retval = true;
	}
	release_queue(kgd);
	return retval;
}

static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	struct cik_sdma_rlc_registers *m;
	uint32_t sdma_base_addr;
	uint32_t sdma_rlc_rb_cntl;

	m = get_sdma_mqd(mqd);
	sdma_base_addr = get_sdma_base_addr(m);

	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);

	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
		return true;

	return false;
}

static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
				unsigned int utimeout, uint32_t pipe_id,
				uint32_t queue_id)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	uint32_t temp;
	int timeout = utimeout;

	acquire_queue(kgd, pipe_id, queue_id);
	WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);

	WREG32(mmCP_HQD_DEQUEUE_REQUEST, reset_type);

	while (true) {
		temp = RREG32(mmCP_HQD_ACTIVE);
		if (temp & CP_HQD_ACTIVE__ACTIVE_MASK)
			break;
		if (timeout <= 0) {
			pr_err("kfd: cp queue preemption time out.\n");
			release_queue(kgd);
			return -ETIME;
		}
		msleep(20);
		timeout -= 20;
	}

	release_queue(kgd);
	return 0;
}

static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
				unsigned int utimeout)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	struct cik_sdma_rlc_registers *m;
	uint32_t sdma_base_addr;
	uint32_t temp;
	int timeout = utimeout;

	m = get_sdma_mqd(mqd);
	sdma_base_addr = get_sdma_base_addr(m);

	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);

	while (true) {
		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
		if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
			break;
		if (timeout <= 0)
			return -ETIME;
		msleep(20);
		timeout -= 20;
	}

	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);

	return 0;
}

static int kgd_address_watch_disable(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	union TCP_WATCH_CNTL_BITS cntl;
	unsigned int i;

	cntl.u32All = 0;

	cntl.bitfields.valid = 0;
	cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
	cntl.bitfields.atc = 1;

	/* Turning off this address until we set all the registers */
	for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
		WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
			ADDRESS_WATCH_REG_CNTL], cntl.u32All);

	return 0;
}

static int kgd_address_watch_execute(struct kgd_dev *kgd,
					unsigned int watch_point_id,
					uint32_t cntl_val,
					uint32_t addr_hi,
					uint32_t addr_lo)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	union TCP_WATCH_CNTL_BITS cntl;

	cntl.u32All = cntl_val;

	/* Turning off this watch point until we set all the registers */
	cntl.bitfields.valid = 0;
	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
		ADDRESS_WATCH_REG_CNTL], cntl.u32All);

	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
		ADDRESS_WATCH_REG_ADDR_HI], addr_hi);

	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
		ADDRESS_WATCH_REG_ADDR_LO], addr_lo);

	/* Enable the watch point */
	cntl.bitfields.valid = 1;

	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
		ADDRESS_WATCH_REG_CNTL], cntl.u32All);

	return 0;
}

static int kgd_wave_control_execute(struct kgd_dev *kgd,
					uint32_t gfx_index_val,
					uint32_t sq_cmd)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	uint32_t data;

	mutex_lock(&adev->grbm_idx_mutex);

	WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
	WREG32(mmSQ_CMD, sq_cmd);

	/*  Restore the GRBM_GFX_INDEX register  */

	data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK |
		GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
		GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;

	WREG32(mmGRBM_GFX_INDEX, data);

	mutex_unlock(&adev->grbm_idx_mutex);

	return 0;
}

static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
					unsigned int watch_point_id,
					unsigned int reg_offset)
{
	return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
}

static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
							uint8_t vmid)
{
	uint32_t reg;
	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;

	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
}

static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
								uint8_t vmid)
{
	uint32_t reg;
	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;

	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
}

static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
{
	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;

	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
}

static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
{
	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
	const union amdgpu_firmware_header *hdr;

	BUG_ON(kgd == NULL);

	switch (type) {
	case KGD_ENGINE_PFP:
		hdr = (const union amdgpu_firmware_header *)
							adev->gfx.pfp_fw->data;
		break;

	case KGD_ENGINE_ME:
		hdr = (const union amdgpu_firmware_header *)
							adev->gfx.me_fw->data;
		break;

	case KGD_ENGINE_CE:
		hdr = (const union amdgpu_firmware_header *)
							adev->gfx.ce_fw->data;
		break;

	case KGD_ENGINE_MEC1:
		hdr = (const union amdgpu_firmware_header *)
							adev->gfx.mec_fw->data;
		break;

	case KGD_ENGINE_MEC2:
		hdr = (const union amdgpu_firmware_header *)
							adev->gfx.mec2_fw->data;
		break;

	case KGD_ENGINE_RLC:
		hdr = (const union amdgpu_firmware_header *)
							adev->gfx.rlc_fw->data;
		break;

	case KGD_ENGINE_SDMA1:
		hdr = (const union amdgpu_firmware_header *)
							adev->sdma.instance[0].fw->data;
		break;

	case KGD_ENGINE_SDMA2:
		hdr = (const union amdgpu_firmware_header *)
							adev->sdma.instance[1].fw->data;
		break;

	default:
		return 0;
	}

	if (hdr == NULL)
		return 0;

	/* Only 12 bit in use*/
	return hdr->common.ucode_version;
}
Commit	Line	Data
32c22e99 OG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	#include <linux/fdtable.h>
	24	#include <linux/uaccess.h>
	25	#include <linux/firmware.h>
	26	#include <drm/drmP.h>
	27	#include "amdgpu.h"
	28	#include "amdgpu_amdkfd.h"
	29	#include "cikd.h"
	30	#include "cik_sdma.h"
	31	#include "amdgpu_ucode.h"
97bf47b2	32	#include "gfx_v7_0.h"
32c22e99 OG	33	#include "gca/gfx_7_2_d.h"
	34	#include "gca/gfx_7_2_enum.h"
	35	#include "gca/gfx_7_2_sh_mask.h"
	36	#include "oss/oss_2_0_d.h"
	37	#include "oss/oss_2_0_sh_mask.h"
	38	#include "gmc/gmc_7_1_d.h"
	39	#include "gmc/gmc_7_1_sh_mask.h"
	40	#include "cik_structs.h"
	41
	42	#define CIK_PIPE_PER_MEC (4)
	43
	44	enum {
	45	MAX_TRAPID = 8, /* 3 bits in the bitfield. */
	46	MAX_WATCH_ADDRESSES = 4
	47	};
	48
	49	enum {
	50	ADDRESS_WATCH_REG_ADDR_HI = 0,
	51	ADDRESS_WATCH_REG_ADDR_LO,
	52	ADDRESS_WATCH_REG_CNTL,
	53	ADDRESS_WATCH_REG_MAX
	54	};
	55
	56	/* not defined in the CI/KV reg file */
	57	enum {
	58	ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
	59	ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
	60	ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
	61	/* extend the mask to 26 bits to match the low address field */
	62	ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
	63	ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
	64	};
	65
	66	static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
	67	mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
	68	mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
	69	mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
	70	mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
	71	};
	72
	73	union TCP_WATCH_CNTL_BITS {
	74	struct {
	75	uint32_t mask:24;
	76	uint32_t vmid:4;
	77	uint32_t atc:1;
	78	uint32_t mode:2;
	79	uint32_t valid:1;
	80	} bitfields, bits;
	81	uint32_t u32All;
	82	signed int i32All;
	83	float f32All;
	84	};
	85
	86	/*
	87	* Register access functions
	88	*/
	89
	90	static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
	91	uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
	92	uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
	93
	94	static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
	95	unsigned int vmid);
	96
97	static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
98	uint32_t hpd_size, uint64_t hpd_gpu_addr);
99	static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
100	static int kgd_hqd_load(struct kgd_dev kgd, void mqd, uint32_t pipe_id,
101	uint32_t queue_id, uint32_t __user *wptr);
102	static int kgd_hqd_sdma_load(struct kgd_dev kgd, void mqd);
103	static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
104	uint32_t pipe_id, uint32_t queue_id);
105
106	static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
1d602430	107	unsigned int utimeout, uint32_t pipe_id,
32c22e99 OG	108	uint32_t queue_id);
	109	static bool kgd_hqd_sdma_is_occupied(struct kgd_dev kgd, void mqd);
	110	static int kgd_hqd_sdma_destroy(struct kgd_dev kgd, void mqd,
1d602430	111	unsigned int utimeout);
32c22e99 OG	112	static int kgd_address_watch_disable(struct kgd_dev *kgd);
	113	static int kgd_address_watch_execute(struct kgd_dev *kgd,
	114	unsigned int watch_point_id,
	115	uint32_t cntl_val,
	116	uint32_t addr_hi,
	117	uint32_t addr_lo);
	118	static int kgd_wave_control_execute(struct kgd_dev *kgd,
	119	uint32_t gfx_index_val,
	120	uint32_t sq_cmd);
	121	static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
	122	unsigned int watch_point_id,
	123	unsigned int reg_offset);
	124
	125	static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
	126	static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
	127	uint8_t vmid);
	128	static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
	129
	130	static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
	131
	132	static const struct kfd2kgd_calls kfd2kgd = {
	133	.init_gtt_mem_allocation = alloc_gtt_mem,
	134	.free_gtt_mem = free_gtt_mem,
	135	.get_vmem_size = get_vmem_size,
	136	.get_gpu_clock_counter = get_gpu_clock_counter,
	137	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
	138	.program_sh_mem_settings = kgd_program_sh_mem_settings,
	139	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
	140	.init_pipeline = kgd_init_pipeline,
	141	.init_interrupts = kgd_init_interrupts,
	142	.hqd_load = kgd_hqd_load,
	143	.hqd_sdma_load = kgd_hqd_sdma_load,
	144	.hqd_is_occupied = kgd_hqd_is_occupied,
	145	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
	146	.hqd_destroy = kgd_hqd_destroy,
	147	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
	148	.address_watch_disable = kgd_address_watch_disable,
	149	.address_watch_execute = kgd_address_watch_execute,
	150	.wave_control_execute = kgd_wave_control_execute,
	151	.address_watch_get_offset = kgd_address_watch_get_offset,
	152	.get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
	153	.get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
	154	.write_vmid_invalidate_request = write_vmid_invalidate_request,
	155	.get_fw_version = get_fw_version
	156	};
	157
f785d987	158	struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
32c22e99 OG	159	{
	160	return (struct kfd2kgd_calls *)&kfd2kgd;
	161	}
	162
	163	static inline struct amdgpu_device get_amdgpu_device(struct kgd_dev kgd)
	164	{
	165	return (struct amdgpu_device *)kgd;
	166	}
	167
	168	static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
	169	uint32_t queue, uint32_t vmid)
	170	{
	171	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	172	uint32_t value = PIPEID(pipe) \| MEID(mec) \| VMID(vmid) \| QUEUEID(queue);
	173
	174	mutex_lock(&adev->srbm_mutex);
	175	WREG32(mmSRBM_GFX_CNTL, value);
	176	}
	177
	178	static void unlock_srbm(struct kgd_dev *kgd)
	179	{
	180	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	181
	182	WREG32(mmSRBM_GFX_CNTL, 0);
	183	mutex_unlock(&adev->srbm_mutex);
	184	}
	185
	186	static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
	187	uint32_t queue_id)
	188	{
	189	uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
	190	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
	191
	192	lock_srbm(kgd, mec, pipe, queue_id, 0);
	193	}
	194
	195	static void release_queue(struct kgd_dev *kgd)
	196	{
	197	unlock_srbm(kgd);
	198	}
	199
	200	static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
	201	uint32_t sh_mem_config,
	202	uint32_t sh_mem_ape1_base,
	203	uint32_t sh_mem_ape1_limit,
	204	uint32_t sh_mem_bases)
	205	{
	206	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	207
	208	lock_srbm(kgd, 0, 0, 0, vmid);
	209
	210	WREG32(mmSH_MEM_CONFIG, sh_mem_config);
	211	WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
	212	WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
	213	WREG32(mmSH_MEM_BASES, sh_mem_bases);
	214
	215	unlock_srbm(kgd);
	216	}
	217
	218	static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
	219	unsigned int vmid)
	220	{
	221	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	222
223	/*
224	* We have to assume that there is no outstanding mapping.
225	* The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
226	* a mapping is in progress or because a mapping finished and the
227	* SW cleared it. So the protocol is to always wait & clear.
228	*/
229	uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid \|
230	ATC_VMID0_PASID_MAPPING__VALID_MASK;
231
232	WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
233
234	while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
235	cpu_relax();
236	WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
237
238	/* Mapping vmid to pasid also for IH block */
239	WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
240
241	return 0;
242	}
243
244	static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
245	uint32_t hpd_size, uint64_t hpd_gpu_addr)
246	{
247	struct amdgpu_device *adev = get_amdgpu_device(kgd);
248
249	uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
250	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
251
252	lock_srbm(kgd, mec, pipe, 0, 0);
253	WREG32(mmCP_HPD_EOP_BASE_ADDR, lower_32_bits(hpd_gpu_addr >> 8));
254	WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(hpd_gpu_addr >> 8));
255	WREG32(mmCP_HPD_EOP_VMID, 0);
256	WREG32(mmCP_HPD_EOP_CONTROL, hpd_size);
257	unlock_srbm(kgd);
258
259	return 0;
260	}
261
262	static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
263	{
264	struct amdgpu_device *adev = get_amdgpu_device(kgd);
265	uint32_t mec;
266	uint32_t pipe;
267
268	mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
269	pipe = (pipe_id % CIK_PIPE_PER_MEC);
270
271	lock_srbm(kgd, mec, pipe, 0, 0);
272
273	WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK \|
274	CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
275
276	unlock_srbm(kgd);
277
278	return 0;
279	}
280
281	static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
282	{
283	uint32_t retval;
284
285	retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
286	m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
287
288	pr_debug("kfd: sdma base address: 0x%x\n", retval);
289
290	return retval;
291	}
292
293	static inline struct cik_mqd get_mqd(void mqd)
294	{
295	return (struct cik_mqd *)mqd;
296	}
297
298	static inline struct cik_sdma_rlc_registers get_sdma_mqd(void mqd)
299	{
300	return (struct cik_sdma_rlc_registers *)mqd;
301	}
302
303	static int kgd_hqd_load(struct kgd_dev kgd, void mqd, uint32_t pipe_id,
304	uint32_t queue_id, uint32_t __user *wptr)
305	{
306	struct amdgpu_device *adev = get_amdgpu_device(kgd);
307	uint32_t wptr_shadow, is_wptr_shadow_valid;
308	struct cik_mqd *m;
309
310	m = get_mqd(mqd);
311
312	is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
32c22e99	313	if (is_wptr_shadow_valid)
97bf47b2	314	m->cp_hqd_pq_wptr = wptr_shadow;
32c22e99	315
97bf47b2 AR	316	acquire_queue(kgd, pipe_id, queue_id);
97bf47b2 AR	317	gfx_v7_0_mqd_commit(adev, m);
32c22e99 OG	318	release_queue(kgd);
	319
	320	return 0;
	321	}
	322
	323	static int kgd_hqd_sdma_load(struct kgd_dev kgd, void mqd)
	324	{
	325	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	326	struct cik_sdma_rlc_registers *m;
	327	uint32_t sdma_base_addr;
	328
	329	m = get_sdma_mqd(mqd);
	330	sdma_base_addr = get_sdma_base_addr(m);
	331
	332	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
	333	m->sdma_rlc_virtual_addr);
	334
	335	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE,
	336	m->sdma_rlc_rb_base);
	337
	338	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
	339	m->sdma_rlc_rb_base_hi);
	340
	341	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
	342	m->sdma_rlc_rb_rptr_addr_lo);
	343
	344	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
	345	m->sdma_rlc_rb_rptr_addr_hi);
	346
	347	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
	348	m->sdma_rlc_doorbell);
	349
	350	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
	351	m->sdma_rlc_rb_cntl);
	352
	353	return 0;
	354	}
	355
	356	static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
	357	uint32_t pipe_id, uint32_t queue_id)
	358	{
	359	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	360	uint32_t act;
	361	bool retval = false;
	362	uint32_t low, high;
	363
	364	acquire_queue(kgd, pipe_id, queue_id);
	365	act = RREG32(mmCP_HQD_ACTIVE);
	366	if (act) {
	367	low = lower_32_bits(queue_address >> 8);
	368	high = upper_32_bits(queue_address >> 8);
	369
	370	if (low == RREG32(mmCP_HQD_PQ_BASE) &&
	371	high == RREG32(mmCP_HQD_PQ_BASE_HI))
	372	retval = true;
	373	}
	374	release_queue(kgd);
	375	return retval;
	376	}
	377
	378	static bool kgd_hqd_sdma_is_occupied(struct kgd_dev kgd, void mqd)
	379	{
	380	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	381	struct cik_sdma_rlc_registers *m;
382	uint32_t sdma_base_addr;
383	uint32_t sdma_rlc_rb_cntl;
384
385	m = get_sdma_mqd(mqd);
386	sdma_base_addr = get_sdma_base_addr(m);
387
388	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
389
390	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
391	return true;
392
393	return false;
394	}
395
396	static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
1d602430	397	unsigned int utimeout, uint32_t pipe_id,
32c22e99 OG	398	uint32_t queue_id)
	399	{
	400	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	401	uint32_t temp;
1d602430	402	int timeout = utimeout;
32c22e99 OG	403
	404	acquire_queue(kgd, pipe_id, queue_id);
	405	WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
	406
	407	WREG32(mmCP_HQD_DEQUEUE_REQUEST, reset_type);
	408
	409	while (true) {
	410	temp = RREG32(mmCP_HQD_ACTIVE);
e8a64b20	411	if (temp & CP_HQD_ACTIVE__ACTIVE_MASK)
32c22e99	412	break;
1d602430 EC	413	if (timeout <= 0) {
1d602430 EC	414	pr_err("kfd: cp queue preemption time out.\n");
32c22e99 OG	415	release_queue(kgd);
	416	return -ETIME;
	417	}
	418	msleep(20);
	419	timeout -= 20;
	420	}
	421
	422	release_queue(kgd);
	423	return 0;
	424	}
	425
	426	static int kgd_hqd_sdma_destroy(struct kgd_dev kgd, void mqd,
1d602430	427	unsigned int utimeout)
32c22e99 OG	428	{
	429	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	430	struct cik_sdma_rlc_registers *m;
	431	uint32_t sdma_base_addr;
	432	uint32_t temp;
1d602430	433	int timeout = utimeout;
32c22e99 OG	434
	435	m = get_sdma_mqd(mqd);
	436	sdma_base_addr = get_sdma_base_addr(m);
	437
	438	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
	439	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
	440	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
	441
	442	while (true) {
	443	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
	444	if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
	445	break;
1d602430	446	if (timeout <= 0)
32c22e99 OG	447	return -ETIME;
	448	msleep(20);
	449	timeout -= 20;
	450	}
	451
	452	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
	453	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
	454	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
	455	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
	456
	457	return 0;
	458	}
	459
	460	static int kgd_address_watch_disable(struct kgd_dev *kgd)
	461	{
	462	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	463	union TCP_WATCH_CNTL_BITS cntl;
	464	unsigned int i;
	465
	466	cntl.u32All = 0;
	467
	468	cntl.bitfields.valid = 0;
	469	cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
	470	cntl.bitfields.atc = 1;
	471
	472	/* Turning off this address until we set all the registers */
	473	for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
	474	WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
	475	ADDRESS_WATCH_REG_CNTL], cntl.u32All);
	476
	477	return 0;
	478	}
	479
	480	static int kgd_address_watch_execute(struct kgd_dev *kgd,
	481	unsigned int watch_point_id,
	482	uint32_t cntl_val,
	483	uint32_t addr_hi,
	484	uint32_t addr_lo)
	485	{
	486	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	487	union TCP_WATCH_CNTL_BITS cntl;
	488
	489	cntl.u32All = cntl_val;
	490
	491	/* Turning off this watch point until we set all the registers */
	492	cntl.bitfields.valid = 0;
	493	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
	494	ADDRESS_WATCH_REG_CNTL], cntl.u32All);
	495
	496	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
	497	ADDRESS_WATCH_REG_ADDR_HI], addr_hi);
	498
	499	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
	500	ADDRESS_WATCH_REG_ADDR_LO], addr_lo);
	501
	502	/* Enable the watch point */
	503	cntl.bitfields.valid = 1;
	504
	505	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
	506	ADDRESS_WATCH_REG_CNTL], cntl.u32All);
	507
	508	return 0;
	509	}
	510
511	static int kgd_wave_control_execute(struct kgd_dev *kgd,
512	uint32_t gfx_index_val,
513	uint32_t sq_cmd)
514	{
515	struct amdgpu_device *adev = get_amdgpu_device(kgd);
516	uint32_t data;
517
518	mutex_lock(&adev->grbm_idx_mutex);
519
520	WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
521	WREG32(mmSQ_CMD, sq_cmd);
522
523	/* Restore the GRBM_GFX_INDEX register */
524
525	data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK \|
526	GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK \|
527	GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
528
529	WREG32(mmGRBM_GFX_INDEX, data);
530
531	mutex_unlock(&adev->grbm_idx_mutex);
532
533	return 0;
534	}
535
536	static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
537	unsigned int watch_point_id,
538	unsigned int reg_offset)
539	{
540	return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
541	}
542
543	static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
544	uint8_t vmid)
545	{
546	uint32_t reg;
547	struct amdgpu_device adev = (struct amdgpu_device ) kgd;
548
549	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
550	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
551	}
552
553	static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
554	uint8_t vmid)
555	{
556	uint32_t reg;
557	struct amdgpu_device adev = (struct amdgpu_device ) kgd;
558
559	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
560	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
561	}
562
563	static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
564	{
565	struct amdgpu_device adev = (struct amdgpu_device ) kgd;
566
567	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
568	}
569
570	static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
571	{
572	struct amdgpu_device adev = (struct amdgpu_device ) kgd;
573	const union amdgpu_firmware_header *hdr;
574
575	BUG_ON(kgd == NULL);
576
577	switch (type) {
578	case KGD_ENGINE_PFP:
579	hdr = (const union amdgpu_firmware_header *)
580	adev->gfx.pfp_fw->data;
581	break;
582
583	case KGD_ENGINE_ME:
584	hdr = (const union amdgpu_firmware_header *)
585	adev->gfx.me_fw->data;
586	break;
587
588	case KGD_ENGINE_CE:
589	hdr = (const union amdgpu_firmware_header *)
590	adev->gfx.ce_fw->data;
591	break;
592
593	case KGD_ENGINE_MEC1:
594	hdr = (const union amdgpu_firmware_header *)
595	adev->gfx.mec_fw->data;
596	break;
597
598	case KGD_ENGINE_MEC2:
599	hdr = (const union amdgpu_firmware_header *)
600	adev->gfx.mec2_fw->data;
601	break;
602
603	case KGD_ENGINE_RLC:
604	hdr = (const union amdgpu_firmware_header *)
605	adev->gfx.rlc_fw->data;
606	break;
607
608	case KGD_ENGINE_SDMA1:
609	hdr = (const union amdgpu_firmware_header *)
c113ea1c	610	adev->sdma.instance[0].fw->data;
32c22e99 OG	611	break;
	612
	613	case KGD_ENGINE_SDMA2:
	614	hdr = (const union amdgpu_firmware_header *)
c113ea1c	615	adev->sdma.instance[1].fw->data;
32c22e99 OG	616	break;
	617
	618	default:
	619	return 0;
	620	}
	621
	622	if (hdr == NULL)
	623	return 0;
	624
	625	/* Only 12 bit in use*/
	626	return hdr->common.ucode_version;
	627	}
	628