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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #ifndef __AMDGPU_ATOMBIOS_H__ | |
25 | #define __AMDGPU_ATOMBIOS_H__ | |
26 | ||
27 | struct atom_clock_dividers { | |
28 | u32 post_div; | |
29 | union { | |
30 | struct { | |
31 | #ifdef __BIG_ENDIAN | |
32 | u32 reserved : 6; | |
33 | u32 whole_fb_div : 12; | |
34 | u32 frac_fb_div : 14; | |
35 | #else | |
36 | u32 frac_fb_div : 14; | |
37 | u32 whole_fb_div : 12; | |
38 | u32 reserved : 6; | |
39 | #endif | |
40 | }; | |
41 | u32 fb_div; | |
42 | }; | |
43 | u32 ref_div; | |
44 | bool enable_post_div; | |
45 | bool enable_dithen; | |
46 | u32 vco_mode; | |
47 | u32 real_clock; | |
48 | /* added for CI */ | |
49 | u32 post_divider; | |
50 | u32 flags; | |
51 | }; | |
52 | ||
53 | struct atom_mpll_param { | |
54 | union { | |
55 | struct { | |
56 | #ifdef __BIG_ENDIAN | |
57 | u32 reserved : 8; | |
58 | u32 clkfrac : 12; | |
59 | u32 clkf : 12; | |
60 | #else | |
61 | u32 clkf : 12; | |
62 | u32 clkfrac : 12; | |
63 | u32 reserved : 8; | |
64 | #endif | |
65 | }; | |
66 | u32 fb_div; | |
67 | }; | |
68 | u32 post_div; | |
69 | u32 bwcntl; | |
70 | u32 dll_speed; | |
71 | u32 vco_mode; | |
72 | u32 yclk_sel; | |
73 | u32 qdr; | |
74 | u32 half_rate; | |
75 | }; | |
76 | ||
77 | #define MEM_TYPE_GDDR5 0x50 | |
78 | #define MEM_TYPE_GDDR4 0x40 | |
79 | #define MEM_TYPE_GDDR3 0x30 | |
80 | #define MEM_TYPE_DDR2 0x20 | |
81 | #define MEM_TYPE_GDDR1 0x10 | |
82 | #define MEM_TYPE_DDR3 0xb0 | |
83 | #define MEM_TYPE_MASK 0xf0 | |
84 | ||
85 | struct atom_memory_info { | |
86 | u8 mem_vendor; | |
87 | u8 mem_type; | |
88 | }; | |
89 | ||
90 | #define MAX_AC_TIMING_ENTRIES 16 | |
91 | ||
92 | struct atom_memory_clock_range_table | |
93 | { | |
94 | u8 num_entries; | |
95 | u8 rsv[3]; | |
96 | u32 mclk[MAX_AC_TIMING_ENTRIES]; | |
97 | }; | |
98 | ||
99 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 | |
100 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 | |
101 | ||
102 | struct atom_mc_reg_entry { | |
103 | u32 mclk_max; | |
104 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; | |
105 | }; | |
106 | ||
107 | struct atom_mc_register_address { | |
108 | u16 s1; | |
109 | u8 pre_reg_data; | |
110 | }; | |
111 | ||
112 | struct atom_mc_reg_table { | |
113 | u8 last; | |
114 | u8 num_entries; | |
115 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; | |
116 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; | |
117 | }; | |
118 | ||
119 | #define MAX_VOLTAGE_ENTRIES 32 | |
120 | ||
121 | struct atom_voltage_table_entry | |
122 | { | |
123 | u16 value; | |
124 | u32 smio_low; | |
125 | }; | |
126 | ||
127 | struct atom_voltage_table | |
128 | { | |
129 | u32 count; | |
130 | u32 mask_low; | |
131 | u32 phase_delay; | |
132 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; | |
133 | }; | |
134 | ||
135 | struct amdgpu_gpio_rec | |
136 | amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, | |
137 | u8 id); | |
138 | ||
139 | struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, | |
140 | uint8_t id); | |
141 | void amdgpu_atombios_i2c_init(struct amdgpu_device *adev); | |
142 | ||
0bad1619 ED |
143 | bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev); |
144 | ||
d38ceaf9 AD |
145 | bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev); |
146 | ||
147 | int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev); | |
148 | ||
397a270e AD |
149 | int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev); |
150 | ||
1ce65f52 HW |
151 | int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev); |
152 | ||
d38ceaf9 AD |
153 | bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, |
154 | struct amdgpu_atom_ss *ss, | |
155 | int id, u32 clock); | |
156 | ||
157 | int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, | |
158 | u8 clock_type, | |
159 | u32 clock, | |
160 | bool strobe_mode, | |
161 | struct atom_clock_dividers *dividers); | |
162 | ||
163 | int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, | |
164 | u32 clock, | |
165 | bool strobe_mode, | |
166 | struct atom_mpll_param *mpll_param); | |
167 | ||
d38ceaf9 AD |
168 | void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, |
169 | u32 eng_clock, u32 mem_clock); | |
170 | ||
171 | int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, | |
172 | u16 *leakage_id); | |
173 | ||
174 | int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev, | |
175 | u16 *vddc, u16 *vddci, | |
176 | u16 virtual_voltage_id, | |
177 | u16 vbios_voltage_id); | |
178 | ||
179 | int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev, | |
180 | u16 virtual_voltage_id, | |
181 | u16 *voltage); | |
182 | ||
183 | bool | |
184 | amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, | |
185 | u8 voltage_type, u8 voltage_mode); | |
186 | ||
187 | int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, | |
188 | u8 voltage_type, u8 voltage_mode, | |
189 | struct atom_voltage_table *voltage_table); | |
190 | ||
191 | int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, | |
192 | u8 module_index, | |
193 | struct atom_mc_reg_table *reg_table); | |
194 | ||
e74adf20 AD |
195 | bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev); |
196 | ||
d38ceaf9 | 197 | void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock); |
72a57438 AD |
198 | void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, |
199 | bool hung); | |
4426826c | 200 | bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev); |
d38ceaf9 AD |
201 | |
202 | void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); | |
9139d731 MSB |
203 | int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type, |
204 | u16 voltage_id, u16 *voltage); | |
205 | int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev, | |
206 | u16 *voltage, | |
207 | u16 leakage_idx); | |
208 | void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev, | |
209 | u16 *vddc, u16 *vddci, u16 *mvdd); | |
210 | int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, | |
211 | u8 clock_type, | |
212 | u32 clock, | |
213 | bool strobe_mode, | |
214 | struct atom_clock_dividers *dividers); | |
215 | int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev, | |
216 | u8 voltage_type, | |
217 | u8 *svd_gpio_id, u8 *svc_gpio_id); | |
43bf11bd | 218 | |
4e89df63 AD |
219 | void amdgpu_atombios_fini(struct amdgpu_device *adev); |
220 | int amdgpu_atombios_init(struct amdgpu_device *adev); | |
43bf11bd | 221 | |
d38ceaf9 | 222 | #endif |