[mirror_ubuntu-kernels.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cgs.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 *
 */
#include <linux/list.h>
#include <linux/pci.h>
#include <linux/slab.h>

#include <linux/firmware.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "atom.h"
#include "amdgpu_ucode.h"

struct amdgpu_cgs_device {
	struct cgs_device base;
	struct amdgpu_device *adev;
};

#define CGS_FUNC_ADEV							\
	struct amdgpu_device *adev =					\
		((struct amdgpu_cgs_device *)cgs_device)->adev


static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
{
	CGS_FUNC_ADEV;
	return RREG32(offset);
}

static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
				      uint32_t value)
{
	CGS_FUNC_ADEV;
	WREG32(offset, value);
}

static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
					     enum cgs_ind_reg space,
					     unsigned index)
{
	CGS_FUNC_ADEV;
	switch (space) {
	case CGS_IND_REG__MMIO:
		return RREG32_IDX(index);
	case CGS_IND_REG__PCIE:
		return RREG32_PCIE(index);
	case CGS_IND_REG__SMC:
		return RREG32_SMC(index);
	case CGS_IND_REG__UVD_CTX:
		return RREG32_UVD_CTX(index);
	case CGS_IND_REG__DIDT:
		return RREG32_DIDT(index);
	case CGS_IND_REG_GC_CAC:
		return RREG32_GC_CAC(index);
	case CGS_IND_REG_SE_CAC:
		return RREG32_SE_CAC(index);
	case CGS_IND_REG__AUDIO_ENDPT:
		DRM_ERROR("audio endpt register access not implemented.\n");
		return 0;
	}
	WARN(1, "Invalid indirect register space");
	return 0;
}

static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
					  enum cgs_ind_reg space,
					  unsigned index, uint32_t value)
{
	CGS_FUNC_ADEV;
	switch (space) {
	case CGS_IND_REG__MMIO:
		return WREG32_IDX(index, value);
	case CGS_IND_REG__PCIE:
		return WREG32_PCIE(index, value);
	case CGS_IND_REG__SMC:
		return WREG32_SMC(index, value);
	case CGS_IND_REG__UVD_CTX:
		return WREG32_UVD_CTX(index, value);
	case CGS_IND_REG__DIDT:
		return WREG32_DIDT(index, value);
	case CGS_IND_REG_GC_CAC:
		return WREG32_GC_CAC(index, value);
	case CGS_IND_REG_SE_CAC:
		return WREG32_SE_CAC(index, value);
	case CGS_IND_REG__AUDIO_ENDPT:
		DRM_ERROR("audio endpt register access not implemented.\n");
		return;
	}
	WARN(1, "Invalid indirect register space");
}

static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
{
	CGS_FUNC_ADEV;
	enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;

	switch (fw_type) {
	case CGS_UCODE_ID_SDMA0:
		result = AMDGPU_UCODE_ID_SDMA0;
		break;
	case CGS_UCODE_ID_SDMA1:
		result = AMDGPU_UCODE_ID_SDMA1;
		break;
	case CGS_UCODE_ID_CP_CE:
		result = AMDGPU_UCODE_ID_CP_CE;
		break;
	case CGS_UCODE_ID_CP_PFP:
		result = AMDGPU_UCODE_ID_CP_PFP;
		break;
	case CGS_UCODE_ID_CP_ME:
		result = AMDGPU_UCODE_ID_CP_ME;
		break;
	case CGS_UCODE_ID_CP_MEC:
	case CGS_UCODE_ID_CP_MEC_JT1:
		result = AMDGPU_UCODE_ID_CP_MEC1;
		break;
	case CGS_UCODE_ID_CP_MEC_JT2:
		/* for VI. JT2 should be the same as JT1, because:
			1, MEC2 and MEC1 use exactly same FW.
			2, JT2 is not pached but JT1 is.
		*/
		if (adev->asic_type >= CHIP_TOPAZ)
			result = AMDGPU_UCODE_ID_CP_MEC1;
		else
			result = AMDGPU_UCODE_ID_CP_MEC2;
		break;
	case CGS_UCODE_ID_RLC_G:
		result = AMDGPU_UCODE_ID_RLC_G;
		break;
	case CGS_UCODE_ID_STORAGE:
		result = AMDGPU_UCODE_ID_STORAGE;
		break;
	default:
		DRM_ERROR("Firmware type not supported\n");
	}
	return result;
}

static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
					enum cgs_ucode_id type)
{
	CGS_FUNC_ADEV;
	uint16_t fw_version = 0;

	switch (type) {
		case CGS_UCODE_ID_SDMA0:
			fw_version = adev->sdma.instance[0].fw_version;
			break;
		case CGS_UCODE_ID_SDMA1:
			fw_version = adev->sdma.instance[1].fw_version;
			break;
		case CGS_UCODE_ID_CP_CE:
			fw_version = adev->gfx.ce_fw_version;
			break;
		case CGS_UCODE_ID_CP_PFP:
			fw_version = adev->gfx.pfp_fw_version;
			break;
		case CGS_UCODE_ID_CP_ME:
			fw_version = adev->gfx.me_fw_version;
			break;
		case CGS_UCODE_ID_CP_MEC:
			fw_version = adev->gfx.mec_fw_version;
			break;
		case CGS_UCODE_ID_CP_MEC_JT1:
			fw_version = adev->gfx.mec_fw_version;
			break;
		case CGS_UCODE_ID_CP_MEC_JT2:
			fw_version = adev->gfx.mec_fw_version;
			break;
		case CGS_UCODE_ID_RLC_G:
			fw_version = adev->gfx.rlc_fw_version;
			break;
		case CGS_UCODE_ID_STORAGE:
			break;
		default:
			DRM_ERROR("firmware type %d do not have version\n", type);
			break;
	}
	return fw_version;
}

static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
					enum cgs_ucode_id type,
					struct cgs_firmware_info *info)
{
	CGS_FUNC_ADEV;

	if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
		uint64_t gpu_addr;
		uint32_t data_size;
		const struct gfx_firmware_header_v1_0 *header;
		enum AMDGPU_UCODE_ID id;
		struct amdgpu_firmware_info *ucode;

		id = fw_type_convert(cgs_device, type);
		ucode = &adev->firmware.ucode[id];
		if (ucode->fw == NULL)
			return -EINVAL;

		gpu_addr  = ucode->mc_addr;
		header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
		data_size = le32_to_cpu(header->header.ucode_size_bytes);

		if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
		    (type == CGS_UCODE_ID_CP_MEC_JT2)) {
			gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
			data_size = le32_to_cpu(header->jt_size) << 2;
		}

		info->kptr = ucode->kaddr;
		info->image_size = data_size;
		info->mc_addr = gpu_addr;
		info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);

		if (CGS_UCODE_ID_CP_MEC == type)
			info->image_size = le32_to_cpu(header->jt_offset) << 2;

		info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
		info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
	} else {
		char fw_name[30] = {0};
		int err = 0;
		uint32_t ucode_size;
		uint32_t ucode_start_address;
		const uint8_t *src;
		const struct smc_firmware_header_v1_0 *hdr;
		const struct common_firmware_header *header;
		struct amdgpu_firmware_info *ucode = NULL;

		if (!adev->pm.fw) {
			switch (adev->asic_type) {
			case CHIP_TAHITI:
				strcpy(fw_name, "radeon/tahiti_smc.bin");
				break;
			case CHIP_PITCAIRN:
				if ((adev->pdev->revision == 0x81) &&
				    ((adev->pdev->device == 0x6810) ||
				    (adev->pdev->device == 0x6811))) {
					info->is_kicker = true;
					strcpy(fw_name, "radeon/pitcairn_k_smc.bin");
				} else {
					strcpy(fw_name, "radeon/pitcairn_smc.bin");
				}
				break;
			case CHIP_VERDE:
				if (((adev->pdev->device == 0x6820) &&
					((adev->pdev->revision == 0x81) ||
					(adev->pdev->revision == 0x83))) ||
				    ((adev->pdev->device == 0x6821) &&
					((adev->pdev->revision == 0x83) ||
					(adev->pdev->revision == 0x87))) ||
				    ((adev->pdev->revision == 0x87) &&
					((adev->pdev->device == 0x6823) ||
					(adev->pdev->device == 0x682b)))) {
					info->is_kicker = true;
					strcpy(fw_name, "radeon/verde_k_smc.bin");
				} else {
					strcpy(fw_name, "radeon/verde_smc.bin");
				}
				break;
			case CHIP_OLAND:
				if (((adev->pdev->revision == 0x81) &&
					((adev->pdev->device == 0x6600) ||
					(adev->pdev->device == 0x6604) ||
					(adev->pdev->device == 0x6605) ||
					(adev->pdev->device == 0x6610))) ||
				    ((adev->pdev->revision == 0x83) &&
					(adev->pdev->device == 0x6610))) {
					info->is_kicker = true;
					strcpy(fw_name, "radeon/oland_k_smc.bin");
				} else {
					strcpy(fw_name, "radeon/oland_smc.bin");
				}
				break;
			case CHIP_HAINAN:
				if (((adev->pdev->revision == 0x81) &&
					(adev->pdev->device == 0x6660)) ||
				    ((adev->pdev->revision == 0x83) &&
					((adev->pdev->device == 0x6660) ||
					(adev->pdev->device == 0x6663) ||
					(adev->pdev->device == 0x6665) ||
					 (adev->pdev->device == 0x6667)))) {
					info->is_kicker = true;
					strcpy(fw_name, "radeon/hainan_k_smc.bin");
				} else if ((adev->pdev->revision == 0xc3) &&
					 (adev->pdev->device == 0x6665)) {
					info->is_kicker = true;
					strcpy(fw_name, "radeon/banks_k_2_smc.bin");
				} else {
					strcpy(fw_name, "radeon/hainan_smc.bin");
				}
				break;
			case CHIP_BONAIRE:
				if ((adev->pdev->revision == 0x80) ||
					(adev->pdev->revision == 0x81) ||
					(adev->pdev->device == 0x665f)) {
					info->is_kicker = true;
					strcpy(fw_name, "amdgpu/bonaire_k_smc.bin");
				} else {
					strcpy(fw_name, "amdgpu/bonaire_smc.bin");
				}
				break;
			case CHIP_HAWAII:
				if (adev->pdev->revision == 0x80) {
					info->is_kicker = true;
					strcpy(fw_name, "amdgpu/hawaii_k_smc.bin");
				} else {
					strcpy(fw_name, "amdgpu/hawaii_smc.bin");
				}
				break;
			case CHIP_TOPAZ:
				if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
				    ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
				    ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)) ||
				    ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD1)) ||
				    ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD3))) {
					info->is_kicker = true;
					strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
				} else
					strcpy(fw_name, "amdgpu/topaz_smc.bin");
				break;
			case CHIP_TONGA:
				if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
				    ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
					info->is_kicker = true;
					strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
				} else
					strcpy(fw_name, "amdgpu/tonga_smc.bin");
				break;
			case CHIP_FIJI:
				strcpy(fw_name, "amdgpu/fiji_smc.bin");
				break;
			case CHIP_POLARIS11:
				if (type == CGS_UCODE_ID_SMU) {
					if (((adev->pdev->device == 0x67ef) &&
					     ((adev->pdev->revision == 0xe0) ||
					      (adev->pdev->revision == 0xe5))) ||
					    ((adev->pdev->device == 0x67ff) &&
					     ((adev->pdev->revision == 0xcf) ||
					      (adev->pdev->revision == 0xef) ||
					      (adev->pdev->revision == 0xff)))) {
						info->is_kicker = true;
						strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
					} else if ((adev->pdev->device == 0x67ef) &&
						   (adev->pdev->revision == 0xe2)) {
						info->is_kicker = true;
						strcpy(fw_name, "amdgpu/polaris11_k2_smc.bin");
					} else {
						strcpy(fw_name, "amdgpu/polaris11_smc.bin");
					}
				} else if (type == CGS_UCODE_ID_SMU_SK) {
					strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
				}
				break;
			case CHIP_POLARIS10:
				if (type == CGS_UCODE_ID_SMU) {
					if (((adev->pdev->device == 0x67df) &&
					     ((adev->pdev->revision == 0xe0) ||
					      (adev->pdev->revision == 0xe3) ||
					      (adev->pdev->revision == 0xe4) ||
					      (adev->pdev->revision == 0xe5) ||
					      (adev->pdev->revision == 0xe7) ||
					      (adev->pdev->revision == 0xef))) ||
					    ((adev->pdev->device == 0x6fdf) &&
					     ((adev->pdev->revision == 0xef) ||
					      (adev->pdev->revision == 0xff)))) {
						info->is_kicker = true;
						strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
					} else if ((adev->pdev->device == 0x67df) &&
						   ((adev->pdev->revision == 0xe1) ||
						    (adev->pdev->revision == 0xf7))) {
						info->is_kicker = true;
						strcpy(fw_name, "amdgpu/polaris10_k2_smc.bin");
					} else {
						strcpy(fw_name, "amdgpu/polaris10_smc.bin");
					}
				} else if (type == CGS_UCODE_ID_SMU_SK) {
					strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
				}
				break;
			case CHIP_POLARIS12:
				if (((adev->pdev->device == 0x6987) &&
				     ((adev->pdev->revision == 0xc0) ||
				      (adev->pdev->revision == 0xc3))) ||
				    ((adev->pdev->device == 0x6981) &&
				     ((adev->pdev->revision == 0x00) ||
				      (adev->pdev->revision == 0x01) ||
				      (adev->pdev->revision == 0x10)))) {
					info->is_kicker = true;
					strcpy(fw_name, "amdgpu/polaris12_k_smc.bin");
				} else {
					strcpy(fw_name, "amdgpu/polaris12_smc.bin");
				}
				break;
			case CHIP_VEGAM:
				strcpy(fw_name, "amdgpu/vegam_smc.bin");
				break;
			case CHIP_VEGA10:
				if ((adev->pdev->device == 0x687f) &&
					((adev->pdev->revision == 0xc0) ||
					(adev->pdev->revision == 0xc1) ||
					(adev->pdev->revision == 0xc3)))
					strcpy(fw_name, "amdgpu/vega10_acg_smc.bin");
				else
					strcpy(fw_name, "amdgpu/vega10_smc.bin");
				break;
			case CHIP_VEGA12:
				strcpy(fw_name, "amdgpu/vega12_smc.bin");
				break;
			case CHIP_VEGA20:
				strcpy(fw_name, "amdgpu/vega20_smc.bin");
				break;
			default:
				DRM_ERROR("SMC firmware not supported\n");
				return -EINVAL;
			}

			err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
			if (err) {
				DRM_ERROR("Failed to request firmware\n");
				return err;
			}

			err = amdgpu_ucode_validate(adev->pm.fw);
			if (err) {
				DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
				release_firmware(adev->pm.fw);
				adev->pm.fw = NULL;
				return err;
			}

			if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
				ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
				ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
				ucode->fw = adev->pm.fw;
				header = (const struct common_firmware_header *)ucode->fw->data;
				adev->firmware.fw_size +=
					ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
			}
		}

		hdr = (const struct smc_firmware_header_v1_0 *)	adev->pm.fw->data;
		amdgpu_ucode_print_smc_hdr(&hdr->header);
		adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
		ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
		ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
		src = (const uint8_t *)(adev->pm.fw->data +
		       le32_to_cpu(hdr->header.ucode_array_offset_bytes));

		info->version = adev->pm.fw_version;
		info->image_size = ucode_size;
		info->ucode_start_address = ucode_start_address;
		info->kptr = (void *)src;
	}
	return 0;
}

static const struct cgs_ops amdgpu_cgs_ops = {
	.read_register = amdgpu_cgs_read_register,
	.write_register = amdgpu_cgs_write_register,
	.read_ind_register = amdgpu_cgs_read_ind_register,
	.write_ind_register = amdgpu_cgs_write_ind_register,
	.get_firmware_info = amdgpu_cgs_get_firmware_info,
};

struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
{
	struct amdgpu_cgs_device *cgs_device =
		kmalloc(sizeof(*cgs_device), GFP_KERNEL);

	if (!cgs_device) {
		DRM_ERROR("Couldn't allocate CGS device structure\n");
		return NULL;
	}

	cgs_device->base.ops = &amdgpu_cgs_ops;
	cgs_device->adev = adev;

	return (struct cgs_device *)cgs_device;
}

void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
{
	kfree(cgs_device);
}
Commit	Line	Data
d03846af CZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*
	23	*/
57ff96cf	24	#include <linux/list.h>
fdf2f6c5	25	#include <linux/pci.h>
57ff96cf	26	#include <linux/slab.h>
fdf2f6c5	27
bf3911b0	28	#include <linux/firmware.h>
57ff96cf	29	#include <drm/amdgpu_drm.h>
d03846af	30	#include "amdgpu.h"
25da4427	31	#include "atom.h"
bf3911b0 JZ	32	#include "amdgpu_ucode.h"
bf3911b0 JZ	33
d03846af CZ	34	struct amdgpu_cgs_device {
	35	struct cgs_device base;
	36	struct amdgpu_device *adev;
	37	};
	38
	39	#define CGS_FUNC_ADEV \
	40	struct amdgpu_device *adev = \
	41	((struct amdgpu_cgs_device *)cgs_device)->adev
	42
ba89a3ec	43
110e6f26	44	static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
d03846af	45	{
aba684d8 CZ	46	CGS_FUNC_ADEV;
aba684d8 CZ	47	return RREG32(offset);
d03846af CZ	48	}
d03846af CZ	49
110e6f26	50	static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
d03846af CZ	51	uint32_t value)
d03846af CZ	52	{
aba684d8 CZ	53	CGS_FUNC_ADEV;
aba684d8 CZ	54	WREG32(offset, value);
d03846af CZ	55	}
d03846af CZ	56
110e6f26	57	static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
d03846af CZ	58	enum cgs_ind_reg space,
	59	unsigned index)
	60	{
aba684d8 CZ	61	CGS_FUNC_ADEV;
	62	switch (space) {
	63	case CGS_IND_REG__MMIO:
	64	return RREG32_IDX(index);
	65	case CGS_IND_REG__PCIE:
	66	return RREG32_PCIE(index);
	67	case CGS_IND_REG__SMC:
	68	return RREG32_SMC(index);
	69	case CGS_IND_REG__UVD_CTX:
	70	return RREG32_UVD_CTX(index);
	71	case CGS_IND_REG__DIDT:
	72	return RREG32_DIDT(index);
ccdbb20a RZ	73	case CGS_IND_REG_GC_CAC:
ccdbb20a RZ	74	return RREG32_GC_CAC(index);
c62a59d0 EQ	75	case CGS_IND_REG_SE_CAC:
c62a59d0 EQ	76	return RREG32_SE_CAC(index);
aba684d8 CZ	77	case CGS_IND_REG__AUDIO_ENDPT:
	78	DRM_ERROR("audio endpt register access not implemented.\n");
	79	return 0;
	80	}
	81	WARN(1, "Invalid indirect register space");
d03846af CZ	82	return 0;
	83	}
	84
110e6f26	85	static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
d03846af CZ	86	enum cgs_ind_reg space,
	87	unsigned index, uint32_t value)
	88	{
aba684d8 CZ	89	CGS_FUNC_ADEV;
	90	switch (space) {
	91	case CGS_IND_REG__MMIO:
	92	return WREG32_IDX(index, value);
	93	case CGS_IND_REG__PCIE:
	94	return WREG32_PCIE(index, value);
	95	case CGS_IND_REG__SMC:
	96	return WREG32_SMC(index, value);
	97	case CGS_IND_REG__UVD_CTX:
	98	return WREG32_UVD_CTX(index, value);
	99	case CGS_IND_REG__DIDT:
	100	return WREG32_DIDT(index, value);
ccdbb20a RZ	101	case CGS_IND_REG_GC_CAC:
ccdbb20a RZ	102	return WREG32_GC_CAC(index, value);
c62a59d0 EQ	103	case CGS_IND_REG_SE_CAC:
c62a59d0 EQ	104	return WREG32_SE_CAC(index, value);
aba684d8 CZ	105	case CGS_IND_REG__AUDIO_ENDPT:
	106	DRM_ERROR("audio endpt register access not implemented.\n");
	107	return;
	108	}
	109	WARN(1, "Invalid indirect register space");
d03846af CZ	110	}
d03846af CZ	111
110e6f26	112	static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
bf3911b0 JZ	113	{
	114	CGS_FUNC_ADEV;
	115	enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
	116
	117	switch (fw_type) {
	118	case CGS_UCODE_ID_SDMA0:
	119	result = AMDGPU_UCODE_ID_SDMA0;
	120	break;
	121	case CGS_UCODE_ID_SDMA1:
	122	result = AMDGPU_UCODE_ID_SDMA1;
	123	break;
	124	case CGS_UCODE_ID_CP_CE:
	125	result = AMDGPU_UCODE_ID_CP_CE;
	126	break;
	127	case CGS_UCODE_ID_CP_PFP:
	128	result = AMDGPU_UCODE_ID_CP_PFP;
	129	break;
	130	case CGS_UCODE_ID_CP_ME:
	131	result = AMDGPU_UCODE_ID_CP_ME;
	132	break;
	133	case CGS_UCODE_ID_CP_MEC:
	134	case CGS_UCODE_ID_CP_MEC_JT1:
	135	result = AMDGPU_UCODE_ID_CP_MEC1;
	136	break;
	137	case CGS_UCODE_ID_CP_MEC_JT2:
4c2b2453 ML	138	/* for VI. JT2 should be the same as JT1, because:
	139	1, MEC2 and MEC1 use exactly same FW.
	140	2, JT2 is not pached but JT1 is.
	141	*/
	142	if (adev->asic_type >= CHIP_TOPAZ)
bf3911b0	143	result = AMDGPU_UCODE_ID_CP_MEC1;
4c2b2453 ML	144	else
4c2b2453 ML	145	result = AMDGPU_UCODE_ID_CP_MEC2;
bf3911b0 JZ	146	break;
	147	case CGS_UCODE_ID_RLC_G:
	148	result = AMDGPU_UCODE_ID_RLC_G;
	149	break;
bed5712e ML	150	case CGS_UCODE_ID_STORAGE:
	151	result = AMDGPU_UCODE_ID_STORAGE;
	152	break;
bf3911b0 JZ	153	default:
	154	DRM_ERROR("Firmware type not supported\n");
	155	}
	156	return result;
	157	}
	158
fc76cbf4 FM	159	static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
	160	enum cgs_ucode_id type)
	161	{
	162	CGS_FUNC_ADEV;
188a301f	163	uint16_t fw_version = 0;
fc76cbf4 FM	164
	165	switch (type) {
	166	case CGS_UCODE_ID_SDMA0:
	167	fw_version = adev->sdma.instance[0].fw_version;
	168	break;
	169	case CGS_UCODE_ID_SDMA1:
	170	fw_version = adev->sdma.instance[1].fw_version;
	171	break;
	172	case CGS_UCODE_ID_CP_CE:
	173	fw_version = adev->gfx.ce_fw_version;
	174	break;
	175	case CGS_UCODE_ID_CP_PFP:
	176	fw_version = adev->gfx.pfp_fw_version;
	177	break;
	178	case CGS_UCODE_ID_CP_ME:
	179	fw_version = adev->gfx.me_fw_version;
	180	break;
	181	case CGS_UCODE_ID_CP_MEC:
	182	fw_version = adev->gfx.mec_fw_version;
	183	break;
	184	case CGS_UCODE_ID_CP_MEC_JT1:
	185	fw_version = adev->gfx.mec_fw_version;
	186	break;
	187	case CGS_UCODE_ID_CP_MEC_JT2:
	188	fw_version = adev->gfx.mec_fw_version;
	189	break;
	190	case CGS_UCODE_ID_RLC_G:
	191	fw_version = adev->gfx.rlc_fw_version;
	192	break;
188a301f XY	193	case CGS_UCODE_ID_STORAGE:
188a301f XY	194	break;
fc76cbf4 FM	195	default:
fc76cbf4 FM	196	DRM_ERROR("firmware type %d do not have version\n", type);
188a301f	197	break;
fc76cbf4 FM	198	}
	199	return fw_version;
	200	}
	201
110e6f26	202	static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
bf3911b0 JZ	203	enum cgs_ucode_id type,
	204	struct cgs_firmware_info *info)
	205	{
	206	CGS_FUNC_ADEV;
	207
735f002b	208	if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
bf3911b0 JZ	209	uint64_t gpu_addr;
	210	uint32_t data_size;
	211	const struct gfx_firmware_header_v1_0 *header;
	212	enum AMDGPU_UCODE_ID id;
	213	struct amdgpu_firmware_info *ucode;
	214
	215	id = fw_type_convert(cgs_device, type);
	216	ucode = &adev->firmware.ucode[id];
	217	if (ucode->fw == NULL)
	218	return -EINVAL;
	219
	220	gpu_addr = ucode->mc_addr;
	221	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
	222	data_size = le32_to_cpu(header->header.ucode_size_bytes);
	223
	224	if ((type == CGS_UCODE_ID_CP_MEC_JT1) \|\|
	225	(type == CGS_UCODE_ID_CP_MEC_JT2)) {
4c2b2453	226	gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
bf3911b0 JZ	227	data_size = le32_to_cpu(header->jt_size) << 2;
bf3911b0 JZ	228	}
4c2b2453 ML	229
4c2b2453 ML	230	info->kptr = ucode->kaddr;
bf3911b0	231	info->image_size = data_size;
4c2b2453	232	info->mc_addr = gpu_addr;
bf3911b0	233	info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
4c2b2453 ML	234
4c2b2453 ML	235	if (CGS_UCODE_ID_CP_MEC == type)
e68760bf	236	info->image_size = le32_to_cpu(header->jt_offset) << 2;
4c2b2453	237
fc76cbf4	238	info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
bf3911b0 JZ	239	info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
	240	} else {
	241	char fw_name[30] = {0};
	242	int err = 0;
	243	uint32_t ucode_size;
	244	uint32_t ucode_start_address;
	245	const uint8_t *src;
	246	const struct smc_firmware_header_v1_0 *hdr;
d1de1ed3 HR	247	const struct common_firmware_header *header;
d1de1ed3 HR	248	struct amdgpu_firmware_info *ucode = NULL;
bf3911b0	249
0b45541d ML	250	if (!adev->pm.fw) {
0b45541d ML	251	switch (adev->asic_type) {
6df9855f RZ	252	case CHIP_TAHITI:
	253	strcpy(fw_name, "radeon/tahiti_smc.bin");
	254	break;
	255	case CHIP_PITCAIRN:
	256	if ((adev->pdev->revision == 0x81) &&
	257	((adev->pdev->device == 0x6810) \|\|
	258	(adev->pdev->device == 0x6811))) {
	259	info->is_kicker = true;
	260	strcpy(fw_name, "radeon/pitcairn_k_smc.bin");
	261	} else {
	262	strcpy(fw_name, "radeon/pitcairn_smc.bin");
	263	}
	264	break;
	265	case CHIP_VERDE:
	266	if (((adev->pdev->device == 0x6820) &&
	267	((adev->pdev->revision == 0x81) \|\|
	268	(adev->pdev->revision == 0x83))) \|\|
	269	((adev->pdev->device == 0x6821) &&
	270	((adev->pdev->revision == 0x83) \|\|
	271	(adev->pdev->revision == 0x87))) \|\|
	272	((adev->pdev->revision == 0x87) &&
	273	((adev->pdev->device == 0x6823) \|\|
	274	(adev->pdev->device == 0x682b)))) {
	275	info->is_kicker = true;
	276	strcpy(fw_name, "radeon/verde_k_smc.bin");
	277	} else {
	278	strcpy(fw_name, "radeon/verde_smc.bin");
	279	}
	280	break;
	281	case CHIP_OLAND:
	282	if (((adev->pdev->revision == 0x81) &&
	283	((adev->pdev->device == 0x6600) \|\|
	284	(adev->pdev->device == 0x6604) \|\|
	285	(adev->pdev->device == 0x6605) \|\|
	286	(adev->pdev->device == 0x6610))) \|\|
	287	((adev->pdev->revision == 0x83) &&
	288	(adev->pdev->device == 0x6610))) {
	289	info->is_kicker = true;
	290	strcpy(fw_name, "radeon/oland_k_smc.bin");
	291	} else {
	292	strcpy(fw_name, "radeon/oland_smc.bin");
	293	}
	294	break;
	295	case CHIP_HAINAN:
	296	if (((adev->pdev->revision == 0x81) &&
	297	(adev->pdev->device == 0x6660)) \|\|
	298	((adev->pdev->revision == 0x83) &&
	299	((adev->pdev->device == 0x6660) \|\|
	300	(adev->pdev->device == 0x6663) \|\|
	301	(adev->pdev->device == 0x6665) \|\|
	302	(adev->pdev->device == 0x6667)))) {
	303	info->is_kicker = true;
	304	strcpy(fw_name, "radeon/hainan_k_smc.bin");
	305	} else if ((adev->pdev->revision == 0xc3) &&
	306	(adev->pdev->device == 0x6665)) {
	307	info->is_kicker = true;
	308	strcpy(fw_name, "radeon/banks_k_2_smc.bin");
	309	} else {
	310	strcpy(fw_name, "radeon/hainan_smc.bin");
	311	}
	312	break;
	313	case CHIP_BONAIRE:
	314	if ((adev->pdev->revision == 0x80) \|\|
	315	(adev->pdev->revision == 0x81) \|\|
316	(adev->pdev->device == 0x665f)) {
317	info->is_kicker = true;
ce206464	318	strcpy(fw_name, "amdgpu/bonaire_k_smc.bin");
6df9855f	319	} else {
ce206464	320	strcpy(fw_name, "amdgpu/bonaire_smc.bin");
6df9855f RZ	321	}
	322	break;
	323	case CHIP_HAWAII:
	324	if (adev->pdev->revision == 0x80) {
	325	info->is_kicker = true;
ce206464	326	strcpy(fw_name, "amdgpu/hawaii_k_smc.bin");
6df9855f	327	} else {
ce206464	328	strcpy(fw_name, "amdgpu/hawaii_smc.bin");
6df9855f RZ	329	}
6df9855f RZ	330	break;
340efe28	331	case CHIP_TOPAZ:
3b496626 AD	332	if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) \|\|
3b496626 AD	333	((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) \|\|
153573d8 AD	334	((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)) \|\|
	335	((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD1)) \|\|
	336	((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD3))) {
5d7213b0	337	info->is_kicker = true;
3b496626	338	strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
5d7213b0	339	} else
3b496626	340	strcpy(fw_name, "amdgpu/topaz_smc.bin");
340efe28	341	break;
0b45541d	342	case CHIP_TONGA:
646cccb5	343	if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) \|\|
5d7213b0 HR	344	((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
5d7213b0 HR	345	info->is_kicker = true;
646cccb5	346	strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
5d7213b0	347	} else
646cccb5	348	strcpy(fw_name, "amdgpu/tonga_smc.bin");
0b45541d ML	349	break;
	350	case CHIP_FIJI:
	351	strcpy(fw_name, "amdgpu/fiji_smc.bin");
	352	break;
	353	case CHIP_POLARIS11:
a52d120f AD	354	if (type == CGS_UCODE_ID_SMU) {
	355	if (((adev->pdev->device == 0x67ef) &&
	356	((adev->pdev->revision == 0xe0) \|\|
a52d120f AD	357	(adev->pdev->revision == 0xe5))) \|\|
	358	((adev->pdev->device == 0x67ff) &&
	359	((adev->pdev->revision == 0xcf) \|\|
	360	(adev->pdev->revision == 0xef) \|\|
5d7213b0 HR	361	(adev->pdev->revision == 0xff)))) {
5d7213b0 HR	362	info->is_kicker = true;
a52d120f	363	strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
153573d8 AD	364	} else if ((adev->pdev->device == 0x67ef) &&
	365	(adev->pdev->revision == 0xe2)) {
	366	info->is_kicker = true;
	367	strcpy(fw_name, "amdgpu/polaris11_k2_smc.bin");
	368	} else {
a52d120f	369	strcpy(fw_name, "amdgpu/polaris11_smc.bin");
153573d8	370	}
a52d120f	371	} else if (type == CGS_UCODE_ID_SMU_SK) {
0b45541d	372	strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
a52d120f	373	}
0b45541d ML	374	break;
0b45541d ML	375	case CHIP_POLARIS10:
a52d120f	376	if (type == CGS_UCODE_ID_SMU) {
30f3984e AD	377	if (((adev->pdev->device == 0x67df) &&
	378	((adev->pdev->revision == 0xe0) \|\|
	379	(adev->pdev->revision == 0xe3) \|\|
	380	(adev->pdev->revision == 0xe4) \|\|
	381	(adev->pdev->revision == 0xe5) \|\|
	382	(adev->pdev->revision == 0xe7) \|\|
	383	(adev->pdev->revision == 0xef))) \|\|
	384	((adev->pdev->device == 0x6fdf) &&
d55d8be0 JZ	385	((adev->pdev->revision == 0xef) \|\|
d55d8be0 JZ	386	(adev->pdev->revision == 0xff)))) {
5d7213b0	387	info->is_kicker = true;
a52d120f	388	strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
153573d8 AD	389	} else if ((adev->pdev->device == 0x67df) &&
	390	((adev->pdev->revision == 0xe1) \|\|
	391	(adev->pdev->revision == 0xf7))) {
	392	info->is_kicker = true;
	393	strcpy(fw_name, "amdgpu/polaris10_k2_smc.bin");
	394	} else {
a52d120f	395	strcpy(fw_name, "amdgpu/polaris10_smc.bin");
153573d8	396	}
a52d120f	397	} else if (type == CGS_UCODE_ID_SMU_SK) {
0b45541d	398	strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
a52d120f	399	}
0b45541d	400	break;
c4642a47	401	case CHIP_POLARIS12:
153573d8 AD	402	if (((adev->pdev->device == 0x6987) &&
	403	((adev->pdev->revision == 0xc0) \|\|
	404	(adev->pdev->revision == 0xc3))) \|\|
	405	((adev->pdev->device == 0x6981) &&
	406	((adev->pdev->revision == 0x00) \|\|
	407	(adev->pdev->revision == 0x01) \|\|
	408	(adev->pdev->revision == 0x10)))) {
	409	info->is_kicker = true;
	410	strcpy(fw_name, "amdgpu/polaris12_k_smc.bin");
	411	} else {
	412	strcpy(fw_name, "amdgpu/polaris12_smc.bin");
	413	}
c4642a47	414	break;
5830bb98 LL	415	case CHIP_VEGAM:
	416	strcpy(fw_name, "amdgpu/vegam_smc.bin");
	417	break;
220ab9bd	418	case CHIP_VEGA10:
747f6c92 EQ	419	if ((adev->pdev->device == 0x687f) &&
	420	((adev->pdev->revision == 0xc0) \|\|
	421	(adev->pdev->revision == 0xc1) \|\|
	422	(adev->pdev->revision == 0xc3)))
	423	strcpy(fw_name, "amdgpu/vega10_acg_smc.bin");
	424	else
	425	strcpy(fw_name, "amdgpu/vega10_smc.bin");
220ab9bd	426	break;
ad0ad9aa HZ	427	case CHIP_VEGA12:
	428	strcpy(fw_name, "amdgpu/vega12_smc.bin");
	429	break;
a167ae25 FX	430	case CHIP_VEGA20:
	431	strcpy(fw_name, "amdgpu/vega20_smc.bin");
	432	break;
0b45541d ML	433	default:
	434	DRM_ERROR("SMC firmware not supported\n");
	435	return -EINVAL;
	436	}
	437
	438	err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
	439	if (err) {
	440	DRM_ERROR("Failed to request firmware\n");
	441	return err;
	442	}
	443
	444	err = amdgpu_ucode_validate(adev->pm.fw);
	445	if (err) {
	446	DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
	447	release_firmware(adev->pm.fw);
	448	adev->pm.fw = NULL;
	449	return err;
	450	}
d1de1ed3 HR	451
	452	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
	453	ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
	454	ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
	455	ucode->fw = adev->pm.fw;
	456	header = (const struct common_firmware_header *)ucode->fw->data;
	457	adev->firmware.fw_size +=
	458	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
	459	}
bf3911b0 JZ	460	}
	461
	462	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
c66875b1	463	amdgpu_ucode_print_smc_hdr(&hdr->header);
bf3911b0 JZ	464	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
	465	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
	466	ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
	467	src = (const uint8_t *)(adev->pm.fw->data +
	468	le32_to_cpu(hdr->header.ucode_array_offset_bytes));
	469
	470	info->version = adev->pm.fw_version;
	471	info->image_size = ucode_size;
340efe28	472	info->ucode_start_address = ucode_start_address;
bf3911b0 JZ	473	info->kptr = (void *)src;
	474	}
	475	return 0;
	476	}
	477
d03846af	478	static const struct cgs_ops amdgpu_cgs_ops = {
613e61a0 KC	479	.read_register = amdgpu_cgs_read_register,
	480	.write_register = amdgpu_cgs_write_register,
	481	.read_ind_register = amdgpu_cgs_read_ind_register,
	482	.write_ind_register = amdgpu_cgs_write_ind_register,
613e61a0	483	.get_firmware_info = amdgpu_cgs_get_firmware_info,
d03846af CZ	484	};
d03846af CZ	485
110e6f26	486	struct cgs_device amdgpu_cgs_create_device(struct amdgpu_device adev)
d03846af CZ	487	{
	488	struct amdgpu_cgs_device *cgs_device =
	489	kmalloc(sizeof(*cgs_device), GFP_KERNEL);
	490
	491	if (!cgs_device) {
	492	DRM_ERROR("Couldn't allocate CGS device structure\n");
	493	return NULL;
	494	}
	495
	496	cgs_device->base.ops = &amdgpu_cgs_ops;
d03846af CZ	497	cgs_device->adev = adev;
d03846af CZ	498
110e6f26	499	return (struct cgs_device *)cgs_device;
d03846af CZ	500	}
d03846af CZ	501
110e6f26	502	void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
d03846af CZ	503	{
	504	kfree(cgs_device);
	505	}