]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: add AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag v3
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cgs.c
CommitLineData
d03846af
CZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
57ff96cf
CZ		 24#include <linux/list.h>
25#include <linux/slab.h>
97cb7f6e 26#include <linux/pci.h>
3f1d35a0 27#include <linux/acpi.h>
57ff96cf 28#include <drm/drmP.h>
bf3911b0 29#include <linux/firmware.h>
57ff96cf 30#include <drm/amdgpu_drm.h>
d03846af
CZ		 31#include "amdgpu.h"
32#include "cgs_linux.h"
25da4427 33#include "atom.h"
bf3911b0
JZ		 34#include "amdgpu_ucode.h"
35
d03846af
CZ		 36struct amdgpu_cgs_device {
37 struct cgs_device base;
38 struct amdgpu_device *adev;
39};
40
41#define CGS_FUNC_ADEV \
42 struct amdgpu_device *adev = \
43 ((struct amdgpu_cgs_device *)cgs_device)->adev
44
110e6f26 45static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
d03846af
CZ		 46 uint64_t *mc_start, uint64_t *mc_size,
47 uint64_t *mem_size)
48{
57ff96cf
CZ		 49 CGS_FUNC_ADEV;
50 switch(type) {
51 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
52 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
53 *mc_start = 0;
54 *mc_size = adev->mc.visible_vram_size;
55 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
56 break;
57 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
58 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
59 *mc_start = adev->mc.visible_vram_size;
60 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
61 *mem_size = *mc_size;
62 break;
63 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
64 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
65 *mc_start = adev->mc.gtt_start;
66 *mc_size = adev->mc.gtt_size;
67 *mem_size = adev->mc.gtt_size - adev->gart_pin_size;
68 break;
69 default:
70 return -EINVAL;
71 }
72
d03846af
CZ		 73 return 0;
74}
75
110e6f26 76static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem,
d03846af
CZ		 77 uint64_t size,
78 uint64_t min_offset, uint64_t max_offset,
79 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
80{
57ff96cf
CZ		 81 CGS_FUNC_ADEV;
82 int ret;
83 struct amdgpu_bo *bo;
84 struct page *kmem_page = vmalloc_to_page(kmem);
85 int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
86
87 struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
88 ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
72d7668b 89 AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo);
57ff96cf
CZ		 90 if (ret)
91 return ret;
92 ret = amdgpu_bo_reserve(bo, false);
93 if (unlikely(ret != 0))
94 return ret;
95
96 /* pin buffer into GTT */
97 ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
98 min_offset, max_offset, mcaddr);
99 amdgpu_bo_unreserve(bo);
100
101 *kmem_handle = (cgs_handle_t)bo;
102 return ret;
d03846af
CZ		 103}
104
110e6f26 105static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle)
d03846af 106{
57ff96cf
CZ		 107 struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
108
109 if (obj) {
110 int r = amdgpu_bo_reserve(obj, false);
111 if (likely(r == 0)) {
112 amdgpu_bo_unpin(obj);
113 amdgpu_bo_unreserve(obj);
114 }
115 amdgpu_bo_unref(&obj);
116
117 }
d03846af
CZ		 118 return 0;
119}
120
110e6f26 121static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
d03846af
CZ		 122 enum cgs_gpu_mem_type type,
123 uint64_t size, uint64_t align,
124 uint64_t min_offset, uint64_t max_offset,
125 cgs_handle_t *handle)
126{
57ff96cf
CZ		 127 CGS_FUNC_ADEV;
128 uint16_t flags = 0;
129 int ret = 0;
130 uint32_t domain = 0;
131 struct amdgpu_bo *obj;
132 struct ttm_placement placement;
133 struct ttm_place place;
134
135 if (min_offset > max_offset) {
136 BUG_ON(1);
137 return -EINVAL;
138 }
139
140 /* fail if the alignment is not a power of 2 */
141 if (((align != 1) && (align & (align - 1)))
142 || size == 0 || align == 0)
143 return -EINVAL;
144
145
146 switch(type) {
147 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
148 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
03f48dd5
CK		 149 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
150 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
57ff96cf
CZ		 151 domain = AMDGPU_GEM_DOMAIN_VRAM;
152 if (max_offset > adev->mc.real_vram_size)
153 return -EINVAL;
154 place.fpfn = min_offset >> PAGE_SHIFT;
155 place.lpfn = max_offset >> PAGE_SHIFT;
156 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
157 TTM_PL_FLAG_VRAM;
158 break;
159 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
160 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
03f48dd5
CK		 161 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
162 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
57ff96cf
CZ		 163 domain = AMDGPU_GEM_DOMAIN_VRAM;
164 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
165 place.fpfn =
166 max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT;
167 place.lpfn =
168 min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT;
169 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
170 TTM_PL_FLAG_VRAM;
171 }
172
173 break;
174 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
175 domain = AMDGPU_GEM_DOMAIN_GTT;
176 place.fpfn = min_offset >> PAGE_SHIFT;
177 place.lpfn = max_offset >> PAGE_SHIFT;
178 place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
179 break;
180 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
181 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
182 domain = AMDGPU_GEM_DOMAIN_GTT;
183 place.fpfn = min_offset >> PAGE_SHIFT;
184 place.lpfn = max_offset >> PAGE_SHIFT;
185 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
186 TTM_PL_FLAG_UNCACHED;
187 break;
188 default:
189 return -EINVAL;
190 }
191
192
193 *handle = 0;
194
195 placement.placement = &place;
196 placement.num_placement = 1;
197 placement.busy_placement = &place;
198 placement.num_busy_placement = 1;
199
200 ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
201 true, domain, flags,
72d7668b
CK		 202 NULL, &placement, NULL,
203 &obj);
57ff96cf
CZ		 204 if (ret) {
205 DRM_ERROR("(%d) bo create failed\n", ret);
206 return ret;
207 }
208 *handle = (cgs_handle_t)obj;
209
210 return ret;
d03846af
CZ		 211}
212
110e6f26 213static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
d03846af 214{
57ff96cf
CZ		 215 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
216
217 if (obj) {
218 int r = amdgpu_bo_reserve(obj, false);
219 if (likely(r == 0)) {
220 amdgpu_bo_kunmap(obj);
221 amdgpu_bo_unpin(obj);
222 amdgpu_bo_unreserve(obj);
223 }
224 amdgpu_bo_unref(&obj);
225
226 }
d03846af
CZ		 227 return 0;
228}
229
110e6f26 230static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
d03846af
CZ		 231 uint64_t *mcaddr)
232{
57ff96cf
CZ		 233 int r;
234 u64 min_offset, max_offset;
235 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
236
237 WARN_ON_ONCE(obj->placement.num_placement > 1);
238
239 min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
240 max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
241
242 r = amdgpu_bo_reserve(obj, false);
243 if (unlikely(r != 0))
244 return r;
245 r = amdgpu_bo_pin_restricted(obj, AMDGPU_GEM_DOMAIN_GTT,
246 min_offset, max_offset, mcaddr);
247 amdgpu_bo_unreserve(obj);
248 return r;
d03846af
CZ		 249}
250
110e6f26 251static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
d03846af 252{
57ff96cf
CZ		 253 int r;
254 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
255 r = amdgpu_bo_reserve(obj, false);
256 if (unlikely(r != 0))
257 return r;
258 r = amdgpu_bo_unpin(obj);
259 amdgpu_bo_unreserve(obj);
260 return r;
d03846af
CZ		 261}
262
110e6f26 263static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
d03846af
CZ		 264 void **map)
265{
57ff96cf
CZ		 266 int r;
267 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
268 r = amdgpu_bo_reserve(obj, false);
269 if (unlikely(r != 0))
270 return r;
271 r = amdgpu_bo_kmap(obj, map);
272 amdgpu_bo_unreserve(obj);
273 return r;
d03846af
CZ		 274}
275
110e6f26 276static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
d03846af 277{
57ff96cf
CZ		 278 int r;
279 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
280 r = amdgpu_bo_reserve(obj, false);
281 if (unlikely(r != 0))
282 return r;
283 amdgpu_bo_kunmap(obj);
284 amdgpu_bo_unreserve(obj);
285 return r;
d03846af
CZ		 286}
287
110e6f26 288static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
d03846af 289{
aba684d8
CZ		 290 CGS_FUNC_ADEV;
291 return RREG32(offset);
d03846af
CZ		 292}
293
110e6f26 294static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
d03846af
CZ		 295 uint32_t value)
296{
aba684d8
CZ		 297 CGS_FUNC_ADEV;
298 WREG32(offset, value);
d03846af
CZ		 299}
300
110e6f26 301static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
d03846af
CZ		 302 enum cgs_ind_reg space,
303 unsigned index)
304{
aba684d8
CZ		 305 CGS_FUNC_ADEV;
306 switch (space) {
307 case CGS_IND_REG__MMIO:
308 return RREG32_IDX(index);
309 case CGS_IND_REG__PCIE:
310 return RREG32_PCIE(index);
311 case CGS_IND_REG__SMC:
312 return RREG32_SMC(index);
313 case CGS_IND_REG__UVD_CTX:
314 return RREG32_UVD_CTX(index);
315 case CGS_IND_REG__DIDT:
316 return RREG32_DIDT(index);
ccdbb20a
RZ		 317 case CGS_IND_REG_GC_CAC:
318 return RREG32_GC_CAC(index);
aba684d8
CZ		 319 case CGS_IND_REG__AUDIO_ENDPT:
320 DRM_ERROR("audio endpt register access not implemented.\n");
321 return 0;
322 }
323 WARN(1, "Invalid indirect register space");
d03846af
CZ		 324 return 0;
325}
326
110e6f26 327static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
d03846af
CZ		 328 enum cgs_ind_reg space,
329 unsigned index, uint32_t value)
330{
aba684d8
CZ		 331 CGS_FUNC_ADEV;
332 switch (space) {
333 case CGS_IND_REG__MMIO:
334 return WREG32_IDX(index, value);
335 case CGS_IND_REG__PCIE:
336 return WREG32_PCIE(index, value);
337 case CGS_IND_REG__SMC:
338 return WREG32_SMC(index, value);
339 case CGS_IND_REG__UVD_CTX:
340 return WREG32_UVD_CTX(index, value);
341 case CGS_IND_REG__DIDT:
342 return WREG32_DIDT(index, value);
ccdbb20a
RZ		 343 case CGS_IND_REG_GC_CAC:
344 return WREG32_GC_CAC(index, value);
aba684d8
CZ		 345 case CGS_IND_REG__AUDIO_ENDPT:
346 DRM_ERROR("audio endpt register access not implemented.\n");
347 return;
348 }
349 WARN(1, "Invalid indirect register space");
d03846af
CZ		 350}
351
110e6f26 352static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr)
d03846af 353{
97cb7f6e
CZ		 354 CGS_FUNC_ADEV;
355 uint8_t val;
356 int ret = pci_read_config_byte(adev->pdev, addr, &val);
357 if (WARN(ret, "pci_read_config_byte error"))
358 return 0;
359 return val;
d03846af
CZ		 360}
361
110e6f26 362static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr)
d03846af 363{
97cb7f6e
CZ		 364 CGS_FUNC_ADEV;
365 uint16_t val;
366 int ret = pci_read_config_word(adev->pdev, addr, &val);
367 if (WARN(ret, "pci_read_config_word error"))
368 return 0;
369 return val;
d03846af
CZ		 370}
371
110e6f26 372static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device,
d03846af
CZ		 373 unsigned addr)
374{
97cb7f6e
CZ		 375 CGS_FUNC_ADEV;
376 uint32_t val;
377 int ret = pci_read_config_dword(adev->pdev, addr, &val);
378 if (WARN(ret, "pci_read_config_dword error"))
379 return 0;
380 return val;
d03846af
CZ		 381}
382
110e6f26 383static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr,
d03846af
CZ		 384 uint8_t value)
385{
97cb7f6e
CZ		 386 CGS_FUNC_ADEV;
387 int ret = pci_write_config_byte(adev->pdev, addr, value);
388 WARN(ret, "pci_write_config_byte error");
d03846af
CZ		 389}
390
110e6f26 391static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr,
d03846af
CZ		 392 uint16_t value)
393{
97cb7f6e
CZ		 394 CGS_FUNC_ADEV;
395 int ret = pci_write_config_word(adev->pdev, addr, value);
396 WARN(ret, "pci_write_config_word error");
d03846af
CZ		 397}
398
110e6f26 399static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr,
d03846af
CZ		 400 uint32_t value)
401{
97cb7f6e
CZ		 402 CGS_FUNC_ADEV;
403 int ret = pci_write_config_dword(adev->pdev, addr, value);
404 WARN(ret, "pci_write_config_dword error");
d03846af
CZ		 405}
406
ba228ac8 407
110e6f26 408static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
ba228ac8
AD		 409 enum cgs_resource_type resource_type,
410 uint64_t size,
411 uint64_t offset,
412 uint64_t *resource_base)
413{
414 CGS_FUNC_ADEV;
415
416 if (resource_base == NULL)
417 return -EINVAL;
418
419 switch (resource_type) {
420 case CGS_RESOURCE_TYPE_MMIO:
421 if (adev->rmmio_size == 0)
422 return -ENOENT;
423 if ((offset + size) > adev->rmmio_size)
424 return -EINVAL;
425 *resource_base = adev->rmmio_base;
426 return 0;
427 case CGS_RESOURCE_TYPE_DOORBELL:
428 if (adev->doorbell.size == 0)
429 return -ENOENT;
430 if ((offset + size) > adev->doorbell.size)
431 return -EINVAL;
432 *resource_base = adev->doorbell.base;
433 return 0;
434 case CGS_RESOURCE_TYPE_FB:
435 case CGS_RESOURCE_TYPE_IO:
436 case CGS_RESOURCE_TYPE_ROM:
437 default:
438 return -EINVAL;
439 }
440}
441
110e6f26 442static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
d03846af
CZ		 443 unsigned table, uint16_t *size,
444 uint8_t *frev, uint8_t *crev)
445{
25da4427
CZ		 446 CGS_FUNC_ADEV;
447 uint16_t data_start;
448
449 if (amdgpu_atom_parse_data_header(
450 adev->mode_info.atom_context, table, size,
451 frev, crev, &data_start))
452 return (uint8_t*)adev->mode_info.atom_context->bios +
453 data_start;
454
d03846af
CZ		 455 return NULL;
456}
457
110e6f26 458static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
d03846af
CZ		 459 uint8_t *frev, uint8_t *crev)
460{
25da4427
CZ		 461 CGS_FUNC_ADEV;
462
463 if (amdgpu_atom_parse_cmd_header(
464 adev->mode_info.atom_context, table,
465 frev, crev))
466 return 0;
467
468 return -EINVAL;
d03846af
CZ		 469}
470
110e6f26 471static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
d03846af
CZ		 472 void *args)
473{
25da4427 474 CGS_FUNC_ADEV;
d03846af 475
25da4427
CZ		 476 return amdgpu_atom_execute_table(
477 adev->mode_info.atom_context, table, args);
478}
d03846af 479
110e6f26 480static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request)
d03846af
CZ		 481{
482 /* TODO */
483 return 0;
484}
485
110e6f26 486static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request)
d03846af
CZ		 487{
488 /* TODO */
489 return 0;
490}
491
110e6f26 492static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request,
d03846af
CZ		 493 int active)
494{
495 /* TODO */
496 return 0;
497}
498
110e6f26 499static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request,
d03846af
CZ		 500 enum cgs_clock clock, unsigned freq)
501{
502 /* TODO */
503 return 0;
504}
505
110e6f26 506static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request,
d03846af
CZ		 507 enum cgs_engine engine, int powered)
508{
509 /* TODO */
510 return 0;
511}
512
513
514
110e6f26 515static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device,
d03846af
CZ		 516 enum cgs_clock clock,
517 struct cgs_clock_limits *limits)
518{
519 /* TODO */
520 return 0;
521}
522
110e6f26 523static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask,
d03846af
CZ		 524 const uint32_t *voltages)
525{
526 DRM_ERROR("not implemented");
527 return -EPERM;
528}
529
0cf3be21
AD		 530struct cgs_irq_params {
531 unsigned src_id;
532 cgs_irq_source_set_func_t set;
533 cgs_irq_handler_func_t handler;
534 void *private_data;
535};
536
537static int cgs_set_irq_state(struct amdgpu_device *adev,
538 struct amdgpu_irq_src *src,
539 unsigned type,
540 enum amdgpu_interrupt_state state)
541{
542 struct cgs_irq_params *irq_params =
543 (struct cgs_irq_params *)src->data;
544 if (!irq_params)
545 return -EINVAL;
546 if (!irq_params->set)
547 return -EINVAL;
548 return irq_params->set(irq_params->private_data,
549 irq_params->src_id,
550 type,
551 (int)state);
552}
553
554static int cgs_process_irq(struct amdgpu_device *adev,
555 struct amdgpu_irq_src *source,
556 struct amdgpu_iv_entry *entry)
557{
558 struct cgs_irq_params *irq_params =
559 (struct cgs_irq_params *)source->data;
560 if (!irq_params)
561 return -EINVAL;
562 if (!irq_params->handler)
563 return -EINVAL;
564 return irq_params->handler(irq_params->private_data,
565 irq_params->src_id,
566 entry->iv_entry);
567}
568
569static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
570 .set = cgs_set_irq_state,
571 .process = cgs_process_irq,
572};
573
110e6f26 574static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id,
d03846af
CZ		 575 unsigned num_types,
576 cgs_irq_source_set_func_t set,
577 cgs_irq_handler_func_t handler,
578 void *private_data)
579{
0cf3be21
AD		 580 CGS_FUNC_ADEV;
581 int ret = 0;
582 struct cgs_irq_params *irq_params;
583 struct amdgpu_irq_src *source =
584 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
585 if (!source)
586 return -ENOMEM;
587 irq_params =
588 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
589 if (!irq_params) {
590 kfree(source);
591 return -ENOMEM;
592 }
593 source->num_types = num_types;
594 source->funcs = &cgs_irq_funcs;
595 irq_params->src_id = src_id;
596 irq_params->set = set;
597 irq_params->handler = handler;
598 irq_params->private_data = private_data;
599 source->data = (void *)irq_params;
600 ret = amdgpu_irq_add_id(adev, src_id, source);
601 if (ret) {
602 kfree(irq_params);
603 kfree(source);
604 }
605
606 return ret;
d03846af
CZ		 607}
608
110e6f26 609static int amdgpu_cgs_irq_get(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
d03846af 610{
0cf3be21
AD		 611 CGS_FUNC_ADEV;
612 return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
d03846af
CZ		 613}
614
110e6f26 615static int amdgpu_cgs_irq_put(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
d03846af 616{
0cf3be21
AD		 617 CGS_FUNC_ADEV;
618 return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
d03846af
CZ		 619}
620
761c2e82 621static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
404b2fa3 622 enum amd_ip_block_type block_type,
623 enum amd_clockgating_state state)
624{
625 CGS_FUNC_ADEV;
626 int i, r = -1;
627
628 for (i = 0; i < adev->num_ip_blocks; i++) {
629 if (!adev->ip_block_status[i].valid)
630 continue;
631
632 if (adev->ip_blocks[i].type == block_type) {
633 r = adev->ip_blocks[i].funcs->set_clockgating_state(
634 (void *)adev,
635 state);
636 break;
637 }
638 }
639 return r;
640}
641
761c2e82 642static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
404b2fa3 643 enum amd_ip_block_type block_type,
644 enum amd_powergating_state state)
645{
646 CGS_FUNC_ADEV;
647 int i, r = -1;
648
649 for (i = 0; i < adev->num_ip_blocks; i++) {
650 if (!adev->ip_block_status[i].valid)
651 continue;
652
653 if (adev->ip_blocks[i].type == block_type) {
654 r = adev->ip_blocks[i].funcs->set_powergating_state(
655 (void *)adev,
656 state);
657 break;
658 }
659 }
660 return r;
661}
662
663
110e6f26 664static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
bf3911b0
JZ		 665{
666 CGS_FUNC_ADEV;
667 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
668
669 switch (fw_type) {
670 case CGS_UCODE_ID_SDMA0:
671 result = AMDGPU_UCODE_ID_SDMA0;
672 break;
673 case CGS_UCODE_ID_SDMA1:
674 result = AMDGPU_UCODE_ID_SDMA1;
675 break;
676 case CGS_UCODE_ID_CP_CE:
677 result = AMDGPU_UCODE_ID_CP_CE;
678 break;
679 case CGS_UCODE_ID_CP_PFP:
680 result = AMDGPU_UCODE_ID_CP_PFP;
681 break;
682 case CGS_UCODE_ID_CP_ME:
683 result = AMDGPU_UCODE_ID_CP_ME;
684 break;
685 case CGS_UCODE_ID_CP_MEC:
686 case CGS_UCODE_ID_CP_MEC_JT1:
687 result = AMDGPU_UCODE_ID_CP_MEC1;
688 break;
689 case CGS_UCODE_ID_CP_MEC_JT2:
2cc0c0b5
FC		 690 if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11
691 || adev->asic_type == CHIP_POLARIS10)
bf3911b0 692 result = AMDGPU_UCODE_ID_CP_MEC2;
c8172625 693 else
bf3911b0
JZ		 694 result = AMDGPU_UCODE_ID_CP_MEC1;
695 break;
696 case CGS_UCODE_ID_RLC_G:
697 result = AMDGPU_UCODE_ID_RLC_G;
698 break;
699 default:
700 DRM_ERROR("Firmware type not supported\n");
701 }
702 return result;
703}
704
a392746a
ML		 705static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
706{
707 CGS_FUNC_ADEV;
708 if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
709 release_firmware(adev->pm.fw);
710 return 0;
711 }
712 /* cannot release other firmware because they are not created by cgs */
713 return -EINVAL;
714}
715
fc76cbf4
FM		 716static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
717 enum cgs_ucode_id type)
718{
719 CGS_FUNC_ADEV;
720 uint16_t fw_version;
721
722 switch (type) {
723 case CGS_UCODE_ID_SDMA0:
724 fw_version = adev->sdma.instance[0].fw_version;
725 break;
726 case CGS_UCODE_ID_SDMA1:
727 fw_version = adev->sdma.instance[1].fw_version;
728 break;
729 case CGS_UCODE_ID_CP_CE:
730 fw_version = adev->gfx.ce_fw_version;
731 break;
732 case CGS_UCODE_ID_CP_PFP:
733 fw_version = adev->gfx.pfp_fw_version;
734 break;
735 case CGS_UCODE_ID_CP_ME:
736 fw_version = adev->gfx.me_fw_version;
737 break;
738 case CGS_UCODE_ID_CP_MEC:
739 fw_version = adev->gfx.mec_fw_version;
740 break;
741 case CGS_UCODE_ID_CP_MEC_JT1:
742 fw_version = adev->gfx.mec_fw_version;
743 break;
744 case CGS_UCODE_ID_CP_MEC_JT2:
745 fw_version = adev->gfx.mec_fw_version;
746 break;
747 case CGS_UCODE_ID_RLC_G:
748 fw_version = adev->gfx.rlc_fw_version;
749 break;
750 default:
751 DRM_ERROR("firmware type %d do not have version\n", type);
752 fw_version = 0;
753 }
754 return fw_version;
755}
756
110e6f26 757static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
bf3911b0
JZ		 758 enum cgs_ucode_id type,
759 struct cgs_firmware_info *info)
760{
761 CGS_FUNC_ADEV;
762
735f002b 763 if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
bf3911b0
JZ		 764 uint64_t gpu_addr;
765 uint32_t data_size;
766 const struct gfx_firmware_header_v1_0 *header;
767 enum AMDGPU_UCODE_ID id;
768 struct amdgpu_firmware_info *ucode;
769
770 id = fw_type_convert(cgs_device, type);
771 ucode = &adev->firmware.ucode[id];
772 if (ucode->fw == NULL)
773 return -EINVAL;
774
775 gpu_addr = ucode->mc_addr;
776 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
777 data_size = le32_to_cpu(header->header.ucode_size_bytes);
778
779 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
780 (type == CGS_UCODE_ID_CP_MEC_JT2)) {
781 gpu_addr += le32_to_cpu(header->jt_offset) << 2;
782 data_size = le32_to_cpu(header->jt_size) << 2;
783 }
784 info->mc_addr = gpu_addr;
785 info->image_size = data_size;
786 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
fc76cbf4 787 info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
bf3911b0
JZ		 788 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
789 } else {
790 char fw_name[30] = {0};
791 int err = 0;
792 uint32_t ucode_size;
793 uint32_t ucode_start_address;
794 const uint8_t *src;
795 const struct smc_firmware_header_v1_0 *hdr;
796
0b45541d
ML		 797 if (!adev->pm.fw) {
798 switch (adev->asic_type) {
340efe28
HR		 799 case CHIP_TOPAZ:
800 strcpy(fw_name, "amdgpu/topaz_smc.bin");
801 break;
0b45541d
ML		 802 case CHIP_TONGA:
803 strcpy(fw_name, "amdgpu/tonga_smc.bin");
804 break;
805 case CHIP_FIJI:
806 strcpy(fw_name, "amdgpu/fiji_smc.bin");
807 break;
808 case CHIP_POLARIS11:
809 if (type == CGS_UCODE_ID_SMU)
810 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
811 else if (type == CGS_UCODE_ID_SMU_SK)
812 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
813 break;
814 case CHIP_POLARIS10:
815 if (type == CGS_UCODE_ID_SMU)
816 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
817 else if (type == CGS_UCODE_ID_SMU_SK)
818 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
819 break;
820 default:
821 DRM_ERROR("SMC firmware not supported\n");
822 return -EINVAL;
823 }
824
825 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
826 if (err) {
827 DRM_ERROR("Failed to request firmware\n");
828 return err;
829 }
830
831 err = amdgpu_ucode_validate(adev->pm.fw);
832 if (err) {
833 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
834 release_firmware(adev->pm.fw);
835 adev->pm.fw = NULL;
836 return err;
837 }
bf3911b0
JZ		 838 }
839
840 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
c66875b1 841 amdgpu_ucode_print_smc_hdr(&hdr->header);
bf3911b0
JZ		 842 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
843 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
844 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
845 src = (const uint8_t *)(adev->pm.fw->data +
846 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
847
848 info->version = adev->pm.fw_version;
849 info->image_size = ucode_size;
340efe28 850 info->ucode_start_address = ucode_start_address;
bf3911b0
JZ		 851 info->kptr = (void *)src;
852 }
853 return 0;
854}
855
110e6f26 856static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
09fc7eff 857 struct cgs_system_info *sys_info)
5e618699
RZ		 858{
859 CGS_FUNC_ADEV;
860
861 if (NULL == sys_info)
862 return -ENODEV;
863
864 if (sizeof(struct cgs_system_info) != sys_info->size)
865 return -ENODEV;
866
867 switch (sys_info->info_id) {
868 case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
869 sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
870 break;
cfd316d5
AD		 871 case CGS_SYSTEM_INFO_PCIE_GEN_INFO:
872 sys_info->value = adev->pm.pcie_gen_mask;
873 break;
874 case CGS_SYSTEM_INFO_PCIE_MLW:
875 sys_info->value = adev->pm.pcie_mlw_mask;
876 break;
09fc7eff
HR		 877 case CGS_SYSTEM_INFO_PCIE_DEV:
878 sys_info->value = adev->pdev->device;
879 break;
880 case CGS_SYSTEM_INFO_PCIE_REV:
881 sys_info->value = adev->pdev->revision;
882 break;
08d33408
AD		 883 case CGS_SYSTEM_INFO_CG_FLAGS:
884 sys_info->value = adev->cg_flags;
885 break;
886 case CGS_SYSTEM_INFO_PG_FLAGS:
887 sys_info->value = adev->pg_flags;
888 break;
bacec898 889 case CGS_SYSTEM_INFO_GFX_CU_INFO:
7dae69a2 890 sys_info->value = adev->gfx.cu_info.number;
bacec898 891 break;
d826c982
RZ		 892 case CGS_SYSTEM_INFO_GFX_SE_INFO:
893 sys_info->value = adev->gfx.config.max_shader_engines;
894 break;
2fef37c6
RZ		 895 case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID:
896 sys_info->value = adev->pdev->subsystem_device;
897 break;
898 case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:
899 sys_info->value = adev->pdev->subsystem_vendor;
900 break;
5e618699
RZ		 901 default:
902 return -ENODEV;
903 }
904
905 return 0;
906}
907
110e6f26 908static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
47bf18b5
RZ		 909 struct cgs_display_info *info)
910{
911 CGS_FUNC_ADEV;
912 struct amdgpu_crtc *amdgpu_crtc;
913 struct drm_device *ddev = adev->ddev;
914 struct drm_crtc *crtc;
915 uint32_t line_time_us, vblank_lines;
f9e9c08e 916 struct cgs_mode_info *mode_info;
47bf18b5
RZ		 917
918 if (info == NULL)
919 return -EINVAL;
920
f9e9c08e
RZ		 921 mode_info = info->mode_info;
922
47bf18b5
RZ		 923 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
924 list_for_each_entry(crtc,
925 &ddev->mode_config.crtc_list, head) {
926 amdgpu_crtc = to_amdgpu_crtc(crtc);
927 if (crtc->enabled) {
928 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
929 info->display_count++;
930 }
f9e9c08e 931 if (mode_info != NULL &&
47bf18b5
RZ		 932 crtc->enabled && amdgpu_crtc->enabled &&
933 amdgpu_crtc->hw_mode.clock) {
934 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
935 amdgpu_crtc->hw_mode.clock;
936 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
937 amdgpu_crtc->hw_mode.crtc_vdisplay +
938 (amdgpu_crtc->v_border * 2);
f9e9c08e
RZ		 939 mode_info->vblank_time_us = vblank_lines * line_time_us;
940 mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
941 mode_info->ref_clock = adev->clock.spll.reference_freq;
942 mode_info = NULL;
47bf18b5
RZ		 943 }
944 }
945 }
946
947 return 0;
948}
949
4c90080b 950
110e6f26 951static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
4c90080b
RZ		 952{
953 CGS_FUNC_ADEV;
954
955 adev->pm.dpm_enabled = enabled;
956
957 return 0;
958}
959
3f1d35a0
RZ		 960/** \brief evaluate acpi namespace object, handle or pathname must be valid
961 * \param cgs_device
962 * \param info input/output arguments for the control method
963 * \return status
964 */
965
966#if defined(CONFIG_ACPI)
110e6f26 967static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
3f1d35a0
RZ		 968 struct cgs_acpi_method_info *info)
969{
970 CGS_FUNC_ADEV;
971 acpi_handle handle;
972 struct acpi_object_list input;
973 struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
1a8e5f28 974 union acpi_object *params, *obj;
3f1d35a0 975 uint8_t name[5] = {'\0'};
eb09d7a7 976 struct cgs_acpi_method_argument *argument;
3f1d35a0
RZ		 977 uint32_t i, count;
978 acpi_status status;
b4fc5972 979 int result;
3f1d35a0
RZ		 980
981 handle = ACPI_HANDLE(&adev->pdev->dev);
982 if (!handle)
983 return -ENODEV;
984
985 memset(&input, 0, sizeof(struct acpi_object_list));
986
987 /* validate input info */
988 if (info->size != sizeof(struct cgs_acpi_method_info))
989 return -EINVAL;
990
991 input.count = info->input_count;
992 if (info->input_count > 0) {
993 if (info->pinput_argument == NULL)
994 return -EINVAL;
b92c26d1 995 argument = info->pinput_argument;
b92c26d1
DC		 996 for (i = 0; i < info->input_count; i++) {
997 if (((argument->type == ACPI_TYPE_STRING) ||
998 (argument->type == ACPI_TYPE_BUFFER)) &&
999 (argument->pointer == NULL))
1000 return -EINVAL;
1001 argument++;
1002 }
3f1d35a0
RZ		 1003 }
1004
1005 if (info->output_count > 0) {
1006 if (info->poutput_argument == NULL)
1007 return -EINVAL;
1008 argument = info->poutput_argument;
1009 for (i = 0; i < info->output_count; i++) {
1010 if (((argument->type == ACPI_TYPE_STRING) ||
1011 (argument->type == ACPI_TYPE_BUFFER))
1012 && (argument->pointer == NULL))
1013 return -EINVAL;
1014 argument++;
1015 }
1016 }
1017
1018 /* The path name passed to acpi_evaluate_object should be null terminated */
1019 if ((info->field & CGS_ACPI_FIELD_METHOD_NAME) != 0) {
1020 strncpy(name, (char *)&(info->name), sizeof(uint32_t));
1021 name[4] = '\0';
1022 }
1023
1024 /* parse input parameters */
1025 if (input.count > 0) {
1026 input.pointer = params =
1027 kzalloc(sizeof(union acpi_object) * input.count, GFP_KERNEL);
1028 if (params == NULL)
1029 return -EINVAL;
1030
1031 argument = info->pinput_argument;
1032
1033 for (i = 0; i < input.count; i++) {
1034 params->type = argument->type;
1035 switch (params->type) {
1036 case ACPI_TYPE_INTEGER:
1037 params->integer.value = argument->value;
1038 break;
1039 case ACPI_TYPE_STRING:
8db6f83b 1040 params->string.length = argument->data_length;
3f1d35a0
RZ		 1041 params->string.pointer = argument->pointer;
1042 break;
1043 case ACPI_TYPE_BUFFER:
8db6f83b 1044 params->buffer.length = argument->data_length;
3f1d35a0
RZ		 1045 params->buffer.pointer = argument->pointer;
1046 break;
1047 default:
1048 break;
1049 }
1050 params++;
1051 argument++;
1052 }
1053 }
1054
1055 /* parse output info */
1056 count = info->output_count;
1057 argument = info->poutput_argument;
1058
1059 /* evaluate the acpi method */
1060 status = acpi_evaluate_object(handle, name, &input, &output);
1061
1062 if (ACPI_FAILURE(status)) {
1063 result = -EIO;
1a8e5f28 1064 goto free_input;
3f1d35a0
RZ		 1065 }
1066
1067 /* return the output info */
1068 obj = output.pointer;
1069
1070 if (count > 1) {
1071 if ((obj->type != ACPI_TYPE_PACKAGE) ||
1072 (obj->package.count != count)) {
1073 result = -EIO;
1a8e5f28 1074 goto free_obj;
3f1d35a0
RZ		 1075 }
1076 params = obj->package.elements;
1077 } else
1078 params = obj;
1079
1080 if (params == NULL) {
1081 result = -EIO;
1a8e5f28 1082 goto free_obj;
3f1d35a0
RZ		 1083 }
1084
1085 for (i = 0; i < count; i++) {
1086 if (argument->type != params->type) {
1087 result = -EIO;
1a8e5f28 1088 goto free_obj;
3f1d35a0
RZ		 1089 }
1090 switch (params->type) {
1091 case ACPI_TYPE_INTEGER:
1092 argument->value = params->integer.value;
1093 break;
1094 case ACPI_TYPE_STRING:
1095 if ((params->string.length != argument->data_length) ||
1096 (params->string.pointer == NULL)) {
1097 result = -EIO;
1a8e5f28 1098 goto free_obj;
3f1d35a0
RZ		 1099 }
1100 strncpy(argument->pointer,
1101 params->string.pointer,
1102 params->string.length);
1103 break;
1104 case ACPI_TYPE_BUFFER:
1105 if (params->buffer.pointer == NULL) {
1106 result = -EIO;
1a8e5f28 1107 goto free_obj;
3f1d35a0
RZ		 1108 }
1109 memcpy(argument->pointer,
1110 params->buffer.pointer,
1111 argument->data_length);
1112 break;
1113 default:
1114 break;
1115 }
1116 argument++;
1117 params++;
1118 }
1119
b4fc5972 1120 result = 0;
1a8e5f28 1121free_obj:
a698e417 1122 kfree(obj);
1a8e5f28 1123free_input:
3f1d35a0
RZ		 1124 kfree((void *)input.pointer);
1125 return result;
1126}
1127#else
110e6f26 1128static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
3f1d35a0
RZ		 1129 struct cgs_acpi_method_info *info)
1130{
1131 return -EIO;
1132}
1133#endif
1134
eadf9543 1135static int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
3f1d35a0
RZ		 1136 uint32_t acpi_method,
1137 uint32_t acpi_function,
1138 void *pinput, void *poutput,
1139 uint32_t output_count,
1140 uint32_t input_size,
1141 uint32_t output_size)
1142{
1143 struct cgs_acpi_method_argument acpi_input[2] = { {0}, {0} };
1144 struct cgs_acpi_method_argument acpi_output = {0};
1145 struct cgs_acpi_method_info info = {0};
1146
1147 acpi_input[0].type = CGS_ACPI_TYPE_INTEGER;
3f1d35a0
RZ		 1148 acpi_input[0].data_length = sizeof(uint32_t);
1149 acpi_input[0].value = acpi_function;
1150
1151 acpi_input[1].type = CGS_ACPI_TYPE_BUFFER;
3f1d35a0
RZ		 1152 acpi_input[1].data_length = input_size;
1153 acpi_input[1].pointer = pinput;
1154
1155 acpi_output.type = CGS_ACPI_TYPE_BUFFER;
3f1d35a0
RZ		 1156 acpi_output.data_length = output_size;
1157 acpi_output.pointer = poutput;
1158
1159 info.size = sizeof(struct cgs_acpi_method_info);
1160 info.field = CGS_ACPI_FIELD_METHOD_NAME | CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT;
1161 info.input_count = 2;
1162 info.name = acpi_method;
1163 info.pinput_argument = acpi_input;
1164 info.output_count = output_count;
1165 info.poutput_argument = &acpi_output;
1166
1167 return amdgpu_cgs_acpi_eval_object(cgs_device, &info);
1168}
1169
d03846af
CZ		 1170static const struct cgs_ops amdgpu_cgs_ops = {
1171 amdgpu_cgs_gpu_mem_info,
1172 amdgpu_cgs_gmap_kmem,
1173 amdgpu_cgs_gunmap_kmem,
1174 amdgpu_cgs_alloc_gpu_mem,
1175 amdgpu_cgs_free_gpu_mem,
1176 amdgpu_cgs_gmap_gpu_mem,
1177 amdgpu_cgs_gunmap_gpu_mem,
1178 amdgpu_cgs_kmap_gpu_mem,
1179 amdgpu_cgs_kunmap_gpu_mem,
1180 amdgpu_cgs_read_register,
1181 amdgpu_cgs_write_register,
1182 amdgpu_cgs_read_ind_register,
1183 amdgpu_cgs_write_ind_register,
1184 amdgpu_cgs_read_pci_config_byte,
1185 amdgpu_cgs_read_pci_config_word,
1186 amdgpu_cgs_read_pci_config_dword,
1187 amdgpu_cgs_write_pci_config_byte,
1188 amdgpu_cgs_write_pci_config_word,
1189 amdgpu_cgs_write_pci_config_dword,
ba228ac8 1190 amdgpu_cgs_get_pci_resource,
d03846af
CZ		 1191 amdgpu_cgs_atom_get_data_table,
1192 amdgpu_cgs_atom_get_cmd_table_revs,
1193 amdgpu_cgs_atom_exec_cmd_table,
1194 amdgpu_cgs_create_pm_request,
1195 amdgpu_cgs_destroy_pm_request,
1196 amdgpu_cgs_set_pm_request,
1197 amdgpu_cgs_pm_request_clock,
1198 amdgpu_cgs_pm_request_engine,
1199 amdgpu_cgs_pm_query_clock_limits,
bf3911b0 1200 amdgpu_cgs_set_camera_voltages,
404b2fa3 1201 amdgpu_cgs_get_firmware_info,
a392746a 1202 amdgpu_cgs_rel_firmware,
404b2fa3 1203 amdgpu_cgs_set_powergating_state,
3f1d35a0 1204 amdgpu_cgs_set_clockgating_state,
47bf18b5 1205 amdgpu_cgs_get_active_displays_info,
4c90080b 1206 amdgpu_cgs_notify_dpm_enabled,
3f1d35a0 1207 amdgpu_cgs_call_acpi_method,
5e618699 1208 amdgpu_cgs_query_system_info,
d03846af
CZ		 1209};
1210
1211static const struct cgs_os_ops amdgpu_cgs_os_ops = {
d03846af
CZ		 1212 amdgpu_cgs_add_irq_source,
1213 amdgpu_cgs_irq_get,
1214 amdgpu_cgs_irq_put
1215};
1216
110e6f26 1217struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
d03846af
CZ		 1218{
1219 struct amdgpu_cgs_device *cgs_device =
1220 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
1221
1222 if (!cgs_device) {
1223 DRM_ERROR("Couldn't allocate CGS device structure\n");
1224 return NULL;
1225 }
1226
1227 cgs_device->base.ops = &amdgpu_cgs_ops;
1228 cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
1229 cgs_device->adev = adev;
1230
110e6f26 1231 return (struct cgs_device *)cgs_device;
d03846af
CZ		 1232}
1233
110e6f26 1234void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
d03846af
CZ		 1235{
1236 kfree(cgs_device);
1237}
ubuntu-bionic-kernel mirror