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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
568d7c76 | 27 | #include <linux/pagemap.h> |
d38ceaf9 AD |
28 | #include <drm/drmP.h> |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
d38ceaf9 AD |
33 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, |
34 | u32 ip_instance, u32 ring, | |
35 | struct amdgpu_ring **out_ring) | |
36 | { | |
37 | /* Right now all IPs have only one instance - multiple rings. */ | |
38 | if (ip_instance != 0) { | |
39 | DRM_ERROR("invalid ip instance: %d\n", ip_instance); | |
40 | return -EINVAL; | |
41 | } | |
42 | ||
43 | switch (ip_type) { | |
44 | default: | |
45 | DRM_ERROR("unknown ip type: %d\n", ip_type); | |
46 | return -EINVAL; | |
47 | case AMDGPU_HW_IP_GFX: | |
48 | if (ring < adev->gfx.num_gfx_rings) { | |
49 | *out_ring = &adev->gfx.gfx_ring[ring]; | |
50 | } else { | |
51 | DRM_ERROR("only %d gfx rings are supported now\n", | |
52 | adev->gfx.num_gfx_rings); | |
53 | return -EINVAL; | |
54 | } | |
55 | break; | |
56 | case AMDGPU_HW_IP_COMPUTE: | |
57 | if (ring < adev->gfx.num_compute_rings) { | |
58 | *out_ring = &adev->gfx.compute_ring[ring]; | |
59 | } else { | |
60 | DRM_ERROR("only %d compute rings are supported now\n", | |
61 | adev->gfx.num_compute_rings); | |
62 | return -EINVAL; | |
63 | } | |
64 | break; | |
65 | case AMDGPU_HW_IP_DMA: | |
c113ea1c AD |
66 | if (ring < adev->sdma.num_instances) { |
67 | *out_ring = &adev->sdma.instance[ring].ring; | |
d38ceaf9 | 68 | } else { |
c113ea1c AD |
69 | DRM_ERROR("only %d SDMA rings are supported\n", |
70 | adev->sdma.num_instances); | |
d38ceaf9 AD |
71 | return -EINVAL; |
72 | } | |
73 | break; | |
74 | case AMDGPU_HW_IP_UVD: | |
75 | *out_ring = &adev->uvd.ring; | |
76 | break; | |
77 | case AMDGPU_HW_IP_VCE: | |
78 | if (ring < 2){ | |
79 | *out_ring = &adev->vce.ring[ring]; | |
80 | } else { | |
81 | DRM_ERROR("only two VCE rings are supported\n"); | |
82 | return -EINVAL; | |
83 | } | |
84 | break; | |
85 | } | |
86 | return 0; | |
87 | } | |
88 | ||
91acbeb6 | 89 | static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, |
758ac17f CK |
90 | struct drm_amdgpu_cs_chunk_fence *data, |
91 | uint32_t *offset) | |
91acbeb6 CK |
92 | { |
93 | struct drm_gem_object *gobj; | |
aa29040b | 94 | unsigned long size; |
91acbeb6 | 95 | |
a8ad0bd8 | 96 | gobj = drm_gem_object_lookup(p->filp, data->handle); |
91acbeb6 CK |
97 | if (gobj == NULL) |
98 | return -EINVAL; | |
99 | ||
758ac17f | 100 | p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); |
91acbeb6 CK |
101 | p->uf_entry.priority = 0; |
102 | p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; | |
103 | p->uf_entry.tv.shared = true; | |
2f568dbd | 104 | p->uf_entry.user_pages = NULL; |
aa29040b CK |
105 | |
106 | size = amdgpu_bo_size(p->uf_entry.robj); | |
107 | if (size != PAGE_SIZE || (data->offset + 8) > size) | |
108 | return -EINVAL; | |
109 | ||
758ac17f | 110 | *offset = data->offset; |
91acbeb6 CK |
111 | |
112 | drm_gem_object_unreference_unlocked(gobj); | |
758ac17f CK |
113 | |
114 | if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) { | |
115 | amdgpu_bo_unref(&p->uf_entry.robj); | |
116 | return -EINVAL; | |
117 | } | |
118 | ||
91acbeb6 CK |
119 | return 0; |
120 | } | |
121 | ||
d38ceaf9 AD |
122 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) |
123 | { | |
4c0b242c | 124 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
c5637837 | 125 | struct amdgpu_vm *vm = &fpriv->vm; |
d38ceaf9 AD |
126 | union drm_amdgpu_cs *cs = data; |
127 | uint64_t *chunk_array_user; | |
1d263474 | 128 | uint64_t *chunk_array; |
50838c8c | 129 | unsigned size, num_ibs = 0; |
758ac17f | 130 | uint32_t uf_offset = 0; |
54313503 | 131 | int i; |
1d263474 | 132 | int ret; |
d38ceaf9 | 133 | |
1d263474 DC |
134 | if (cs->in.num_chunks == 0) |
135 | return 0; | |
136 | ||
137 | chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); | |
138 | if (!chunk_array) | |
139 | return -ENOMEM; | |
d38ceaf9 | 140 | |
3cb485f3 CK |
141 | p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); |
142 | if (!p->ctx) { | |
1d263474 DC |
143 | ret = -EINVAL; |
144 | goto free_chunk; | |
3cb485f3 | 145 | } |
1d263474 | 146 | |
d38ceaf9 | 147 | /* get chunks */ |
028423b0 | 148 | chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); |
d38ceaf9 AD |
149 | if (copy_from_user(chunk_array, chunk_array_user, |
150 | sizeof(uint64_t)*cs->in.num_chunks)) { | |
1d263474 | 151 | ret = -EFAULT; |
2a7d9bda | 152 | goto put_ctx; |
d38ceaf9 AD |
153 | } |
154 | ||
155 | p->nchunks = cs->in.num_chunks; | |
e60b344f | 156 | p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), |
d38ceaf9 | 157 | GFP_KERNEL); |
1d263474 DC |
158 | if (!p->chunks) { |
159 | ret = -ENOMEM; | |
2a7d9bda | 160 | goto put_ctx; |
d38ceaf9 AD |
161 | } |
162 | ||
163 | for (i = 0; i < p->nchunks; i++) { | |
164 | struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; | |
165 | struct drm_amdgpu_cs_chunk user_chunk; | |
166 | uint32_t __user *cdata; | |
167 | ||
028423b0 | 168 | chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; |
d38ceaf9 AD |
169 | if (copy_from_user(&user_chunk, chunk_ptr, |
170 | sizeof(struct drm_amdgpu_cs_chunk))) { | |
1d263474 DC |
171 | ret = -EFAULT; |
172 | i--; | |
173 | goto free_partial_kdata; | |
d38ceaf9 AD |
174 | } |
175 | p->chunks[i].chunk_id = user_chunk.chunk_id; | |
176 | p->chunks[i].length_dw = user_chunk.length_dw; | |
d38ceaf9 AD |
177 | |
178 | size = p->chunks[i].length_dw; | |
028423b0 | 179 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; |
d38ceaf9 AD |
180 | |
181 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
182 | if (p->chunks[i].kdata == NULL) { | |
1d263474 DC |
183 | ret = -ENOMEM; |
184 | i--; | |
185 | goto free_partial_kdata; | |
d38ceaf9 AD |
186 | } |
187 | size *= sizeof(uint32_t); | |
188 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { | |
1d263474 DC |
189 | ret = -EFAULT; |
190 | goto free_partial_kdata; | |
d38ceaf9 AD |
191 | } |
192 | ||
9a5e8fb1 CK |
193 | switch (p->chunks[i].chunk_id) { |
194 | case AMDGPU_CHUNK_ID_IB: | |
50838c8c | 195 | ++num_ibs; |
9a5e8fb1 CK |
196 | break; |
197 | ||
198 | case AMDGPU_CHUNK_ID_FENCE: | |
d38ceaf9 | 199 | size = sizeof(struct drm_amdgpu_cs_chunk_fence); |
91acbeb6 | 200 | if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { |
1d263474 DC |
201 | ret = -EINVAL; |
202 | goto free_partial_kdata; | |
d38ceaf9 | 203 | } |
91acbeb6 | 204 | |
758ac17f CK |
205 | ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata, |
206 | &uf_offset); | |
91acbeb6 CK |
207 | if (ret) |
208 | goto free_partial_kdata; | |
209 | ||
9a5e8fb1 CK |
210 | break; |
211 | ||
2b48d323 CK |
212 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
213 | break; | |
214 | ||
9a5e8fb1 | 215 | default: |
1d263474 DC |
216 | ret = -EINVAL; |
217 | goto free_partial_kdata; | |
d38ceaf9 AD |
218 | } |
219 | } | |
220 | ||
c5637837 | 221 | ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm); |
50838c8c | 222 | if (ret) |
4acabfe3 | 223 | goto free_all_kdata; |
d38ceaf9 | 224 | |
b5f5acbc CK |
225 | if (p->uf_entry.robj) |
226 | p->job->uf_addr = uf_offset; | |
d38ceaf9 | 227 | kfree(chunk_array); |
1d263474 DC |
228 | return 0; |
229 | ||
230 | free_all_kdata: | |
231 | i = p->nchunks - 1; | |
232 | free_partial_kdata: | |
233 | for (; i >= 0; i--) | |
234 | drm_free_large(p->chunks[i].kdata); | |
235 | kfree(p->chunks); | |
2a7d9bda | 236 | put_ctx: |
1d263474 DC |
237 | amdgpu_ctx_put(p->ctx); |
238 | free_chunk: | |
239 | kfree(chunk_array); | |
240 | ||
241 | return ret; | |
d38ceaf9 AD |
242 | } |
243 | ||
95844d20 MO |
244 | /* Convert microseconds to bytes. */ |
245 | static u64 us_to_bytes(struct amdgpu_device *adev, s64 us) | |
246 | { | |
247 | if (us <= 0 || !adev->mm_stats.log2_max_MBps) | |
248 | return 0; | |
249 | ||
250 | /* Since accum_us is incremented by a million per second, just | |
251 | * multiply it by the number of MB/s to get the number of bytes. | |
252 | */ | |
253 | return us << adev->mm_stats.log2_max_MBps; | |
254 | } | |
255 | ||
256 | static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes) | |
257 | { | |
258 | if (!adev->mm_stats.log2_max_MBps) | |
259 | return 0; | |
260 | ||
261 | return bytes >> adev->mm_stats.log2_max_MBps; | |
262 | } | |
263 | ||
264 | /* Returns how many bytes TTM can move right now. If no bytes can be moved, | |
265 | * it returns 0. If it returns non-zero, it's OK to move at least one buffer, | |
266 | * which means it can go over the threshold once. If that happens, the driver | |
267 | * will be in debt and no other buffer migrations can be done until that debt | |
268 | * is repaid. | |
269 | * | |
270 | * This approach allows moving a buffer of any size (it's important to allow | |
271 | * that). | |
272 | * | |
273 | * The currency is simply time in microseconds and it increases as the clock | |
274 | * ticks. The accumulated microseconds (us) are converted to bytes and | |
275 | * returned. | |
d38ceaf9 AD |
276 | */ |
277 | static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) | |
278 | { | |
95844d20 MO |
279 | s64 time_us, increment_us; |
280 | u64 max_bytes; | |
281 | u64 free_vram, total_vram, used_vram; | |
d38ceaf9 | 282 | |
95844d20 MO |
283 | /* Allow a maximum of 200 accumulated ms. This is basically per-IB |
284 | * throttling. | |
d38ceaf9 | 285 | * |
95844d20 MO |
286 | * It means that in order to get full max MBps, at least 5 IBs per |
287 | * second must be submitted and not more than 200ms apart from each | |
288 | * other. | |
289 | */ | |
290 | const s64 us_upper_bound = 200000; | |
d38ceaf9 | 291 | |
95844d20 MO |
292 | if (!adev->mm_stats.log2_max_MBps) |
293 | return 0; | |
294 | ||
295 | total_vram = adev->mc.real_vram_size - adev->vram_pin_size; | |
296 | used_vram = atomic64_read(&adev->vram_usage); | |
297 | free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram; | |
298 | ||
299 | spin_lock(&adev->mm_stats.lock); | |
300 | ||
301 | /* Increase the amount of accumulated us. */ | |
302 | time_us = ktime_to_us(ktime_get()); | |
303 | increment_us = time_us - adev->mm_stats.last_update_us; | |
304 | adev->mm_stats.last_update_us = time_us; | |
305 | adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us, | |
306 | us_upper_bound); | |
307 | ||
308 | /* This prevents the short period of low performance when the VRAM | |
309 | * usage is low and the driver is in debt or doesn't have enough | |
310 | * accumulated us to fill VRAM quickly. | |
d38ceaf9 | 311 | * |
95844d20 MO |
312 | * The situation can occur in these cases: |
313 | * - a lot of VRAM is freed by userspace | |
314 | * - the presence of a big buffer causes a lot of evictions | |
315 | * (solution: split buffers into smaller ones) | |
d38ceaf9 | 316 | * |
95844d20 MO |
317 | * If 128 MB or 1/8th of VRAM is free, start filling it now by setting |
318 | * accum_us to a positive number. | |
d38ceaf9 | 319 | */ |
95844d20 MO |
320 | if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) { |
321 | s64 min_us; | |
322 | ||
323 | /* Be more aggresive on dGPUs. Try to fill a portion of free | |
324 | * VRAM now. | |
325 | */ | |
326 | if (!(adev->flags & AMD_IS_APU)) | |
327 | min_us = bytes_to_us(adev, free_vram / 4); | |
328 | else | |
329 | min_us = 0; /* Reset accum_us on APUs. */ | |
330 | ||
331 | adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us); | |
332 | } | |
d38ceaf9 | 333 | |
95844d20 MO |
334 | /* This returns 0 if the driver is in debt to disallow (optional) |
335 | * buffer moves. | |
336 | */ | |
337 | max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us); | |
338 | ||
339 | spin_unlock(&adev->mm_stats.lock); | |
340 | return max_bytes; | |
341 | } | |
342 | ||
343 | /* Report how many bytes have really been moved for the last command | |
344 | * submission. This can result in a debt that can stop buffer migrations | |
345 | * temporarily. | |
346 | */ | |
347 | static void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, | |
348 | u64 num_bytes) | |
349 | { | |
350 | spin_lock(&adev->mm_stats.lock); | |
351 | adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes); | |
352 | spin_unlock(&adev->mm_stats.lock); | |
d38ceaf9 AD |
353 | } |
354 | ||
14fd833e CZ |
355 | static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, |
356 | struct amdgpu_bo *bo) | |
357 | { | |
a7d64de6 | 358 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
14fd833e CZ |
359 | u64 initial_bytes_moved; |
360 | uint32_t domain; | |
361 | int r; | |
362 | ||
363 | if (bo->pin_count) | |
364 | return 0; | |
365 | ||
95844d20 MO |
366 | /* Don't move this buffer if we have depleted our allowance |
367 | * to move it. Don't move anything if the threshold is zero. | |
14fd833e | 368 | */ |
95844d20 | 369 | if (p->bytes_moved < p->bytes_moved_threshold) |
14fd833e CZ |
370 | domain = bo->prefered_domains; |
371 | else | |
372 | domain = bo->allowed_domains; | |
373 | ||
374 | retry: | |
375 | amdgpu_ttm_placement_from_domain(bo, domain); | |
a7d64de6 | 376 | initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); |
14fd833e | 377 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
a7d64de6 | 378 | p->bytes_moved += atomic64_read(&adev->num_bytes_moved) - |
14fd833e CZ |
379 | initial_bytes_moved; |
380 | ||
1abdc3d7 CK |
381 | if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { |
382 | domain = bo->allowed_domains; | |
383 | goto retry; | |
14fd833e CZ |
384 | } |
385 | ||
386 | return r; | |
387 | } | |
388 | ||
662bfa61 CK |
389 | /* Last resort, try to evict something from the current working set */ |
390 | static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, | |
f7da30d9 | 391 | struct amdgpu_bo *validated) |
662bfa61 | 392 | { |
f7da30d9 | 393 | uint32_t domain = validated->allowed_domains; |
662bfa61 CK |
394 | int r; |
395 | ||
396 | if (!p->evictable) | |
397 | return false; | |
398 | ||
399 | for (;&p->evictable->tv.head != &p->validated; | |
400 | p->evictable = list_prev_entry(p->evictable, tv.head)) { | |
401 | ||
402 | struct amdgpu_bo_list_entry *candidate = p->evictable; | |
403 | struct amdgpu_bo *bo = candidate->robj; | |
a7d64de6 | 404 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
662bfa61 CK |
405 | u64 initial_bytes_moved; |
406 | uint32_t other; | |
407 | ||
408 | /* If we reached our current BO we can forget it */ | |
f7da30d9 | 409 | if (candidate->robj == validated) |
662bfa61 CK |
410 | break; |
411 | ||
412 | other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
413 | ||
414 | /* Check if this BO is in one of the domains we need space for */ | |
415 | if (!(other & domain)) | |
416 | continue; | |
417 | ||
418 | /* Check if we can move this BO somewhere else */ | |
419 | other = bo->allowed_domains & ~domain; | |
420 | if (!other) | |
421 | continue; | |
422 | ||
423 | /* Good we can try to move this BO somewhere else */ | |
424 | amdgpu_ttm_placement_from_domain(bo, other); | |
a7d64de6 | 425 | initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); |
662bfa61 | 426 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
a7d64de6 | 427 | p->bytes_moved += atomic64_read(&adev->num_bytes_moved) - |
662bfa61 CK |
428 | initial_bytes_moved; |
429 | ||
430 | if (unlikely(r)) | |
431 | break; | |
432 | ||
433 | p->evictable = list_prev_entry(p->evictable, tv.head); | |
434 | list_move(&candidate->tv.head, &p->validated); | |
435 | ||
436 | return true; | |
437 | } | |
438 | ||
439 | return false; | |
440 | } | |
441 | ||
f7da30d9 CK |
442 | static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo) |
443 | { | |
444 | struct amdgpu_cs_parser *p = param; | |
445 | int r; | |
446 | ||
447 | do { | |
448 | r = amdgpu_cs_bo_validate(p, bo); | |
449 | } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo)); | |
450 | if (r) | |
451 | return r; | |
452 | ||
453 | if (bo->shadow) | |
454 | r = amdgpu_cs_bo_validate(p, bo); | |
455 | ||
456 | return r; | |
457 | } | |
458 | ||
761c2e82 | 459 | static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, |
a5b75058 | 460 | struct list_head *validated) |
d38ceaf9 | 461 | { |
d38ceaf9 | 462 | struct amdgpu_bo_list_entry *lobj; |
d38ceaf9 AD |
463 | int r; |
464 | ||
a5b75058 | 465 | list_for_each_entry(lobj, validated, tv.head) { |
36409d12 | 466 | struct amdgpu_bo *bo = lobj->robj; |
2f568dbd | 467 | bool binding_userptr = false; |
cc325d19 | 468 | struct mm_struct *usermm; |
d38ceaf9 | 469 | |
cc325d19 CK |
470 | usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); |
471 | if (usermm && usermm != current->mm) | |
472 | return -EPERM; | |
473 | ||
2f568dbd CK |
474 | /* Check if we have user pages and nobody bound the BO already */ |
475 | if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) { | |
476 | size_t size = sizeof(struct page *); | |
477 | ||
478 | size *= bo->tbo.ttm->num_pages; | |
479 | memcpy(bo->tbo.ttm->pages, lobj->user_pages, size); | |
480 | binding_userptr = true; | |
481 | } | |
482 | ||
662bfa61 CK |
483 | if (p->evictable == lobj) |
484 | p->evictable = NULL; | |
485 | ||
f7da30d9 | 486 | r = amdgpu_cs_validate(p, bo); |
14fd833e | 487 | if (r) |
36409d12 | 488 | return r; |
662bfa61 | 489 | |
2f568dbd CK |
490 | if (binding_userptr) { |
491 | drm_free_large(lobj->user_pages); | |
492 | lobj->user_pages = NULL; | |
493 | } | |
d38ceaf9 AD |
494 | } |
495 | return 0; | |
496 | } | |
497 | ||
2a7d9bda CK |
498 | static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, |
499 | union drm_amdgpu_cs *cs) | |
d38ceaf9 AD |
500 | { |
501 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
2f568dbd | 502 | struct amdgpu_bo_list_entry *e; |
a5b75058 | 503 | struct list_head duplicates; |
840d5144 | 504 | bool need_mmap_lock = false; |
2f568dbd | 505 | unsigned i, tries = 10; |
636ce25c | 506 | int r; |
d38ceaf9 | 507 | |
2a7d9bda CK |
508 | INIT_LIST_HEAD(&p->validated); |
509 | ||
510 | p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); | |
840d5144 | 511 | if (p->bo_list) { |
211dff55 CK |
512 | need_mmap_lock = p->bo_list->first_userptr != |
513 | p->bo_list->num_entries; | |
636ce25c | 514 | amdgpu_bo_list_get_list(p->bo_list, &p->validated); |
840d5144 | 515 | } |
d38ceaf9 | 516 | |
3c0eea6c | 517 | INIT_LIST_HEAD(&duplicates); |
56467ebf | 518 | amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); |
d38ceaf9 | 519 | |
758ac17f | 520 | if (p->uf_entry.robj) |
91acbeb6 CK |
521 | list_add(&p->uf_entry.tv.head, &p->validated); |
522 | ||
d38ceaf9 AD |
523 | if (need_mmap_lock) |
524 | down_read(¤t->mm->mmap_sem); | |
525 | ||
2f568dbd CK |
526 | while (1) { |
527 | struct list_head need_pages; | |
528 | unsigned i; | |
529 | ||
530 | r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, | |
531 | &duplicates); | |
f1037950 MO |
532 | if (unlikely(r != 0)) { |
533 | DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); | |
2f568dbd | 534 | goto error_free_pages; |
f1037950 | 535 | } |
2f568dbd CK |
536 | |
537 | /* Without a BO list we don't have userptr BOs */ | |
538 | if (!p->bo_list) | |
539 | break; | |
540 | ||
541 | INIT_LIST_HEAD(&need_pages); | |
542 | for (i = p->bo_list->first_userptr; | |
543 | i < p->bo_list->num_entries; ++i) { | |
544 | ||
545 | e = &p->bo_list->array[i]; | |
546 | ||
547 | if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm, | |
548 | &e->user_invalidated) && e->user_pages) { | |
549 | ||
550 | /* We acquired a page array, but somebody | |
551 | * invalidated it. Free it an try again | |
552 | */ | |
553 | release_pages(e->user_pages, | |
554 | e->robj->tbo.ttm->num_pages, | |
555 | false); | |
556 | drm_free_large(e->user_pages); | |
557 | e->user_pages = NULL; | |
558 | } | |
559 | ||
560 | if (e->robj->tbo.ttm->state != tt_bound && | |
561 | !e->user_pages) { | |
562 | list_del(&e->tv.head); | |
563 | list_add(&e->tv.head, &need_pages); | |
564 | ||
565 | amdgpu_bo_unreserve(e->robj); | |
566 | } | |
567 | } | |
568 | ||
569 | if (list_empty(&need_pages)) | |
570 | break; | |
571 | ||
572 | /* Unreserve everything again. */ | |
573 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
574 | ||
f1037950 | 575 | /* We tried too many times, just abort */ |
2f568dbd CK |
576 | if (!--tries) { |
577 | r = -EDEADLK; | |
f1037950 | 578 | DRM_ERROR("deadlock in %s\n", __func__); |
2f568dbd CK |
579 | goto error_free_pages; |
580 | } | |
581 | ||
582 | /* Fill the page arrays for all useptrs. */ | |
583 | list_for_each_entry(e, &need_pages, tv.head) { | |
584 | struct ttm_tt *ttm = e->robj->tbo.ttm; | |
585 | ||
586 | e->user_pages = drm_calloc_large(ttm->num_pages, | |
587 | sizeof(struct page*)); | |
588 | if (!e->user_pages) { | |
589 | r = -ENOMEM; | |
f1037950 | 590 | DRM_ERROR("calloc failure in %s\n", __func__); |
2f568dbd CK |
591 | goto error_free_pages; |
592 | } | |
593 | ||
594 | r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages); | |
595 | if (r) { | |
f1037950 | 596 | DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); |
2f568dbd CK |
597 | drm_free_large(e->user_pages); |
598 | e->user_pages = NULL; | |
599 | goto error_free_pages; | |
600 | } | |
601 | } | |
602 | ||
603 | /* And try again. */ | |
604 | list_splice(&need_pages, &p->validated); | |
605 | } | |
a5b75058 | 606 | |
f69f90a1 CK |
607 | p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev); |
608 | p->bytes_moved = 0; | |
662bfa61 CK |
609 | p->evictable = list_last_entry(&p->validated, |
610 | struct amdgpu_bo_list_entry, | |
611 | tv.head); | |
f69f90a1 | 612 | |
f7da30d9 CK |
613 | r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm, |
614 | amdgpu_cs_validate, p); | |
615 | if (r) { | |
616 | DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n"); | |
617 | goto error_validate; | |
618 | } | |
619 | ||
f69f90a1 | 620 | r = amdgpu_cs_list_validate(p, &duplicates); |
f1037950 MO |
621 | if (r) { |
622 | DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n"); | |
a5b75058 | 623 | goto error_validate; |
f1037950 | 624 | } |
a5b75058 | 625 | |
f69f90a1 | 626 | r = amdgpu_cs_list_validate(p, &p->validated); |
f1037950 MO |
627 | if (r) { |
628 | DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n"); | |
a8480309 | 629 | goto error_validate; |
f1037950 | 630 | } |
a8480309 | 631 | |
95844d20 MO |
632 | amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved); |
633 | ||
5a712a87 CK |
634 | fpriv->vm.last_eviction_counter = |
635 | atomic64_read(&p->adev->num_evictions); | |
636 | ||
a8480309 | 637 | if (p->bo_list) { |
d88bf583 CK |
638 | struct amdgpu_bo *gds = p->bo_list->gds_obj; |
639 | struct amdgpu_bo *gws = p->bo_list->gws_obj; | |
640 | struct amdgpu_bo *oa = p->bo_list->oa_obj; | |
a8480309 CK |
641 | struct amdgpu_vm *vm = &fpriv->vm; |
642 | unsigned i; | |
643 | ||
644 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
645 | struct amdgpu_bo *bo = p->bo_list->array[i].robj; | |
646 | ||
647 | p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo); | |
648 | } | |
d88bf583 CK |
649 | |
650 | if (gds) { | |
651 | p->job->gds_base = amdgpu_bo_gpu_offset(gds); | |
652 | p->job->gds_size = amdgpu_bo_size(gds); | |
653 | } | |
654 | if (gws) { | |
655 | p->job->gws_base = amdgpu_bo_gpu_offset(gws); | |
656 | p->job->gws_size = amdgpu_bo_size(gws); | |
657 | } | |
658 | if (oa) { | |
659 | p->job->oa_base = amdgpu_bo_gpu_offset(oa); | |
660 | p->job->oa_size = amdgpu_bo_size(oa); | |
661 | } | |
a8480309 | 662 | } |
a5b75058 | 663 | |
c855e250 CK |
664 | if (!r && p->uf_entry.robj) { |
665 | struct amdgpu_bo *uf = p->uf_entry.robj; | |
666 | ||
bb990bb0 | 667 | r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem); |
c855e250 CK |
668 | p->job->uf_addr += amdgpu_bo_gpu_offset(uf); |
669 | } | |
b5f5acbc | 670 | |
a5b75058 | 671 | error_validate: |
eceb8a15 CK |
672 | if (r) { |
673 | amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); | |
a5b75058 | 674 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); |
eceb8a15 | 675 | } |
d38ceaf9 | 676 | |
2f568dbd CK |
677 | error_free_pages: |
678 | ||
d38ceaf9 AD |
679 | if (need_mmap_lock) |
680 | up_read(¤t->mm->mmap_sem); | |
681 | ||
2f568dbd CK |
682 | if (p->bo_list) { |
683 | for (i = p->bo_list->first_userptr; | |
684 | i < p->bo_list->num_entries; ++i) { | |
685 | e = &p->bo_list->array[i]; | |
686 | ||
687 | if (!e->user_pages) | |
688 | continue; | |
689 | ||
690 | release_pages(e->user_pages, | |
691 | e->robj->tbo.ttm->num_pages, | |
692 | false); | |
693 | drm_free_large(e->user_pages); | |
694 | } | |
695 | } | |
696 | ||
d38ceaf9 AD |
697 | return r; |
698 | } | |
699 | ||
700 | static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
701 | { | |
702 | struct amdgpu_bo_list_entry *e; | |
703 | int r; | |
704 | ||
705 | list_for_each_entry(e, &p->validated, tv.head) { | |
706 | struct reservation_object *resv = e->robj->tbo.resv; | |
e86f9cee | 707 | r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp); |
d38ceaf9 AD |
708 | |
709 | if (r) | |
710 | return r; | |
711 | } | |
712 | return 0; | |
713 | } | |
714 | ||
984810fc CK |
715 | /** |
716 | * cs_parser_fini() - clean parser states | |
717 | * @parser: parser structure holding parsing context. | |
718 | * @error: error number | |
719 | * | |
720 | * If error is set than unvalidate buffer, otherwise just free memory | |
721 | * used by parsing context. | |
722 | **/ | |
723 | static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) | |
049fc527 | 724 | { |
eceb8a15 | 725 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; |
984810fc CK |
726 | unsigned i; |
727 | ||
d38ceaf9 | 728 | if (!error) { |
28b8d66e NH |
729 | amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); |
730 | ||
d38ceaf9 | 731 | ttm_eu_fence_buffer_objects(&parser->ticket, |
984810fc CK |
732 | &parser->validated, |
733 | parser->fence); | |
d38ceaf9 AD |
734 | } else if (backoff) { |
735 | ttm_eu_backoff_reservation(&parser->ticket, | |
736 | &parser->validated); | |
737 | } | |
984810fc | 738 | fence_put(parser->fence); |
7e52a81c | 739 | |
3cb485f3 CK |
740 | if (parser->ctx) |
741 | amdgpu_ctx_put(parser->ctx); | |
a3348bb8 CZ |
742 | if (parser->bo_list) |
743 | amdgpu_bo_list_put(parser->bo_list); | |
744 | ||
d38ceaf9 AD |
745 | for (i = 0; i < parser->nchunks; i++) |
746 | drm_free_large(parser->chunks[i].kdata); | |
747 | kfree(parser->chunks); | |
50838c8c CK |
748 | if (parser->job) |
749 | amdgpu_job_free(parser->job); | |
91acbeb6 | 750 | amdgpu_bo_unref(&parser->uf_entry.robj); |
d38ceaf9 AD |
751 | } |
752 | ||
753 | static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, | |
754 | struct amdgpu_vm *vm) | |
755 | { | |
756 | struct amdgpu_device *adev = p->adev; | |
757 | struct amdgpu_bo_va *bo_va; | |
758 | struct amdgpu_bo *bo; | |
759 | int i, r; | |
760 | ||
761 | r = amdgpu_vm_update_page_directory(adev, vm); | |
762 | if (r) | |
763 | return r; | |
764 | ||
e86f9cee | 765 | r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence); |
05906dec BN |
766 | if (r) |
767 | return r; | |
768 | ||
d38ceaf9 AD |
769 | r = amdgpu_vm_clear_freed(adev, vm); |
770 | if (r) | |
771 | return r; | |
772 | ||
773 | if (p->bo_list) { | |
774 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
91e1a520 CK |
775 | struct fence *f; |
776 | ||
d38ceaf9 AD |
777 | /* ignore duplicates */ |
778 | bo = p->bo_list->array[i].robj; | |
779 | if (!bo) | |
780 | continue; | |
781 | ||
782 | bo_va = p->bo_list->array[i].bo_va; | |
783 | if (bo_va == NULL) | |
784 | continue; | |
785 | ||
99e124f4 | 786 | r = amdgpu_vm_bo_update(adev, bo_va, false); |
d38ceaf9 AD |
787 | if (r) |
788 | return r; | |
789 | ||
bb1e38a4 | 790 | f = bo_va->last_pt_update; |
e86f9cee | 791 | r = amdgpu_sync_fence(adev, &p->job->sync, f); |
91e1a520 CK |
792 | if (r) |
793 | return r; | |
d38ceaf9 | 794 | } |
b495bd3a CK |
795 | |
796 | } | |
797 | ||
e86f9cee | 798 | r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync); |
b495bd3a CK |
799 | |
800 | if (amdgpu_vm_debug && p->bo_list) { | |
801 | /* Invalidate all BOs to test for userspace bugs */ | |
802 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
803 | /* ignore duplicates */ | |
804 | bo = p->bo_list->array[i].robj; | |
805 | if (!bo) | |
806 | continue; | |
807 | ||
808 | amdgpu_vm_bo_invalidate(adev, bo); | |
809 | } | |
d38ceaf9 AD |
810 | } |
811 | ||
b495bd3a | 812 | return r; |
d38ceaf9 AD |
813 | } |
814 | ||
815 | static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, | |
b07c60c0 | 816 | struct amdgpu_cs_parser *p) |
d38ceaf9 | 817 | { |
b07c60c0 | 818 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
d38ceaf9 | 819 | struct amdgpu_vm *vm = &fpriv->vm; |
b07c60c0 | 820 | struct amdgpu_ring *ring = p->job->ring; |
d38ceaf9 AD |
821 | int i, r; |
822 | ||
d38ceaf9 | 823 | /* Only for UVD/VCE VM emulation */ |
b07c60c0 CK |
824 | if (ring->funcs->parse_cs) { |
825 | for (i = 0; i < p->job->num_ibs; i++) { | |
826 | r = amdgpu_ring_parse_cs(ring, p, i); | |
d38ceaf9 AD |
827 | if (r) |
828 | return r; | |
829 | } | |
45088efc CK |
830 | } |
831 | ||
832 | if (p->job->vm) { | |
9a79588c | 833 | p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); |
281d144d | 834 | |
9a79588c CK |
835 | r = amdgpu_bo_vm_update_pte(p, vm); |
836 | if (r) | |
837 | return r; | |
838 | } | |
d38ceaf9 | 839 | |
9a79588c | 840 | return amdgpu_cs_sync_rings(p); |
d38ceaf9 AD |
841 | } |
842 | ||
843 | static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) | |
844 | { | |
845 | if (r == -EDEADLK) { | |
846 | r = amdgpu_gpu_reset(adev); | |
847 | if (!r) | |
848 | r = -EAGAIN; | |
849 | } | |
850 | return r; | |
851 | } | |
852 | ||
853 | static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |
854 | struct amdgpu_cs_parser *parser) | |
855 | { | |
856 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
857 | struct amdgpu_vm *vm = &fpriv->vm; | |
858 | int i, j; | |
859 | int r; | |
860 | ||
50838c8c | 861 | for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) { |
d38ceaf9 AD |
862 | struct amdgpu_cs_chunk *chunk; |
863 | struct amdgpu_ib *ib; | |
864 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
d38ceaf9 | 865 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
866 | |
867 | chunk = &parser->chunks[i]; | |
50838c8c | 868 | ib = &parser->job->ibs[j]; |
d38ceaf9 AD |
869 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; |
870 | ||
871 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
872 | continue; | |
873 | ||
d38ceaf9 AD |
874 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, |
875 | chunk_ib->ip_instance, chunk_ib->ring, | |
876 | &ring); | |
3ccec53c | 877 | if (r) |
d38ceaf9 | 878 | return r; |
d38ceaf9 | 879 | |
753ad49c ML |
880 | if (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) { |
881 | parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT; | |
882 | if (!parser->ctx->preamble_presented) { | |
883 | parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST; | |
884 | parser->ctx->preamble_presented = true; | |
885 | } | |
886 | } | |
887 | ||
b07c60c0 CK |
888 | if (parser->job->ring && parser->job->ring != ring) |
889 | return -EINVAL; | |
890 | ||
891 | parser->job->ring = ring; | |
892 | ||
d38ceaf9 | 893 | if (ring->funcs->parse_cs) { |
4802ce11 | 894 | struct amdgpu_bo_va_mapping *m; |
3ccec53c | 895 | struct amdgpu_bo *aobj = NULL; |
4802ce11 CK |
896 | uint64_t offset; |
897 | uint8_t *kptr; | |
3ccec53c | 898 | |
4802ce11 CK |
899 | m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, |
900 | &aobj); | |
3ccec53c MO |
901 | if (!aobj) { |
902 | DRM_ERROR("IB va_start is invalid\n"); | |
903 | return -EINVAL; | |
d38ceaf9 AD |
904 | } |
905 | ||
4802ce11 CK |
906 | if ((chunk_ib->va_start + chunk_ib->ib_bytes) > |
907 | (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
908 | DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
909 | return -EINVAL; | |
910 | } | |
911 | ||
3ccec53c | 912 | /* the IB should be reserved at this point */ |
4802ce11 | 913 | r = amdgpu_bo_kmap(aobj, (void **)&kptr); |
d38ceaf9 | 914 | if (r) { |
d38ceaf9 AD |
915 | return r; |
916 | } | |
917 | ||
4802ce11 CK |
918 | offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; |
919 | kptr += chunk_ib->va_start - offset; | |
920 | ||
45088efc | 921 | r = amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib); |
d38ceaf9 AD |
922 | if (r) { |
923 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
924 | return r; |
925 | } | |
926 | ||
927 | memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
928 | amdgpu_bo_kunmap(aobj); | |
d38ceaf9 | 929 | } else { |
b07c60c0 | 930 | r = amdgpu_ib_get(adev, vm, 0, ib); |
d38ceaf9 AD |
931 | if (r) { |
932 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
933 | return r; |
934 | } | |
935 | ||
d38ceaf9 | 936 | } |
d38ceaf9 | 937 | |
45088efc | 938 | ib->gpu_addr = chunk_ib->va_start; |
3ccec53c | 939 | ib->length_dw = chunk_ib->ib_bytes / 4; |
de807f81 | 940 | ib->flags = chunk_ib->flags; |
d38ceaf9 AD |
941 | j++; |
942 | } | |
943 | ||
758ac17f | 944 | /* UVD & VCE fw doesn't support user fences */ |
b5f5acbc | 945 | if (parser->job->uf_addr && ( |
21cd942e CK |
946 | parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD || |
947 | parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE)) | |
758ac17f | 948 | return -EINVAL; |
d38ceaf9 AD |
949 | |
950 | return 0; | |
951 | } | |
952 | ||
2b48d323 CK |
953 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
954 | struct amdgpu_cs_parser *p) | |
955 | { | |
76a1ea61 | 956 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
2b48d323 CK |
957 | int i, j, r; |
958 | ||
2b48d323 CK |
959 | for (i = 0; i < p->nchunks; ++i) { |
960 | struct drm_amdgpu_cs_chunk_dep *deps; | |
961 | struct amdgpu_cs_chunk *chunk; | |
962 | unsigned num_deps; | |
963 | ||
964 | chunk = &p->chunks[i]; | |
965 | ||
966 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) | |
967 | continue; | |
968 | ||
969 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | |
970 | num_deps = chunk->length_dw * 4 / | |
971 | sizeof(struct drm_amdgpu_cs_chunk_dep); | |
972 | ||
973 | for (j = 0; j < num_deps; ++j) { | |
2b48d323 | 974 | struct amdgpu_ring *ring; |
76a1ea61 | 975 | struct amdgpu_ctx *ctx; |
21c16bf6 | 976 | struct fence *fence; |
2b48d323 CK |
977 | |
978 | r = amdgpu_cs_get_ring(adev, deps[j].ip_type, | |
979 | deps[j].ip_instance, | |
980 | deps[j].ring, &ring); | |
981 | if (r) | |
982 | return r; | |
983 | ||
76a1ea61 CK |
984 | ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); |
985 | if (ctx == NULL) | |
986 | return -EINVAL; | |
987 | ||
21c16bf6 CK |
988 | fence = amdgpu_ctx_get_fence(ctx, ring, |
989 | deps[j].handle); | |
990 | if (IS_ERR(fence)) { | |
991 | r = PTR_ERR(fence); | |
76a1ea61 | 992 | amdgpu_ctx_put(ctx); |
2b48d323 | 993 | return r; |
91e1a520 | 994 | |
21c16bf6 | 995 | } else if (fence) { |
e86f9cee CK |
996 | r = amdgpu_sync_fence(adev, &p->job->sync, |
997 | fence); | |
21c16bf6 CK |
998 | fence_put(fence); |
999 | amdgpu_ctx_put(ctx); | |
1000 | if (r) | |
1001 | return r; | |
1002 | } | |
2b48d323 CK |
1003 | } |
1004 | } | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
cd75dc68 CK |
1009 | static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, |
1010 | union drm_amdgpu_cs *cs) | |
1011 | { | |
b07c60c0 | 1012 | struct amdgpu_ring *ring = p->job->ring; |
92f25098 | 1013 | struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity; |
cd75dc68 | 1014 | struct amdgpu_job *job; |
e686941a | 1015 | int r; |
cd75dc68 | 1016 | |
50838c8c CK |
1017 | job = p->job; |
1018 | p->job = NULL; | |
cd75dc68 | 1019 | |
595a9cd6 | 1020 | r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp); |
e686941a | 1021 | if (r) { |
d71518b5 | 1022 | amdgpu_job_free(job); |
e686941a | 1023 | return r; |
cd75dc68 CK |
1024 | } |
1025 | ||
e686941a | 1026 | job->owner = p->filp; |
3aecd24c | 1027 | job->fence_ctx = entity->fence_context; |
595a9cd6 CK |
1028 | p->fence = fence_get(&job->base.s_fence->finished); |
1029 | cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence); | |
758ac17f | 1030 | job->uf_sequence = cs->out.handle; |
a5fb4ec2 | 1031 | amdgpu_job_free_resources(job); |
cd75dc68 CK |
1032 | |
1033 | trace_amdgpu_cs_ioctl(job); | |
1034 | amd_sched_entity_push_job(&job->base); | |
1035 | ||
1036 | return 0; | |
1037 | } | |
1038 | ||
049fc527 CZ |
1039 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
1040 | { | |
1041 | struct amdgpu_device *adev = dev->dev_private; | |
1042 | union drm_amdgpu_cs *cs = data; | |
7e52a81c | 1043 | struct amdgpu_cs_parser parser = {}; |
26a6980c CK |
1044 | bool reserved_buffers = false; |
1045 | int i, r; | |
049fc527 | 1046 | |
0c418f10 | 1047 | if (!adev->accel_working) |
049fc527 | 1048 | return -EBUSY; |
2b48d323 | 1049 | |
7e52a81c CK |
1050 | parser.adev = adev; |
1051 | parser.filp = filp; | |
1052 | ||
1053 | r = amdgpu_cs_parser_init(&parser, data); | |
d38ceaf9 | 1054 | if (r) { |
049fc527 | 1055 | DRM_ERROR("Failed to initialize parser !\n"); |
7e52a81c | 1056 | amdgpu_cs_parser_fini(&parser, r, false); |
d38ceaf9 AD |
1057 | r = amdgpu_cs_handle_lockup(adev, r); |
1058 | return r; | |
1059 | } | |
2a7d9bda | 1060 | r = amdgpu_cs_parser_bos(&parser, data); |
26a6980c CK |
1061 | if (r == -ENOMEM) |
1062 | DRM_ERROR("Not enough memory for command submission!\n"); | |
1063 | else if (r && r != -ERESTARTSYS) | |
1064 | DRM_ERROR("Failed to process the buffer list %d!\n", r); | |
1065 | else if (!r) { | |
1066 | reserved_buffers = true; | |
7e52a81c | 1067 | r = amdgpu_cs_ib_fill(adev, &parser); |
26a6980c CK |
1068 | } |
1069 | ||
1070 | if (!r) { | |
7e52a81c | 1071 | r = amdgpu_cs_dependencies(adev, &parser); |
26a6980c CK |
1072 | if (r) |
1073 | DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
1074 | } | |
1075 | ||
1076 | if (r) | |
1077 | goto out; | |
1078 | ||
50838c8c | 1079 | for (i = 0; i < parser.job->num_ibs; i++) |
7e52a81c | 1080 | trace_amdgpu_cs(&parser, i); |
26a6980c | 1081 | |
7e52a81c | 1082 | r = amdgpu_cs_ib_vm_chunk(adev, &parser); |
4fe63117 CZ |
1083 | if (r) |
1084 | goto out; | |
1085 | ||
4acabfe3 | 1086 | r = amdgpu_cs_submit(&parser, cs); |
d38ceaf9 | 1087 | |
d38ceaf9 | 1088 | out: |
7e52a81c | 1089 | amdgpu_cs_parser_fini(&parser, r, reserved_buffers); |
d38ceaf9 AD |
1090 | r = amdgpu_cs_handle_lockup(adev, r); |
1091 | return r; | |
1092 | } | |
1093 | ||
1094 | /** | |
1095 | * amdgpu_cs_wait_ioctl - wait for a command submission to finish | |
1096 | * | |
1097 | * @dev: drm device | |
1098 | * @data: data from userspace | |
1099 | * @filp: file private | |
1100 | * | |
1101 | * Wait for the command submission identified by handle to finish. | |
1102 | */ | |
1103 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, | |
1104 | struct drm_file *filp) | |
1105 | { | |
1106 | union drm_amdgpu_wait_cs *wait = data; | |
1107 | struct amdgpu_device *adev = dev->dev_private; | |
d38ceaf9 | 1108 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); |
03507c4f | 1109 | struct amdgpu_ring *ring = NULL; |
66b3cf2a | 1110 | struct amdgpu_ctx *ctx; |
21c16bf6 | 1111 | struct fence *fence; |
d38ceaf9 AD |
1112 | long r; |
1113 | ||
21c16bf6 CK |
1114 | r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, |
1115 | wait->in.ring, &ring); | |
1116 | if (r) | |
1117 | return r; | |
1118 | ||
66b3cf2a JZ |
1119 | ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); |
1120 | if (ctx == NULL) | |
1121 | return -EINVAL; | |
d38ceaf9 | 1122 | |
4b559c90 CZ |
1123 | fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); |
1124 | if (IS_ERR(fence)) | |
1125 | r = PTR_ERR(fence); | |
1126 | else if (fence) { | |
1127 | r = fence_wait_timeout(fence, true, timeout); | |
1128 | fence_put(fence); | |
1129 | } else | |
1130 | r = 1; | |
049fc527 | 1131 | |
66b3cf2a | 1132 | amdgpu_ctx_put(ctx); |
d38ceaf9 AD |
1133 | if (r < 0) |
1134 | return r; | |
1135 | ||
1136 | memset(wait, 0, sizeof(*wait)); | |
1137 | wait->out.status = (r == 0); | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | /** | |
1143 | * amdgpu_cs_find_bo_va - find bo_va for VM address | |
1144 | * | |
1145 | * @parser: command submission parser context | |
1146 | * @addr: VM address | |
1147 | * @bo: resulting BO of the mapping found | |
1148 | * | |
1149 | * Search the buffer objects in the command submission context for a certain | |
1150 | * virtual memory address. Returns allocation structure when found, NULL | |
1151 | * otherwise. | |
1152 | */ | |
1153 | struct amdgpu_bo_va_mapping * | |
1154 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
1155 | uint64_t addr, struct amdgpu_bo **bo) | |
1156 | { | |
d38ceaf9 | 1157 | struct amdgpu_bo_va_mapping *mapping; |
15486fd2 CK |
1158 | unsigned i; |
1159 | ||
1160 | if (!parser->bo_list) | |
1161 | return NULL; | |
d38ceaf9 AD |
1162 | |
1163 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
1164 | ||
15486fd2 CK |
1165 | for (i = 0; i < parser->bo_list->num_entries; i++) { |
1166 | struct amdgpu_bo_list_entry *lobj; | |
1167 | ||
1168 | lobj = &parser->bo_list->array[i]; | |
1169 | if (!lobj->bo_va) | |
d38ceaf9 AD |
1170 | continue; |
1171 | ||
15486fd2 | 1172 | list_for_each_entry(mapping, &lobj->bo_va->valids, list) { |
7fc11959 CK |
1173 | if (mapping->it.start > addr || |
1174 | addr > mapping->it.last) | |
1175 | continue; | |
1176 | ||
15486fd2 | 1177 | *bo = lobj->bo_va->bo; |
7fc11959 CK |
1178 | return mapping; |
1179 | } | |
1180 | ||
15486fd2 | 1181 | list_for_each_entry(mapping, &lobj->bo_va->invalids, list) { |
d38ceaf9 AD |
1182 | if (mapping->it.start > addr || |
1183 | addr > mapping->it.last) | |
1184 | continue; | |
1185 | ||
15486fd2 | 1186 | *bo = lobj->bo_va->bo; |
d38ceaf9 AD |
1187 | return mapping; |
1188 | } | |
1189 | } | |
1190 | ||
1191 | return NULL; | |
1192 | } | |
c855e250 CK |
1193 | |
1194 | /** | |
1195 | * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM | |
1196 | * | |
1197 | * @parser: command submission parser context | |
1198 | * | |
1199 | * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM. | |
1200 | */ | |
1201 | int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser) | |
1202 | { | |
1203 | unsigned i; | |
1204 | int r; | |
1205 | ||
1206 | if (!parser->bo_list) | |
1207 | return 0; | |
1208 | ||
1209 | for (i = 0; i < parser->bo_list->num_entries; i++) { | |
1210 | struct amdgpu_bo *bo = parser->bo_list->array[i].robj; | |
1211 | ||
bb990bb0 | 1212 | r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); |
c855e250 CK |
1213 | if (unlikely(r)) |
1214 | return r; | |
03f48dd5 CK |
1215 | |
1216 | if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) | |
1217 | continue; | |
1218 | ||
1219 | bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; | |
1220 | amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains); | |
1221 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); | |
1222 | if (unlikely(r)) | |
1223 | return r; | |
c855e250 CK |
1224 | } |
1225 | ||
1226 | return 0; | |
1227 | } |